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a5fcccbc FL |
1 | /* |
2 | * Copyright (C) 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /dts-v1/; | |
10 | ||
a5fcccbc FL |
11 | #include "imx6ul.dtsi" |
12 | ||
13 | / { | |
14 | model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; | |
15 | compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; | |
16 | ||
17 | chosen { | |
18 | stdout-path = &uart1; | |
19 | }; | |
20 | ||
21 | memory { | |
22 | reg = <0x80000000 0x20000000>; | |
23 | }; | |
24 | ||
e5adcb7c FE |
25 | backlight { |
26 | compatible = "pwm-backlight"; | |
27 | pwms = <&pwm1 0 5000000>; | |
28 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
29 | default-brightness-level = <6>; | |
30 | status = "okay"; | |
31 | }; | |
32 | ||
a5fcccbc FL |
33 | regulators { |
34 | compatible = "simple-bus"; | |
35 | #address-cells = <1>; | |
36 | #size-cells = <0>; | |
37 | ||
38 | reg_sd1_vmmc: sd1_regulator { | |
39 | compatible = "regulator-fixed"; | |
40 | regulator-name = "VSD_3V3"; | |
41 | regulator-min-microvolt = <3300000>; | |
42 | regulator-max-microvolt = <3300000>; | |
43 | gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; | |
44 | enable-active-high; | |
45 | }; | |
46 | }; | |
bf3251e1 FE |
47 | |
48 | sound { | |
49 | compatible = "simple-audio-card"; | |
50 | simple-audio-card,name = "mx6ul-wm8960"; | |
51 | simple-audio-card,format = "i2s"; | |
52 | simple-audio-card,bitclock-master = <&dailink_master>; | |
53 | simple-audio-card,frame-master = <&dailink_master>; | |
54 | simple-audio-card,widgets = | |
55 | "Microphone", "Mic Jack", | |
56 | "Line", "Line In", | |
57 | "Line", "Line Out", | |
58 | "Speaker", "Speaker", | |
59 | "Headphone", "Headphone Jack"; | |
60 | simple-audio-card,routing = | |
61 | "Headphone Jack", "HP_L", | |
62 | "Headphone Jack", "HP_R", | |
63 | "Speaker", "SPK_LP", | |
64 | "Speaker", "SPK_LN", | |
65 | "Speaker", "SPK_RP", | |
66 | "Speaker", "SPK_RN", | |
67 | "LINPUT1", "Mic Jack", | |
68 | "LINPUT3", "Mic Jack", | |
69 | "RINPUT1", "Mic Jack", | |
70 | "RINPUT2", "Mic Jack"; | |
71 | ||
72 | simple-audio-card,cpu { | |
73 | sound-dai = <&sai2>; | |
74 | }; | |
75 | ||
76 | dailink_master: simple-audio-card,codec { | |
77 | sound-dai = <&codec>; | |
78 | clocks = <&clks IMX6UL_CLK_SAI2>; | |
79 | }; | |
80 | }; | |
81 | }; | |
82 | ||
83 | &clks { | |
84 | assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; | |
85 | assigned-clock-rates = <786432000>; | |
a5fcccbc FL |
86 | }; |
87 | ||
bf3251e1 FE |
88 | &i2c2 { |
89 | clock_frequency = <100000>; | |
90 | pinctrl-names = "default"; | |
91 | pinctrl-0 = <&pinctrl_i2c2>; | |
92 | status = "okay"; | |
93 | ||
94 | codec: wm8960@1a { | |
95 | #sound-dai-cells = <0>; | |
96 | compatible = "wlf,wm8960"; | |
97 | reg = <0x1a>; | |
98 | wlf,shared-lrclk; | |
99 | }; | |
100 | }; | |
101 | ||
5e8cdb01 FD |
102 | &fec1 { |
103 | pinctrl-names = "default"; | |
104 | pinctrl-0 = <&pinctrl_enet1>; | |
105 | phy-mode = "rmii"; | |
106 | phy-handle = <ðphy0>; | |
107 | status = "okay"; | |
108 | }; | |
109 | ||
110 | &fec2 { | |
111 | pinctrl-names = "default"; | |
112 | pinctrl-0 = <&pinctrl_enet2>; | |
113 | phy-mode = "rmii"; | |
114 | phy-handle = <ðphy1>; | |
115 | status = "okay"; | |
116 | ||
117 | mdio { | |
118 | #address-cells = <1>; | |
119 | #size-cells = <0>; | |
120 | ||
121 | ethphy0: ethernet-phy@2 { | |
122 | reg = <2>; | |
e6f4292a LC |
123 | micrel,led-mode = <1>; |
124 | clocks = <&clks IMX6UL_CLK_ENET_REF>; | |
125 | clock-names = "rmii-ref"; | |
5e8cdb01 FD |
126 | }; |
127 | ||
128 | ethphy1: ethernet-phy@1 { | |
129 | reg = <1>; | |
e6f4292a LC |
130 | micrel,led-mode = <1>; |
131 | clocks = <&clks IMX6UL_CLK_ENET2_REF>; | |
132 | clock-names = "rmii-ref"; | |
5e8cdb01 FD |
133 | }; |
134 | }; | |
135 | }; | |
136 | ||
e5adcb7c FE |
137 | |
138 | &lcdif { | |
139 | pinctrl-names = "default"; | |
140 | pinctrl-0 = <&pinctrl_lcdif_dat | |
141 | &pinctrl_lcdif_ctrl>; | |
142 | display = <&display0>; | |
143 | status = "okay"; | |
144 | ||
145 | display0: display { | |
146 | bits-per-pixel = <16>; | |
147 | bus-width = <24>; | |
148 | ||
149 | display-timings { | |
150 | native-mode = <&timing0>; | |
151 | ||
152 | timing0: timing0 { | |
153 | clock-frequency = <9200000>; | |
154 | hactive = <480>; | |
155 | vactive = <272>; | |
156 | hfront-porch = <8>; | |
157 | hback-porch = <4>; | |
158 | hsync-len = <41>; | |
159 | vback-porch = <2>; | |
160 | vfront-porch = <4>; | |
161 | vsync-len = <10>; | |
162 | hsync-active = <0>; | |
163 | vsync-active = <0>; | |
164 | de-active = <1>; | |
165 | pixelclk-active = <0>; | |
166 | }; | |
167 | }; | |
168 | }; | |
169 | }; | |
170 | ||
171 | &pwm1 { | |
172 | pinctrl-names = "default"; | |
173 | pinctrl-0 = <&pinctrl_pwm1>; | |
174 | status = "okay"; | |
175 | }; | |
176 | ||
5ff807a5 FL |
177 | &qspi { |
178 | pinctrl-names = "default"; | |
179 | pinctrl-0 = <&pinctrl_qspi>; | |
180 | status = "okay"; | |
181 | ||
182 | flash0: n25q256a@0 { | |
183 | #address-cells = <1>; | |
184 | #size-cells = <1>; | |
185 | compatible = "micron,n25q256a"; | |
186 | spi-max-frequency = <29000000>; | |
187 | reg = <0>; | |
188 | }; | |
189 | }; | |
190 | ||
bf3251e1 FE |
191 | &sai2 { |
192 | pinctrl-names = "default"; | |
193 | pinctrl-0 = <&pinctrl_sai2>; | |
194 | assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, | |
195 | <&clks IMX6UL_CLK_SAI2>; | |
196 | assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; | |
197 | assigned-clock-rates = <0>, <12288000>; | |
d805adb2 | 198 | fsl,sai-mclk-direction-output; |
bf3251e1 FE |
199 | status = "okay"; |
200 | }; | |
201 | ||
ab0a05d8 AH |
202 | &snvs_poweroff { |
203 | status = "okay"; | |
204 | }; | |
205 | ||
d272c07b HC |
206 | &tsc { |
207 | pinctrl-names = "default"; | |
208 | pinctrl-0 = <&pinctrl_tsc>; | |
209 | xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; | |
210 | measure-delay-time = <0xffff>; | |
211 | pre-charge-time = <0xfff>; | |
212 | status = "okay"; | |
213 | }; | |
214 | ||
a5fcccbc FL |
215 | &uart1 { |
216 | pinctrl-names = "default"; | |
217 | pinctrl-0 = <&pinctrl_uart1>; | |
218 | status = "okay"; | |
219 | }; | |
220 | ||
221 | &uart2 { | |
222 | pinctrl-names = "default"; | |
223 | pinctrl-0 = <&pinctrl_uart2>; | |
2e7c416c | 224 | uart-has-rtscts; |
a5fcccbc FL |
225 | status = "okay"; |
226 | }; | |
227 | ||
cad2cb69 | 228 | &usbotg1 { |
a16fe2c1 | 229 | dr_mode = "otg"; |
cad2cb69 FL |
230 | status = "okay"; |
231 | }; | |
232 | ||
233 | &usbotg2 { | |
234 | dr_mode = "host"; | |
235 | disable-over-current; | |
236 | status = "okay"; | |
237 | }; | |
238 | ||
901725b7 PC |
239 | &usbphy1 { |
240 | fsl,tx-d-cal = <106>; | |
241 | }; | |
242 | ||
243 | &usbphy2 { | |
244 | fsl,tx-d-cal = <106>; | |
245 | }; | |
246 | ||
a5fcccbc FL |
247 | &usdhc1 { |
248 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
249 | pinctrl-0 = <&pinctrl_usdhc1>; | |
250 | pinctrl-1 = <&pinctrl_usdhc1_100mhz>; | |
251 | pinctrl-2 = <&pinctrl_usdhc1_200mhz>; | |
252 | cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; | |
253 | keep-power-in-suspend; | |
26cefdd1 | 254 | wakeup-source; |
a5fcccbc FL |
255 | vmmc-supply = <®_sd1_vmmc>; |
256 | status = "okay"; | |
257 | }; | |
258 | ||
259 | &usdhc2 { | |
260 | pinctrl-names = "default"; | |
261 | pinctrl-0 = <&pinctrl_usdhc2>; | |
262 | no-1-8-v; | |
263 | keep-power-in-suspend; | |
26cefdd1 | 264 | wakeup-source; |
a5fcccbc FL |
265 | status = "okay"; |
266 | }; | |
267 | ||
50e02998 FE |
268 | &wdog1 { |
269 | pinctrl-names = "default"; | |
270 | pinctrl-0 = <&pinctrl_wdog>; | |
271 | fsl,ext-reset-output; | |
272 | }; | |
273 | ||
a5fcccbc FL |
274 | &iomuxc { |
275 | pinctrl-names = "default"; | |
276 | ||
277 | pinctrl_csi1: csi1grp { | |
278 | fsl,pins = < | |
279 | MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 | |
280 | MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 | |
281 | MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 | |
282 | MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 | |
283 | MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 | |
284 | MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 | |
285 | MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 | |
286 | MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 | |
287 | MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 | |
288 | MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 | |
289 | MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 | |
290 | MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 | |
291 | >; | |
292 | }; | |
293 | ||
294 | pinctrl_enet1: enet1grp { | |
295 | fsl,pins = < | |
296 | MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 | |
297 | MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 | |
298 | MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 | |
299 | MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 | |
300 | MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 | |
301 | MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 | |
302 | MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 | |
303 | MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 | |
304 | >; | |
305 | }; | |
306 | ||
307 | pinctrl_enet2: enet2grp { | |
308 | fsl,pins = < | |
309 | MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 | |
310 | MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 | |
311 | MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 | |
312 | MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 | |
313 | MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 | |
314 | MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 | |
315 | MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 | |
316 | MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 | |
317 | MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 | |
318 | MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 | |
319 | MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 | |
320 | >; | |
321 | }; | |
322 | ||
323 | pinctrl_flexcan1: flexcan1grp{ | |
324 | fsl,pins = < | |
325 | MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 | |
326 | MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 | |
327 | >; | |
328 | }; | |
329 | ||
330 | pinctrl_flexcan2: flexcan2grp{ | |
331 | fsl,pins = < | |
332 | MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 | |
333 | MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 | |
334 | >; | |
335 | }; | |
336 | ||
337 | pinctrl_i2c1: i2c1grp { | |
338 | fsl,pins = < | |
339 | MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 | |
340 | MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 | |
341 | >; | |
342 | }; | |
343 | ||
344 | pinctrl_i2c2: i2c2grp { | |
345 | fsl,pins = < | |
346 | MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 | |
347 | MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 | |
348 | >; | |
349 | }; | |
350 | ||
351 | pinctrl_lcdif_dat: lcdifdatgrp { | |
352 | fsl,pins = < | |
353 | MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 | |
354 | MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 | |
355 | MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 | |
356 | MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 | |
357 | MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 | |
358 | MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 | |
359 | MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 | |
360 | MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 | |
361 | MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 | |
362 | MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 | |
363 | MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 | |
364 | MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 | |
365 | MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 | |
366 | MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 | |
367 | MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 | |
368 | MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 | |
369 | MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 | |
370 | MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 | |
371 | MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 | |
372 | MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 | |
373 | MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 | |
374 | MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 | |
375 | MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 | |
376 | MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 | |
377 | >; | |
378 | }; | |
379 | ||
380 | pinctrl_lcdif_ctrl: lcdifctrlgrp { | |
381 | fsl,pins = < | |
382 | MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 | |
383 | MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 | |
384 | MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 | |
385 | MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 | |
386 | /* used for lcd reset */ | |
387 | MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 | |
388 | >; | |
389 | }; | |
390 | ||
5ff807a5 FL |
391 | pinctrl_qspi: qspigrp { |
392 | fsl,pins = < | |
393 | MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 | |
394 | MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 | |
395 | MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 | |
396 | MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 | |
397 | MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 | |
398 | MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 | |
399 | >; | |
400 | }; | |
401 | ||
bf3251e1 FE |
402 | pinctrl_sai2: sai2grp { |
403 | fsl,pins = < | |
404 | MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 | |
405 | MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 | |
406 | MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 | |
407 | MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 | |
408 | MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 | |
409 | MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 | |
410 | >; | |
411 | }; | |
412 | ||
a5fcccbc FL |
413 | pinctrl_pwm1: pwm1grp { |
414 | fsl,pins = < | |
415 | MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 | |
416 | >; | |
417 | }; | |
418 | ||
419 | pinctrl_sim2: sim2grp { | |
420 | fsl,pins = < | |
421 | MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 | |
422 | MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 | |
423 | MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 | |
424 | MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 | |
425 | MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 | |
426 | MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 | |
427 | >; | |
428 | }; | |
429 | ||
d272c07b HC |
430 | pinctrl_tsc: tscgrp { |
431 | fsl,pins = < | |
432 | MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 | |
433 | MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 | |
434 | MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 | |
435 | MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 | |
436 | >; | |
437 | }; | |
438 | ||
a5fcccbc FL |
439 | pinctrl_uart1: uart1grp { |
440 | fsl,pins = < | |
441 | MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 | |
442 | MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 | |
443 | >; | |
444 | }; | |
445 | ||
446 | pinctrl_uart2: uart2grp { | |
447 | fsl,pins = < | |
448 | MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 | |
449 | MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 | |
450 | MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 | |
451 | MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 | |
452 | >; | |
453 | }; | |
454 | ||
455 | pinctrl_usdhc1: usdhc1grp { | |
456 | fsl,pins = < | |
457 | MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 | |
458 | MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 | |
459 | MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 | |
460 | MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 | |
461 | MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 | |
462 | MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 | |
463 | MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ | |
464 | MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ | |
465 | MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ | |
466 | >; | |
467 | }; | |
468 | ||
469 | pinctrl_usdhc1_100mhz: usdhc1grp100mhz { | |
470 | fsl,pins = < | |
471 | MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 | |
472 | MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 | |
473 | MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 | |
474 | MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 | |
475 | MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 | |
476 | MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 | |
477 | ||
478 | >; | |
479 | }; | |
480 | ||
481 | pinctrl_usdhc1_200mhz: usdhc1grp200mhz { | |
482 | fsl,pins = < | |
483 | MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 | |
484 | MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 | |
485 | MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 | |
486 | MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 | |
487 | MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 | |
488 | MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 | |
489 | >; | |
490 | }; | |
491 | ||
492 | pinctrl_usdhc2: usdhc2grp { | |
493 | fsl,pins = < | |
494 | MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 | |
495 | MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 | |
496 | MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 | |
497 | MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 | |
498 | MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 | |
499 | MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 | |
500 | >; | |
501 | }; | |
50e02998 FE |
502 | |
503 | pinctrl_wdog: wdoggrp { | |
504 | fsl,pins = < | |
505 | MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 | |
506 | >; | |
507 | }; | |
a5fcccbc | 508 | }; |