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a5fcccbc FL |
1 | /* |
2 | * Copyright (C) 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /dts-v1/; | |
10 | ||
a5fcccbc FL |
11 | #include "imx6ul.dtsi" |
12 | ||
13 | / { | |
14 | model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; | |
15 | compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; | |
16 | ||
17 | chosen { | |
18 | stdout-path = &uart1; | |
19 | }; | |
20 | ||
21 | memory { | |
22 | reg = <0x80000000 0x20000000>; | |
23 | }; | |
24 | ||
25 | regulators { | |
26 | compatible = "simple-bus"; | |
27 | #address-cells = <1>; | |
28 | #size-cells = <0>; | |
29 | ||
30 | reg_sd1_vmmc: sd1_regulator { | |
31 | compatible = "regulator-fixed"; | |
32 | regulator-name = "VSD_3V3"; | |
33 | regulator-min-microvolt = <3300000>; | |
34 | regulator-max-microvolt = <3300000>; | |
35 | gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; | |
36 | enable-active-high; | |
37 | }; | |
38 | }; | |
39 | }; | |
40 | ||
41 | &cpu0 { | |
42 | arm-supply = <®_arm>; | |
43 | soc-supply = <®_soc>; | |
44 | }; | |
45 | ||
5e8cdb01 FD |
46 | &fec1 { |
47 | pinctrl-names = "default"; | |
48 | pinctrl-0 = <&pinctrl_enet1>; | |
49 | phy-mode = "rmii"; | |
50 | phy-handle = <ðphy0>; | |
51 | status = "okay"; | |
52 | }; | |
53 | ||
54 | &fec2 { | |
55 | pinctrl-names = "default"; | |
56 | pinctrl-0 = <&pinctrl_enet2>; | |
57 | phy-mode = "rmii"; | |
58 | phy-handle = <ðphy1>; | |
59 | status = "okay"; | |
60 | ||
61 | mdio { | |
62 | #address-cells = <1>; | |
63 | #size-cells = <0>; | |
64 | ||
65 | ethphy0: ethernet-phy@2 { | |
66 | reg = <2>; | |
67 | }; | |
68 | ||
69 | ethphy1: ethernet-phy@1 { | |
70 | reg = <1>; | |
71 | }; | |
72 | }; | |
73 | }; | |
74 | ||
5ff807a5 FL |
75 | &qspi { |
76 | pinctrl-names = "default"; | |
77 | pinctrl-0 = <&pinctrl_qspi>; | |
78 | status = "okay"; | |
79 | ||
80 | flash0: n25q256a@0 { | |
81 | #address-cells = <1>; | |
82 | #size-cells = <1>; | |
83 | compatible = "micron,n25q256a"; | |
84 | spi-max-frequency = <29000000>; | |
85 | reg = <0>; | |
86 | }; | |
87 | }; | |
88 | ||
ab0a05d8 AH |
89 | &snvs_poweroff { |
90 | status = "okay"; | |
91 | }; | |
92 | ||
d272c07b HC |
93 | &tsc { |
94 | pinctrl-names = "default"; | |
95 | pinctrl-0 = <&pinctrl_tsc>; | |
96 | xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; | |
97 | measure-delay-time = <0xffff>; | |
98 | pre-charge-time = <0xfff>; | |
99 | status = "okay"; | |
100 | }; | |
101 | ||
a5fcccbc FL |
102 | &uart1 { |
103 | pinctrl-names = "default"; | |
104 | pinctrl-0 = <&pinctrl_uart1>; | |
105 | status = "okay"; | |
106 | }; | |
107 | ||
108 | &uart2 { | |
109 | pinctrl-names = "default"; | |
110 | pinctrl-0 = <&pinctrl_uart2>; | |
111 | fsl,uart-has-rtscts; | |
112 | status = "okay"; | |
113 | }; | |
114 | ||
cad2cb69 FL |
115 | &usbotg1 { |
116 | dr_mode = "peripheral"; | |
117 | status = "okay"; | |
118 | }; | |
119 | ||
120 | &usbotg2 { | |
121 | dr_mode = "host"; | |
122 | disable-over-current; | |
123 | status = "okay"; | |
124 | }; | |
125 | ||
a5fcccbc FL |
126 | &usdhc1 { |
127 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
128 | pinctrl-0 = <&pinctrl_usdhc1>; | |
129 | pinctrl-1 = <&pinctrl_usdhc1_100mhz>; | |
130 | pinctrl-2 = <&pinctrl_usdhc1_200mhz>; | |
131 | cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; | |
132 | keep-power-in-suspend; | |
26cefdd1 | 133 | wakeup-source; |
a5fcccbc FL |
134 | vmmc-supply = <®_sd1_vmmc>; |
135 | status = "okay"; | |
136 | }; | |
137 | ||
138 | &usdhc2 { | |
139 | pinctrl-names = "default"; | |
140 | pinctrl-0 = <&pinctrl_usdhc2>; | |
141 | no-1-8-v; | |
142 | keep-power-in-suspend; | |
26cefdd1 | 143 | wakeup-source; |
a5fcccbc FL |
144 | status = "okay"; |
145 | }; | |
146 | ||
147 | &iomuxc { | |
148 | pinctrl-names = "default"; | |
149 | ||
150 | pinctrl_csi1: csi1grp { | |
151 | fsl,pins = < | |
152 | MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 | |
153 | MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 | |
154 | MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 | |
155 | MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 | |
156 | MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 | |
157 | MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 | |
158 | MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 | |
159 | MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 | |
160 | MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 | |
161 | MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 | |
162 | MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 | |
163 | MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 | |
164 | >; | |
165 | }; | |
166 | ||
167 | pinctrl_enet1: enet1grp { | |
168 | fsl,pins = < | |
169 | MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 | |
170 | MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 | |
171 | MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 | |
172 | MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 | |
173 | MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 | |
174 | MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 | |
175 | MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 | |
176 | MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 | |
177 | >; | |
178 | }; | |
179 | ||
180 | pinctrl_enet2: enet2grp { | |
181 | fsl,pins = < | |
182 | MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 | |
183 | MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 | |
184 | MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 | |
185 | MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 | |
186 | MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 | |
187 | MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 | |
188 | MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 | |
189 | MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 | |
190 | MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 | |
191 | MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 | |
192 | MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 | |
193 | >; | |
194 | }; | |
195 | ||
196 | pinctrl_flexcan1: flexcan1grp{ | |
197 | fsl,pins = < | |
198 | MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 | |
199 | MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 | |
200 | >; | |
201 | }; | |
202 | ||
203 | pinctrl_flexcan2: flexcan2grp{ | |
204 | fsl,pins = < | |
205 | MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 | |
206 | MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 | |
207 | >; | |
208 | }; | |
209 | ||
210 | pinctrl_i2c1: i2c1grp { | |
211 | fsl,pins = < | |
212 | MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 | |
213 | MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 | |
214 | >; | |
215 | }; | |
216 | ||
217 | pinctrl_i2c2: i2c2grp { | |
218 | fsl,pins = < | |
219 | MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 | |
220 | MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 | |
221 | >; | |
222 | }; | |
223 | ||
224 | pinctrl_lcdif_dat: lcdifdatgrp { | |
225 | fsl,pins = < | |
226 | MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 | |
227 | MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 | |
228 | MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 | |
229 | MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 | |
230 | MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 | |
231 | MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 | |
232 | MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 | |
233 | MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 | |
234 | MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 | |
235 | MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 | |
236 | MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 | |
237 | MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 | |
238 | MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 | |
239 | MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 | |
240 | MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 | |
241 | MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 | |
242 | MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 | |
243 | MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 | |
244 | MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 | |
245 | MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 | |
246 | MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 | |
247 | MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 | |
248 | MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 | |
249 | MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 | |
250 | >; | |
251 | }; | |
252 | ||
253 | pinctrl_lcdif_ctrl: lcdifctrlgrp { | |
254 | fsl,pins = < | |
255 | MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 | |
256 | MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 | |
257 | MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 | |
258 | MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 | |
259 | /* used for lcd reset */ | |
260 | MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 | |
261 | >; | |
262 | }; | |
263 | ||
5ff807a5 FL |
264 | pinctrl_qspi: qspigrp { |
265 | fsl,pins = < | |
266 | MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 | |
267 | MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 | |
268 | MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 | |
269 | MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 | |
270 | MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 | |
271 | MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 | |
272 | >; | |
273 | }; | |
274 | ||
a5fcccbc FL |
275 | pinctrl_pwm1: pwm1grp { |
276 | fsl,pins = < | |
277 | MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 | |
278 | >; | |
279 | }; | |
280 | ||
281 | pinctrl_sim2: sim2grp { | |
282 | fsl,pins = < | |
283 | MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 | |
284 | MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 | |
285 | MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 | |
286 | MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 | |
287 | MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 | |
288 | MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 | |
289 | >; | |
290 | }; | |
291 | ||
d272c07b HC |
292 | pinctrl_tsc: tscgrp { |
293 | fsl,pins = < | |
294 | MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 | |
295 | MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 | |
296 | MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 | |
297 | MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 | |
298 | >; | |
299 | }; | |
300 | ||
a5fcccbc FL |
301 | pinctrl_uart1: uart1grp { |
302 | fsl,pins = < | |
303 | MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 | |
304 | MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 | |
305 | >; | |
306 | }; | |
307 | ||
308 | pinctrl_uart2: uart2grp { | |
309 | fsl,pins = < | |
310 | MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 | |
311 | MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 | |
312 | MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 | |
313 | MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 | |
314 | >; | |
315 | }; | |
316 | ||
317 | pinctrl_usdhc1: usdhc1grp { | |
318 | fsl,pins = < | |
319 | MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 | |
320 | MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 | |
321 | MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 | |
322 | MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 | |
323 | MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 | |
324 | MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 | |
325 | MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ | |
326 | MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ | |
327 | MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ | |
328 | >; | |
329 | }; | |
330 | ||
331 | pinctrl_usdhc1_100mhz: usdhc1grp100mhz { | |
332 | fsl,pins = < | |
333 | MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 | |
334 | MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 | |
335 | MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 | |
336 | MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 | |
337 | MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 | |
338 | MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 | |
339 | ||
340 | >; | |
341 | }; | |
342 | ||
343 | pinctrl_usdhc1_200mhz: usdhc1grp200mhz { | |
344 | fsl,pins = < | |
345 | MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 | |
346 | MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 | |
347 | MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 | |
348 | MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 | |
349 | MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 | |
350 | MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 | |
351 | >; | |
352 | }; | |
353 | ||
354 | pinctrl_usdhc2: usdhc2grp { | |
355 | fsl,pins = < | |
356 | MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 | |
357 | MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 | |
358 | MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 | |
359 | MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 | |
360 | MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 | |
361 | MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 | |
362 | >; | |
363 | }; | |
364 | }; |