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ARM: dts: imx6ul: Enable SNVS power key according to board design
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx6ul.dtsi
CommitLineData
241f76b2
FE		 1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2015 Freescale Semiconductor, Inc.
a5fcccbc
FL		 4
5#include <dt-bindings/clock/imx6ul-clock.h>
6#include <dt-bindings/gpio/gpio.h>
89435fea 7#include <dt-bindings/input/input.h>
a5fcccbc
FL		 8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include "imx6ul-pinfunc.h"
a5fcccbc
FL		 10
11/ {
7f107887
FE		 12 #address-cells = <1>;
13 #size-cells = <1>;
a971c554
FE		 14 /*
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
a971c554
FE		 18 */
19 chosen {};
7f107887 20
a5fcccbc 21 aliases {
01f3dc7d
FD		 22 ethernet0 = &fec1;
23 ethernet1 = &fec2;
a5fcccbc
FL		 24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
32 i2c3 = &i2c4;
33 mmc0 = &usdhc1;
34 mmc1 = &usdhc2;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 serial4 = &uart5;
40 serial5 = &uart6;
41 serial6 = &uart7;
42 serial7 = &uart8;
fb3239ff
FE		 43 sai1 = &sai1;
44 sai2 = &sai2;
45 sai3 = &sai3;
a5fcccbc
FL		 46 spi0 = &ecspi1;
47 spi1 = &ecspi2;
48 spi2 = &ecspi3;
49 spi3 = &ecspi4;
50 usbphy0 = &usbphy1;
51 usbphy1 = &usbphy2;
52 };
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu0: cpu@0 {
59 compatible = "arm,cortex-a7";
60 device_type = "cpu";
61 reg = <0>;
43f1322b 62 clock-frequency = <696000000>;
a5fcccbc 63 clock-latency = <61036>; /* two CLK32 periods */
f3d80deb 64 #cooling-cells = <2>;
a5fcccbc
FL		 65 operating-points = <
66 /* kHz uV */
c9619bb2 67 696000 1275000
f7084446
FE		 68 528000 1175000
69 396000 1025000
70 198000 950000
a5fcccbc
FL		 71 >;
72 fsl,soc-operating-points = <
73 /* KHz uV */
c9619bb2 74 696000 1275000
f7084446
FE		 75 528000 1175000
76 396000 1175000
77 198000 1175000
a5fcccbc
FL		 78 >;
79 clocks = <&clks IMX6UL_CLK_ARM>,
80 <&clks IMX6UL_CLK_PLL2_BUS>,
81 <&clks IMX6UL_CLK_PLL2_PFD2>,
82 <&clks IMX6UL_CA7_SECONDARY_SEL>,
83 <&clks IMX6UL_CLK_STEP>,
84 <&clks IMX6UL_CLK_PLL1_SW>,
4a7459bc 85 <&clks IMX6UL_CLK_PLL1_SYS>;
a5fcccbc
FL		 86 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
87 "secondary_sel", "step", "pll1_sw",
4a7459bc 88 "pll1_sys";
a5fcccbc
FL		 89 arm-supply = <&reg_arm>;
90 soc-supply = <&reg_soc>;
92f0eb08
AH		 91 nvmem-cells = <&cpu_speed_grade>;
92 nvmem-cell-names = "speed_grade";
a5fcccbc
FL		 93 };
94 };
95
efb9adb2 96 intc: interrupt-controller@a01000 {
387720c9 97 compatible = "arm,gic-400", "arm,cortex-a7-gic";
0c29339d 98 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
a5fcccbc
FL		 99 #interrupt-cells = <3>;
100 interrupt-controller;
8dc72265 101 interrupt-parent = <&intc>;
a5fcccbc 102 reg = <0x00a01000 0x1000>,
387720c9 103 <0x00a02000 0x2000>,
a5fcccbc
FL		 104 <0x00a04000 0x2000>,
105 <0x00a06000 0x2000>;
106 };
107
cff1ce71
SA		 108 timer {
109 compatible = "arm,armv7-timer";
0c29339d
FE		 110 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
111 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
cff1ce71
SA		 114 interrupt-parent = <&intc>;
115 status = "disabled";
116 };
117
a5fcccbc
FL		 118 ckil: clock-cli {
119 compatible = "fixed-clock";
120 #clock-cells = <0>;
121 clock-frequency = <32768>;
122 clock-output-names = "ckil";
123 };
124
125 osc: clock-osc {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <24000000>;
129 clock-output-names = "osc";
130 };
131
132 ipp_di0: clock-di0 {
133 compatible = "fixed-clock";
134 #clock-cells = <0>;
135 clock-frequency = <0>;
136 clock-output-names = "ipp_di0";
137 };
138
139 ipp_di1: clock-di1 {
140 compatible = "fixed-clock";
141 #clock-cells = <0>;
142 clock-frequency = <0>;
143 clock-output-names = "ipp_di1";
144 };
145
1e989603
FE		 146 tempmon: tempmon {
147 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
148 interrupt-parent = <&gpc>;
149 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
150 fsl,tempmon = <&anatop>;
151 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
152 nvmem-cell-names = "calib", "temp_grade";
153 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
154 };
155
156 pmu {
157 compatible = "arm,cortex-a7-pmu";
158 interrupt-parent = <&gpc>;
159 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1e989603
FE		 160 };
161
a5fcccbc
FL		 162 soc {
163 #address-cells = <1>;
164 #size-cells = <1>;
165 compatible = "simple-bus";
18619ff5 166 interrupt-parent = <&gpc>;
a5fcccbc
FL		 167 ranges;
168
efb9adb2 169 ocram: sram@900000 {
322d09d6
AH		 170 compatible = "mmio-sram";
171 reg = <0x00900000 0x20000>;
172 };
173
efb9adb2 174 dma_apbh: dma-apbh@1804000 {
7d1cd297
LW		 175 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
176 reg = <0x01804000 0x2000>;
177 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
178 <0 13 IRQ_TYPE_LEVEL_HIGH>,
179 <0 13 IRQ_TYPE_LEVEL_HIGH>,
180 <0 13 IRQ_TYPE_LEVEL_HIGH>;
181 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
182 #dma-cells = <1>;
183 dma-channels = <4>;
184 clocks = <&clks IMX6UL_CLK_APBHDMA>;
185 };
186
81c0039b 187 gpmi: gpmi-nand@1806000 {
7d1cd297
LW		 188 compatible = "fsl,imx6q-gpmi-nand";
189 #address-cells = <1>;
190 #size-cells = <1>;
191 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
192 reg-names = "gpmi-nand", "bch";
193 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
194 interrupt-names = "bch";
195 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
196 <&clks IMX6UL_CLK_GPMI_APB>,
197 <&clks IMX6UL_CLK_GPMI_BCH>,
198 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
199 <&clks IMX6UL_CLK_PER_BCH>;
200 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
201 "gpmi_bch_apb", "per1_bch";
202 dmas = <&dma_apbh 0>;
203 dma-names = "rx-tx";
204 status = "disabled";
205 };
206
efb9adb2 207 aips1: aips-bus@2000000 {
a5fcccbc
FL		 208 compatible = "fsl,aips-bus", "simple-bus";
209 #address-cells = <1>;
210 #size-cells = <1>;
211 reg = <0x02000000 0x100000>;
212 ranges;
213
efb9adb2 214 spba-bus@2000000 {
a5fcccbc
FL		 215 compatible = "fsl,spba-bus", "simple-bus";
216 #address-cells = <1>;
217 #size-cells = <1>;
218 reg = <0x02000000 0x40000>;
219 ranges;
220
5a2ecf0d 221 ecspi1: spi@2008000 {
a5fcccbc
FL		 222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
225 reg = <0x02008000 0x4000>;
226 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clks IMX6UL_CLK_ECSPI1>,
228 <&clks IMX6UL_CLK_ECSPI1>;
229 clock-names = "ipg", "per";
230 status = "disabled";
231 };
232
5a2ecf0d 233 ecspi2: spi@200c000 {
a5fcccbc
FL		 234 #address-cells = <1>;
235 #size-cells = <0>;
236 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
237 reg = <0x0200c000 0x4000>;
238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&clks IMX6UL_CLK_ECSPI2>,
240 <&clks IMX6UL_CLK_ECSPI2>;
241 clock-names = "ipg", "per";
242 status = "disabled";
243 };
244
5a2ecf0d 245 ecspi3: spi@2010000 {
a5fcccbc
FL		 246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
249 reg = <0x02010000 0x4000>;
250 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&clks IMX6UL_CLK_ECSPI3>,
252 <&clks IMX6UL_CLK_ECSPI3>;
253 clock-names = "ipg", "per";
254 status = "disabled";
255 };
256
5a2ecf0d 257 ecspi4: spi@2014000 {
a5fcccbc
FL		 258 #address-cells = <1>;
259 #size-cells = <0>;
260 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
261 reg = <0x02014000 0x4000>;
262 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&clks IMX6UL_CLK_ECSPI4>,
264 <&clks IMX6UL_CLK_ECSPI4>;
265 clock-names = "ipg", "per";
266 status = "disabled";
267 };
268
efb9adb2 269 uart7: serial@2018000 {
a5fcccbc
FL		 270 compatible = "fsl,imx6ul-uart",
271 "fsl,imx6q-uart";
272 reg = <0x02018000 0x4000>;
273 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
275 <&clks IMX6UL_CLK_UART7_SERIAL>;
276 clock-names = "ipg", "per";
277 status = "disabled";
278 };
279
efb9adb2 280 uart1: serial@2020000 {
a5fcccbc
FL		 281 compatible = "fsl,imx6ul-uart",
282 "fsl,imx6q-uart";
283 reg = <0x02020000 0x4000>;
284 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
286 <&clks IMX6UL_CLK_UART1_SERIAL>;
287 clock-names = "ipg", "per";
288 status = "disabled";
289 };
290
efb9adb2 291 uart8: serial@2024000 {
a5fcccbc
FL		 292 compatible = "fsl,imx6ul-uart",
293 "fsl,imx6q-uart";
294 reg = <0x02024000 0x4000>;
295 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
297 <&clks IMX6UL_CLK_UART8_SERIAL>;
298 clock-names = "ipg", "per";
299 status = "disabled";
300 };
36e2edf6 301
efb9adb2 302 sai1: sai@2028000 {
36e2edf6
LW		 303 #sound-dai-cells = <0>;
304 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
305 reg = <0x02028000 0x4000>;
306 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
308 <&clks IMX6UL_CLK_SAI1>,
309 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
310 clock-names = "bus", "mclk1", "mclk2", "mclk3";
311 dmas = <&sdma 35 24 0>,
312 <&sdma 36 24 0>;
313 dma-names = "rx", "tx";
314 status = "disabled";
315 };
316
efb9adb2 317 sai2: sai@202c000 {
36e2edf6
LW		 318 #sound-dai-cells = <0>;
319 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
320 reg = <0x0202c000 0x4000>;
321 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
323 <&clks IMX6UL_CLK_SAI2>,
324 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
325 clock-names = "bus", "mclk1", "mclk2", "mclk3";
326 dmas = <&sdma 37 24 0>,
327 <&sdma 38 24 0>;
328 dma-names = "rx", "tx";
329 status = "disabled";
330 };
331
efb9adb2 332 sai3: sai@2030000 {
36e2edf6
LW		 333 #sound-dai-cells = <0>;
334 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
335 reg = <0x02030000 0x4000>;
336 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
338 <&clks IMX6UL_CLK_SAI3>,
339 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
340 clock-names = "bus", "mclk1", "mclk2", "mclk3";
341 dmas = <&sdma 39 24 0>,
342 <&sdma 40 24 0>;
343 dma-names = "rx", "tx";
344 status = "disabled";
345 };
a5fcccbc
FL		 346 };
347
efb9adb2 348 tsc: tsc@2040000 {
302e01b2
LW		 349 compatible = "fsl,imx6ul-tsc";
350 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
351 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&clks IMX6UL_CLK_IPG>,
354 <&clks IMX6UL_CLK_ADC2>;
355 clock-names = "tsc", "adc";
356 status = "disabled";
357 };
358
efb9adb2 359 pwm1: pwm@2080000 {
b9901fe8
LW		 360 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
361 reg = <0x02080000 0x4000>;
362 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clks IMX6UL_CLK_PWM1>,
364 <&clks IMX6UL_CLK_PWM1>;
365 clock-names = "ipg", "per";
366 #pwm-cells = <2>;
367 status = "disabled";
368 };
369
efb9adb2 370 pwm2: pwm@2084000 {
b9901fe8
LW		 371 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
372 reg = <0x02084000 0x4000>;
373 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&clks IMX6UL_CLK_PWM2>,
375 <&clks IMX6UL_CLK_PWM2>;
376 clock-names = "ipg", "per";
377 #pwm-cells = <2>;
378 status = "disabled";
379 };
380
efb9adb2 381 pwm3: pwm@2088000 {
b9901fe8
LW		 382 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
383 reg = <0x02088000 0x4000>;
384 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&clks IMX6UL_CLK_PWM3>,
386 <&clks IMX6UL_CLK_PWM3>;
387 clock-names = "ipg", "per";
388 #pwm-cells = <2>;
389 status = "disabled";
390 };
391
efb9adb2 392 pwm4: pwm@208c000 {
b9901fe8
LW		 393 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
394 reg = <0x0208c000 0x4000>;
395 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&clks IMX6UL_CLK_PWM4>,
397 <&clks IMX6UL_CLK_PWM4>;
398 clock-names = "ipg", "per";
399 #pwm-cells = <2>;
400 status = "disabled";
401 };
402
efb9adb2 403 can1: flexcan@2090000 {
c4aac1b1
LW		 404 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
405 reg = <0x02090000 0x4000>;
406 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
408 <&clks IMX6UL_CLK_CAN1_SERIAL>;
409 clock-names = "ipg", "per";
f049557e 410 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
c4aac1b1
LW		 411 status = "disabled";
412 };
413
efb9adb2 414 can2: flexcan@2094000 {
c4aac1b1
LW		 415 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
416 reg = <0x02094000 0x4000>;
417 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
419 <&clks IMX6UL_CLK_CAN2_SERIAL>;
420 clock-names = "ipg", "per";
f049557e 421 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
c4aac1b1
LW		 422 status = "disabled";
423 };
424
efb9adb2 425 gpt1: gpt@2098000 {
a5fcccbc
FL		 426 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
427 reg = <0x02098000 0x4000>;
428 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
430 <&clks IMX6UL_CLK_GPT1_SERIAL>;
431 clock-names = "ipg", "per";
432 };
433
efb9adb2 434 gpio1: gpio@209c000 {
a5fcccbc
FL		 435 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
436 reg = <0x0209c000 0x4000>;
437 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
bc36b2aa 439 clocks = <&clks IMX6UL_CLK_GPIO1>;
a5fcccbc
FL		 440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
bb728d66
VZ		 444 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
445 <&iomuxc 16 33 16>;
a5fcccbc
FL		 446 };
447
efb9adb2 448 gpio2: gpio@20a0000 {
a5fcccbc
FL		 449 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
450 reg = <0x020a0000 0x4000>;
451 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
bc36b2aa 453 clocks = <&clks IMX6UL_CLK_GPIO2>;
a5fcccbc
FL		 454 gpio-controller;
455 #gpio-cells = <2>;
456 interrupt-controller;
457 #interrupt-cells = <2>;
bb728d66 458 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
a5fcccbc
FL		 459 };
460
efb9adb2 461 gpio3: gpio@20a4000 {
a5fcccbc
FL		 462 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
463 reg = <0x020a4000 0x4000>;
464 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
bc36b2aa 466 clocks = <&clks IMX6UL_CLK_GPIO3>;
a5fcccbc
FL		 467 gpio-controller;
468 #gpio-cells = <2>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
bb728d66 471 gpio-ranges = <&iomuxc 0 65 29>;
a5fcccbc
FL		 472 };
473
efb9adb2 474 gpio4: gpio@20a8000 {
a5fcccbc
FL		 475 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
476 reg = <0x020a8000 0x4000>;
477 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
bc36b2aa 479 clocks = <&clks IMX6UL_CLK_GPIO4>;
a5fcccbc
FL		 480 gpio-controller;
481 #gpio-cells = <2>;
482 interrupt-controller;
483 #interrupt-cells = <2>;
bb728d66 484 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
a5fcccbc
FL		 485 };
486
efb9adb2 487 gpio5: gpio@20ac000 {
a5fcccbc
FL		 488 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
489 reg = <0x020ac000 0x4000>;
490 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
bc36b2aa 492 clocks = <&clks IMX6UL_CLK_GPIO5>;
a5fcccbc
FL		 493 gpio-controller;
494 #gpio-cells = <2>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
bb728d66 497 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
a5fcccbc
FL		 498 };
499
efb9adb2 500 fec2: ethernet@20b4000 {
01f3dc7d
FD		 501 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
502 reg = <0x020b4000 0x4000>;
e94a2309 503 interrupt-names = "int0", "pps";
01f3dc7d
FD		 504 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clks IMX6UL_CLK_ENET>,
507 <&clks IMX6UL_CLK_ENET_AHB>,
508 <&clks IMX6UL_CLK_ENET_PTP>,
509 <&clks IMX6UL_CLK_ENET2_REF_125M>,
510 <&clks IMX6UL_CLK_ENET2_REF_125M>;
511 clock-names = "ipg", "ahb", "ptp",
512 "enet_clk_ref", "enet_out";
513 fsl,num-tx-queues=<1>;
514 fsl,num-rx-queues=<1>;
515 status = "disabled";
516 };
517
efb9adb2 518 kpp: kpp@20b8000 {
ea1c1752
LW		 519 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
520 reg = <0x020b8000 0x4000>;
521 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&clks IMX6UL_CLK_KPP>;
523 status = "disabled";
524 };
525
efb9adb2 526 wdog1: wdog@20bc000 {
a5fcccbc
FL		 527 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
528 reg = <0x020bc000 0x4000>;
529 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&clks IMX6UL_CLK_WDOG1>;
531 };
532
efb9adb2 533 wdog2: wdog@20c0000 {
a5fcccbc
FL		 534 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
535 reg = <0x020c0000 0x4000>;
536 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&clks IMX6UL_CLK_WDOG2>;
538 status = "disabled";
539 };
540
efb9adb2 541 clks: ccm@20c4000 {
a5fcccbc
FL		 542 compatible = "fsl,imx6ul-ccm";
543 reg = <0x020c4000 0x4000>;
544 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
546 #clock-cells = <1>;
547 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
548 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
549 };
550
efb9adb2 551 anatop: anatop@20c8000 {
a5fcccbc
FL		 552 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
553 "syscon", "simple-bus";
554 reg = <0x020c8000 0x1000>;
555 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
558
71db3948 559 reg_3p0: regulator-3p0 {
a5fcccbc
FL		 560 compatible = "fsl,anatop-regulator";
561 regulator-name = "vdd3p0";
562 regulator-min-microvolt = <2625000>;
563 regulator-max-microvolt = <3400000>;
564 anatop-reg-offset = <0x120>;
565 anatop-vol-bit-shift = <8>;
566 anatop-vol-bit-width = <5>;
567 anatop-min-bit-val = <0>;
568 anatop-min-voltage = <2625000>;
569 anatop-max-voltage = <3400000>;
38281a47 570 anatop-enable-bit = <0>;
a5fcccbc
FL		 571 };
572
71db3948 573 reg_arm: regulator-vddcore {
a5fcccbc
FL		 574 compatible = "fsl,anatop-regulator";
575 regulator-name = "cpu";
576 regulator-min-microvolt = <725000>;
577 regulator-max-microvolt = <1450000>;
578 regulator-always-on;
579 anatop-reg-offset = <0x140>;
580 anatop-vol-bit-shift = <0>;
581 anatop-vol-bit-width = <5>;
582 anatop-delay-reg-offset = <0x170>;
583 anatop-delay-bit-shift = <24>;
584 anatop-delay-bit-width = <2>;
585 anatop-min-bit-val = <1>;
586 anatop-min-voltage = <725000>;
587 anatop-max-voltage = <1450000>;
588 };
589
71db3948 590 reg_soc: regulator-vddsoc {
a5fcccbc
FL		 591 compatible = "fsl,anatop-regulator";
592 regulator-name = "vddsoc";
593 regulator-min-microvolt = <725000>;
594 regulator-max-microvolt = <1450000>;
595 regulator-always-on;
596 anatop-reg-offset = <0x140>;
597 anatop-vol-bit-shift = <18>;
598 anatop-vol-bit-width = <5>;
599 anatop-delay-reg-offset = <0x170>;
600 anatop-delay-bit-shift = <28>;
601 anatop-delay-bit-width = <2>;
602 anatop-min-bit-val = <1>;
603 anatop-min-voltage = <725000>;
604 anatop-max-voltage = <1450000>;
605 };
606 };
607
efb9adb2 608 usbphy1: usbphy@20c9000 {
a5fcccbc
FL		 609 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
610 reg = <0x020c9000 0x1000>;
611 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clks IMX6UL_CLK_USBPHY1>;
613 phy-3p0-supply = <&reg_3p0>;
614 fsl,anatop = <&anatop>;
615 };
616
efb9adb2 617 usbphy2: usbphy@20ca000 {
a5fcccbc
FL		 618 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
619 reg = <0x020ca000 0x1000>;
620 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&clks IMX6UL_CLK_USBPHY2>;
622 phy-3p0-supply = <&reg_3p0>;
623 fsl,anatop = <&anatop>;
624 };
625
efb9adb2 626 snvs: snvs@20cc000 {
5b032872
AH		 627 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
628 reg = <0x020cc000 0x4000>;
629
630 snvs_rtc: snvs-rtc-lp {
631 compatible = "fsl,sec-v4.0-mon-rtc-lp";
632 regmap = <&snvs>;
633 offset = <0x34>;
634 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
636 };
36032575 637
ab0a05d8
AH		 638 snvs_poweroff: snvs-poweroff {
639 compatible = "syscon-poweroff";
640 regmap = <&snvs>;
641 offset = <0x38>;
87a84c62 642 value = <0x60>;
ab0a05d8
AH		 643 mask = <0x60>;
644 status = "disabled";
645 };
646
36032575
AH		 647 snvs_pwrkey: snvs-powerkey {
648 compatible = "fsl,sec-v4.0-pwrkey";
649 regmap = <&snvs>;
650 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
651 linux,keycode = <KEY_POWER>;
652 wakeup-source;
052ce6f4 653 status = "disabled";
36032575 654 };
a53745d1
OR		 655
656 snvs_lpgpr: snvs-lpgpr {
657 compatible = "fsl,imx6ul-snvs-lpgpr";
658 };
5b032872
AH		 659 };
660
efb9adb2 661 epit1: epit@20d0000 {
a5fcccbc
FL		 662 reg = <0x020d0000 0x4000>;
663 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
664 };
665
efb9adb2 666 epit2: epit@20d4000 {
a5fcccbc
FL		 667 reg = <0x020d4000 0x4000>;
668 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
669 };
670
efb9adb2 671 src: src@20d8000 {
a5fcccbc
FL		 672 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
673 reg = <0x020d8000 0x4000>;
674 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
676 #reset-cells = <1>;
677 };
678
efb9adb2 679 gpc: gpc@20dc000 {
a5fcccbc
FL		 680 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
681 reg = <0x020dc000 0x4000>;
18619ff5
AH		 682 interrupt-controller;
683 #interrupt-cells = <3>;
a5fcccbc 684 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
18619ff5 685 interrupt-parent = <&intc>;
a5fcccbc
FL		 686 };
687
efb9adb2 688 iomuxc: iomuxc@20e0000 {
a5fcccbc
FL		 689 compatible = "fsl,imx6ul-iomuxc";
690 reg = <0x020e0000 0x4000>;
691 };
692
efb9adb2 693 gpr: iomuxc-gpr@20e4000 {
0f39c504
AH		 694 compatible = "fsl,imx6ul-iomuxc-gpr",
695 "fsl,imx6q-iomuxc-gpr", "syscon";
a5fcccbc
FL		 696 reg = <0x020e4000 0x4000>;
697 };
698
efb9adb2 699 gpt2: gpt@20e8000 {
a5fcccbc
FL		 700 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
701 reg = <0x020e8000 0x4000>;
702 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
d97ca99f
LW		 703 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
704 <&clks IMX6UL_CLK_GPT2_SERIAL>;
a5fcccbc
FL		 705 clock-names = "ipg", "per";
706 };
707
efb9adb2 708 sdma: sdma@20ec000 {
76758c6a
LW		 709 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
710 "fsl,imx35-sdma";
711 reg = <0x020ec000 0x4000>;
712 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
7b3132ec 713 clocks = <&clks IMX6UL_CLK_IPG>,
76758c6a
LW		 714 <&clks IMX6UL_CLK_SDMA>;
715 clock-names = "ipg", "ahb";
716 #dma-cells = <3>;
717 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
718 };
719
efb9adb2 720 pwm5: pwm@20f0000 {
a5fcccbc
FL		 721 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
722 reg = <0x020f0000 0x4000>;
723 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 724 clocks = <&clks IMX6UL_CLK_PWM5>,
725 <&clks IMX6UL_CLK_PWM5>;
a5fcccbc
FL		 726 clock-names = "ipg", "per";
727 #pwm-cells = <2>;
dd135095 728 status = "disabled";
a5fcccbc
FL		 729 };
730
efb9adb2 731 pwm6: pwm@20f4000 {
a5fcccbc
FL		 732 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
733 reg = <0x020f4000 0x4000>;
734 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 735 clocks = <&clks IMX6UL_CLK_PWM6>,
736 <&clks IMX6UL_CLK_PWM6>;
a5fcccbc
FL		 737 clock-names = "ipg", "per";
738 #pwm-cells = <2>;
dd135095 739 status = "disabled";
a5fcccbc
FL		 740 };
741
efb9adb2 742 pwm7: pwm@20f8000 {
a5fcccbc
FL		 743 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
744 reg = <0x020f8000 0x4000>;
745 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 746 clocks = <&clks IMX6UL_CLK_PWM7>,
747 <&clks IMX6UL_CLK_PWM7>;
a5fcccbc
FL		 748 clock-names = "ipg", "per";
749 #pwm-cells = <2>;
dd135095 750 status = "disabled";
a5fcccbc
FL		 751 };
752
efb9adb2 753 pwm8: pwm@20fc000 {
a5fcccbc
FL		 754 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
755 reg = <0x020fc000 0x4000>;
756 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 757 clocks = <&clks IMX6UL_CLK_PWM8>,
758 <&clks IMX6UL_CLK_PWM8>;
a5fcccbc
FL		 759 clock-names = "ipg", "per";
760 #pwm-cells = <2>;
dd135095 761 status = "disabled";
a5fcccbc
FL		 762 };
763 };
764
efb9adb2 765 aips2: aips-bus@2100000 {
a5fcccbc
FL		 766 compatible = "fsl,aips-bus", "simple-bus";
767 #address-cells = <1>;
768 #size-cells = <1>;
769 reg = <0x02100000 0x100000>;
770 ranges;
771
8c371730
FE		 772 crypto: caam@2140000 {
773 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
774 #address-cells = <1>;
775 #size-cells = <1>;
776 reg = <0x2140000 0x3c000>;
777 ranges = <0 0x2140000 0x3c000>;
778 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
780 <&clks IMX6UL_CLK_CAAM_MEM>;
781 clock-names = "ipg", "aclk", "mem";
782
783 sec_jr0: jr0@1000 {
784 compatible = "fsl,sec-v4.0-job-ring";
785 reg = <0x1000 0x1000>;
786 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
787 };
788
789 sec_jr1: jr1@2000 {
790 compatible = "fsl,sec-v4.0-job-ring";
791 reg = <0x2000 0x1000>;
792 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
793 };
794
795 sec_jr2: jr2@3000 {
796 compatible = "fsl,sec-v4.0-job-ring";
797 reg = <0x3000 0x1000>;
798 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
799 };
800 };
801
efb9adb2 802 usbotg1: usb@2184000 {
cad2cb69
FL		 803 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
804 reg = <0x02184000 0x200>;
805 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clks IMX6UL_CLK_USBOH3>;
807 fsl,usbphy = <&usbphy1>;
808 fsl,usbmisc = <&usbmisc 0>;
809 fsl,anatop = <&anatop>;
9493bf54 810 ahb-burst-config = <0x0>;
2b1a40e8
PC		 811 tx-burst-size-dword = <0x10>;
812 rx-burst-size-dword = <0x10>;
cad2cb69
FL		 813 status = "disabled";
814 };
815
efb9adb2 816 usbotg2: usb@2184200 {
cad2cb69
FL		 817 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
818 reg = <0x02184200 0x200>;
819 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&clks IMX6UL_CLK_USBOH3>;
821 fsl,usbphy = <&usbphy2>;
822 fsl,usbmisc = <&usbmisc 1>;
9493bf54 823 ahb-burst-config = <0x0>;
2b1a40e8
PC		 824 tx-burst-size-dword = <0x10>;
825 rx-burst-size-dword = <0x10>;
cad2cb69
FL		 826 status = "disabled";
827 };
828
efb9adb2 829 usbmisc: usbmisc@2184800 {
cad2cb69
FL		 830 #index-cells = <1>;
831 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
832 reg = <0x02184800 0x200>;
833 };
834
efb9adb2 835 fec1: ethernet@2188000 {
01f3dc7d
FD		 836 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
837 reg = <0x02188000 0x4000>;
e94a2309 838 interrupt-names = "int0", "pps";
01f3dc7d
FD		 839 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&clks IMX6UL_CLK_ENET>,
842 <&clks IMX6UL_CLK_ENET_AHB>,
843 <&clks IMX6UL_CLK_ENET_PTP>,
844 <&clks IMX6UL_CLK_ENET_REF>,
845 <&clks IMX6UL_CLK_ENET_REF>;
846 clock-names = "ipg", "ahb", "ptp",
847 "enet_clk_ref", "enet_out";
848 fsl,num-tx-queues=<1>;
849 fsl,num-rx-queues=<1>;
850 status = "disabled";
851 };
852
efb9adb2 853 usdhc1: usdhc@2190000 {
a5fcccbc
FL		 854 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
855 reg = <0x02190000 0x4000>;
856 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&clks IMX6UL_CLK_USDHC1>,
858 <&clks IMX6UL_CLK_USDHC1>,
859 <&clks IMX6UL_CLK_USDHC1>;
860 clock-names = "ipg", "ahb", "per";
20353143
IO		 861 fsl,tuning-step= <2>;
862 fsl,tuning-start-tap = <20>;
a5fcccbc
FL		 863 bus-width = <4>;
864 status = "disabled";
865 };
866
efb9adb2 867 usdhc2: usdhc@2194000 {
a5fcccbc
FL		 868 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
869 reg = <0x02194000 0x4000>;
870 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clks IMX6UL_CLK_USDHC2>,
872 <&clks IMX6UL_CLK_USDHC2>,
873 <&clks IMX6UL_CLK_USDHC2>;
874 clock-names = "ipg", "ahb", "per";
875 bus-width = <4>;
20353143
IO		 876 fsl,tuning-step= <2>;
877 fsl,tuning-start-tap = <20>;
a5fcccbc
FL		 878 status = "disabled";
879 };
880
efb9adb2 881 adc1: adc@2198000 {
aab8ec0c
FE		 882 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
883 reg = <0x02198000 0x4000>;
884 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clks IMX6UL_CLK_ADC1>;
886 num-channels = <2>;
887 clock-names = "adc";
888 fsl,adck-max-frequency = <30000000>, <40000000>,
889 <20000000>;
890 status = "disabled";
891 };
892
efb9adb2 893 i2c1: i2c@21a0000 {
a5fcccbc
FL		 894 #address-cells = <1>;
895 #size-cells = <0>;
896 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
897 reg = <0x021a0000 0x4000>;
898 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clks IMX6UL_CLK_I2C1>;
900 status = "disabled";
901 };
902
efb9adb2 903 i2c2: i2c@21a4000 {
a5fcccbc
FL		 904 #address-cells = <1>;
905 #size-cells = <0>;
906 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
907 reg = <0x021a4000 0x4000>;
908 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&clks IMX6UL_CLK_I2C2>;
910 status = "disabled";
911 };
912
efb9adb2 913 i2c3: i2c@21a8000 {
a5fcccbc
FL		 914 #address-cells = <1>;
915 #size-cells = <0>;
916 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
917 reg = <0x021a8000 0x4000>;
918 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
919 clocks = <&clks IMX6UL_CLK_I2C3>;
920 status = "disabled";
921 };
922
476f6e53 923 memory-controller@21b0000 {
51a37443
AH		 924 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
925 reg = <0x021b0000 0x4000>;
39db0e13 926 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
51a37443
AH		 927 };
928
3494cfb5
SS		 929 weim: weim@21b8000 {
930 #address-cells = <2>;
931 #size-cells = <1>;
932 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
933 reg = <0x021b8000 0x4000>;
934 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&clks IMX6UL_CLK_EIM>;
936 fsl,weim-cs-gpr = <&gpr>;
937 status = "disabled";
938 };
939
efb9adb2 940 ocotp: ocotp-ctrl@21bc000 {
2067b757
LC		 941 #address-cells = <1>;
942 #size-cells = <1>;
8686439d
BP		 943 compatible = "fsl,imx6ul-ocotp", "syscon";
944 reg = <0x021bc000 0x4000>;
945 clocks = <&clks IMX6UL_CLK_OCOTP>;
2067b757
LC		 946
947 tempmon_calib: calib@38 {
948 reg = <0x38 4>;
949 };
950
951 tempmon_temp_grade: temp-grade@20 {
952 reg = <0x20 4>;
953 };
92f0eb08
AH		 954
955 cpu_speed_grade: speed-grade@10 {
956 reg = <0x10 4>;
957 };
8686439d
BP		 958 };
959
efb9adb2 960 lcdif: lcdif@21c8000 {
6fe01eb7
LW		 961 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
962 reg = <0x021c8000 0x4000>;
963 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
964 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
965 <&clks IMX6UL_CLK_LCDIF_APB>,
966 <&clks IMX6UL_CLK_DUMMY>;
967 clock-names = "pix", "axi", "disp_axi";
968 status = "disabled";
969 };
970
5a2ecf0d 971 qspi: spi@21e0000 {
5ff807a5
FL		 972 #address-cells = <1>;
973 #size-cells = <0>;
974 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
975 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
976 reg-names = "QuadSPI", "QuadSPI-memory";
977 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&clks IMX6UL_CLK_QSPI>,
979 <&clks IMX6UL_CLK_QSPI>;
980 clock-names = "qspi_en", "qspi";
981 status = "disabled";
982 };
983
fa2f2576
JK		 984 wdog3: wdog@21e4000 {
985 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
986 reg = <0x021e4000 0x4000>;
987 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&clks IMX6UL_CLK_WDOG3>;
989 status = "disabled";
990 };
991
efb9adb2 992 uart2: serial@21e8000 {
a5fcccbc
FL		 993 compatible = "fsl,imx6ul-uart",
994 "fsl,imx6q-uart";
995 reg = <0x021e8000 0x4000>;
996 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
998 <&clks IMX6UL_CLK_UART2_SERIAL>;
999 clock-names = "ipg", "per";
1000 status = "disabled";
1001 };
1002
efb9adb2 1003 uart3: serial@21ec000 {
a5fcccbc
FL		 1004 compatible = "fsl,imx6ul-uart",
1005 "fsl,imx6q-uart";
1006 reg = <0x021ec000 0x4000>;
1007 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1009 <&clks IMX6UL_CLK_UART3_SERIAL>;
1010 clock-names = "ipg", "per";
1011 status = "disabled";
1012 };
1013
efb9adb2 1014 uart4: serial@21f0000 {
a5fcccbc
FL		 1015 compatible = "fsl,imx6ul-uart",
1016 "fsl,imx6q-uart";
1017 reg = <0x021f0000 0x4000>;
1018 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1020 <&clks IMX6UL_CLK_UART4_SERIAL>;
1021 clock-names = "ipg", "per";
1022 status = "disabled";
1023 };
1024
efb9adb2 1025 uart5: serial@21f4000 {
a5fcccbc
FL		 1026 compatible = "fsl,imx6ul-uart",
1027 "fsl,imx6q-uart";
1028 reg = <0x021f4000 0x4000>;
1029 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1031 <&clks IMX6UL_CLK_UART5_SERIAL>;
1032 clock-names = "ipg", "per";
1033 status = "disabled";
1034 };
1035
efb9adb2 1036 i2c4: i2c@21f8000 {
a5fcccbc
FL		 1037 #address-cells = <1>;
1038 #size-cells = <0>;
1039 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1040 reg = <0x021f8000 0x4000>;
1041 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&clks IMX6UL_CLK_I2C4>;
1043 status = "disabled";
1044 };
1045
efb9adb2 1046 uart6: serial@21fc000 {
a5fcccbc
FL		 1047 compatible = "fsl,imx6ul-uart",
1048 "fsl,imx6q-uart";
1049 reg = <0x021fc000 0x4000>;
1050 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1051 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1052 <&clks IMX6UL_CLK_UART6_SERIAL>;
1053 clock-names = "ipg", "per";
1054 status = "disabled";
1055 };
1056 };
1057 };
1058};
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