]>
Commit | Line | Data |
---|---|---|
a5fcccbc FL |
1 | /* |
2 | * Copyright 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <dt-bindings/clock/imx6ul-clock.h> | |
10 | #include <dt-bindings/gpio/gpio.h> | |
89435fea | 11 | #include <dt-bindings/input/input.h> |
a5fcccbc FL |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
13 | #include "imx6ul-pinfunc.h" | |
a5fcccbc FL |
14 | |
15 | / { | |
7f107887 FE |
16 | #address-cells = <1>; |
17 | #size-cells = <1>; | |
a971c554 FE |
18 | /* |
19 | * The decompressor and also some bootloaders rely on a | |
20 | * pre-existing /chosen node to be available to insert the | |
21 | * command line and merge other ATAGS info. | |
22 | * Also for U-Boot there must be a pre-existing /memory node. | |
23 | */ | |
24 | chosen {}; | |
25 | memory { device_type = "memory"; reg = <0 0>; }; | |
7f107887 | 26 | |
a5fcccbc | 27 | aliases { |
01f3dc7d FD |
28 | ethernet0 = &fec1; |
29 | ethernet1 = &fec2; | |
a5fcccbc FL |
30 | gpio0 = &gpio1; |
31 | gpio1 = &gpio2; | |
32 | gpio2 = &gpio3; | |
33 | gpio3 = &gpio4; | |
34 | gpio4 = &gpio5; | |
35 | i2c0 = &i2c1; | |
36 | i2c1 = &i2c2; | |
37 | i2c2 = &i2c3; | |
38 | i2c3 = &i2c4; | |
39 | mmc0 = &usdhc1; | |
40 | mmc1 = &usdhc2; | |
41 | serial0 = &uart1; | |
42 | serial1 = &uart2; | |
43 | serial2 = &uart3; | |
44 | serial3 = &uart4; | |
45 | serial4 = &uart5; | |
46 | serial5 = &uart6; | |
47 | serial6 = &uart7; | |
48 | serial7 = &uart8; | |
fb3239ff FE |
49 | sai1 = &sai1; |
50 | sai2 = &sai2; | |
51 | sai3 = &sai3; | |
a5fcccbc FL |
52 | spi0 = &ecspi1; |
53 | spi1 = &ecspi2; | |
54 | spi2 = &ecspi3; | |
55 | spi3 = &ecspi4; | |
56 | usbphy0 = &usbphy1; | |
57 | usbphy1 = &usbphy2; | |
58 | }; | |
59 | ||
60 | cpus { | |
61 | #address-cells = <1>; | |
62 | #size-cells = <0>; | |
63 | ||
64 | cpu0: cpu@0 { | |
65 | compatible = "arm,cortex-a7"; | |
66 | device_type = "cpu"; | |
67 | reg = <0>; | |
68 | clock-latency = <61036>; /* two CLK32 periods */ | |
69 | operating-points = < | |
70 | /* kHz uV */ | |
f7084446 FE |
71 | 528000 1175000 |
72 | 396000 1025000 | |
73 | 198000 950000 | |
a5fcccbc FL |
74 | >; |
75 | fsl,soc-operating-points = < | |
76 | /* KHz uV */ | |
f7084446 FE |
77 | 528000 1175000 |
78 | 396000 1175000 | |
79 | 198000 1175000 | |
a5fcccbc FL |
80 | >; |
81 | clocks = <&clks IMX6UL_CLK_ARM>, | |
82 | <&clks IMX6UL_CLK_PLL2_BUS>, | |
83 | <&clks IMX6UL_CLK_PLL2_PFD2>, | |
84 | <&clks IMX6UL_CA7_SECONDARY_SEL>, | |
85 | <&clks IMX6UL_CLK_STEP>, | |
86 | <&clks IMX6UL_CLK_PLL1_SW>, | |
87 | <&clks IMX6UL_CLK_PLL1_SYS>, | |
88 | <&clks IMX6UL_PLL1_BYPASS>, | |
89 | <&clks IMX6UL_CLK_PLL1>, | |
90 | <&clks IMX6UL_PLL1_BYPASS_SRC>, | |
91 | <&clks IMX6UL_CLK_OSC>; | |
92 | clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", | |
93 | "secondary_sel", "step", "pll1_sw", | |
94 | "pll1_sys", "pll1_bypass", "pll1", | |
95 | "pll1_bypass_src", "osc"; | |
96 | arm-supply = <®_arm>; | |
97 | soc-supply = <®_soc>; | |
98 | }; | |
99 | }; | |
100 | ||
101 | intc: interrupt-controller@00a01000 { | |
102 | compatible = "arm,cortex-a7-gic"; | |
103 | #interrupt-cells = <3>; | |
104 | interrupt-controller; | |
105 | reg = <0x00a01000 0x1000>, | |
106 | <0x00a02000 0x1000>, | |
107 | <0x00a04000 0x2000>, | |
108 | <0x00a06000 0x2000>; | |
109 | }; | |
110 | ||
111 | ckil: clock-cli { | |
112 | compatible = "fixed-clock"; | |
113 | #clock-cells = <0>; | |
114 | clock-frequency = <32768>; | |
115 | clock-output-names = "ckil"; | |
116 | }; | |
117 | ||
118 | osc: clock-osc { | |
119 | compatible = "fixed-clock"; | |
120 | #clock-cells = <0>; | |
121 | clock-frequency = <24000000>; | |
122 | clock-output-names = "osc"; | |
123 | }; | |
124 | ||
125 | ipp_di0: clock-di0 { | |
126 | compatible = "fixed-clock"; | |
127 | #clock-cells = <0>; | |
128 | clock-frequency = <0>; | |
129 | clock-output-names = "ipp_di0"; | |
130 | }; | |
131 | ||
132 | ipp_di1: clock-di1 { | |
133 | compatible = "fixed-clock"; | |
134 | #clock-cells = <0>; | |
135 | clock-frequency = <0>; | |
136 | clock-output-names = "ipp_di1"; | |
137 | }; | |
138 | ||
139 | soc { | |
140 | #address-cells = <1>; | |
141 | #size-cells = <1>; | |
142 | compatible = "simple-bus"; | |
18619ff5 | 143 | interrupt-parent = <&gpc>; |
a5fcccbc FL |
144 | ranges; |
145 | ||
146 | pmu { | |
147 | compatible = "arm,cortex-a7-pmu"; | |
148 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
149 | status = "disabled"; | |
150 | }; | |
151 | ||
322d09d6 AH |
152 | ocram: sram@00900000 { |
153 | compatible = "mmio-sram"; | |
154 | reg = <0x00900000 0x20000>; | |
155 | }; | |
156 | ||
7d1cd297 LW |
157 | dma_apbh: dma-apbh@01804000 { |
158 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; | |
159 | reg = <0x01804000 0x2000>; | |
160 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
161 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
162 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
163 | <0 13 IRQ_TYPE_LEVEL_HIGH>; | |
164 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; | |
165 | #dma-cells = <1>; | |
166 | dma-channels = <4>; | |
167 | clocks = <&clks IMX6UL_CLK_APBHDMA>; | |
168 | }; | |
169 | ||
170 | gpmi: gpmi-nand@01806000 { | |
171 | compatible = "fsl,imx6q-gpmi-nand"; | |
172 | #address-cells = <1>; | |
173 | #size-cells = <1>; | |
174 | reg = <0x01806000 0x2000>, <0x01808000 0x2000>; | |
175 | reg-names = "gpmi-nand", "bch"; | |
176 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; | |
177 | interrupt-names = "bch"; | |
178 | clocks = <&clks IMX6UL_CLK_GPMI_IO>, | |
179 | <&clks IMX6UL_CLK_GPMI_APB>, | |
180 | <&clks IMX6UL_CLK_GPMI_BCH>, | |
181 | <&clks IMX6UL_CLK_GPMI_BCH_APB>, | |
182 | <&clks IMX6UL_CLK_PER_BCH>; | |
183 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", | |
184 | "gpmi_bch_apb", "per1_bch"; | |
185 | dmas = <&dma_apbh 0>; | |
186 | dma-names = "rx-tx"; | |
187 | status = "disabled"; | |
188 | }; | |
189 | ||
a5fcccbc FL |
190 | aips1: aips-bus@02000000 { |
191 | compatible = "fsl,aips-bus", "simple-bus"; | |
192 | #address-cells = <1>; | |
193 | #size-cells = <1>; | |
194 | reg = <0x02000000 0x100000>; | |
195 | ranges; | |
196 | ||
197 | spba-bus@02000000 { | |
198 | compatible = "fsl,spba-bus", "simple-bus"; | |
199 | #address-cells = <1>; | |
200 | #size-cells = <1>; | |
201 | reg = <0x02000000 0x40000>; | |
202 | ranges; | |
203 | ||
204 | ecspi1: ecspi@02008000 { | |
205 | #address-cells = <1>; | |
206 | #size-cells = <0>; | |
207 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
208 | reg = <0x02008000 0x4000>; | |
209 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
210 | clocks = <&clks IMX6UL_CLK_ECSPI1>, | |
211 | <&clks IMX6UL_CLK_ECSPI1>; | |
212 | clock-names = "ipg", "per"; | |
213 | status = "disabled"; | |
214 | }; | |
215 | ||
216 | ecspi2: ecspi@0200c000 { | |
217 | #address-cells = <1>; | |
218 | #size-cells = <0>; | |
219 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
220 | reg = <0x0200c000 0x4000>; | |
221 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
222 | clocks = <&clks IMX6UL_CLK_ECSPI2>, | |
223 | <&clks IMX6UL_CLK_ECSPI2>; | |
224 | clock-names = "ipg", "per"; | |
225 | status = "disabled"; | |
226 | }; | |
227 | ||
228 | ecspi3: ecspi@02010000 { | |
229 | #address-cells = <1>; | |
230 | #size-cells = <0>; | |
231 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
232 | reg = <0x02010000 0x4000>; | |
233 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
234 | clocks = <&clks IMX6UL_CLK_ECSPI3>, | |
235 | <&clks IMX6UL_CLK_ECSPI3>; | |
236 | clock-names = "ipg", "per"; | |
237 | status = "disabled"; | |
238 | }; | |
239 | ||
240 | ecspi4: ecspi@02014000 { | |
241 | #address-cells = <1>; | |
242 | #size-cells = <0>; | |
243 | compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
244 | reg = <0x02014000 0x4000>; | |
245 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
246 | clocks = <&clks IMX6UL_CLK_ECSPI4>, | |
247 | <&clks IMX6UL_CLK_ECSPI4>; | |
248 | clock-names = "ipg", "per"; | |
249 | status = "disabled"; | |
250 | }; | |
251 | ||
252 | uart7: serial@02018000 { | |
253 | compatible = "fsl,imx6ul-uart", | |
254 | "fsl,imx6q-uart"; | |
255 | reg = <0x02018000 0x4000>; | |
256 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
257 | clocks = <&clks IMX6UL_CLK_UART7_IPG>, | |
258 | <&clks IMX6UL_CLK_UART7_SERIAL>; | |
259 | clock-names = "ipg", "per"; | |
260 | status = "disabled"; | |
261 | }; | |
262 | ||
263 | uart1: serial@02020000 { | |
264 | compatible = "fsl,imx6ul-uart", | |
265 | "fsl,imx6q-uart"; | |
266 | reg = <0x02020000 0x4000>; | |
267 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
268 | clocks = <&clks IMX6UL_CLK_UART1_IPG>, | |
269 | <&clks IMX6UL_CLK_UART1_SERIAL>; | |
270 | clock-names = "ipg", "per"; | |
271 | status = "disabled"; | |
272 | }; | |
273 | ||
274 | uart8: serial@02024000 { | |
275 | compatible = "fsl,imx6ul-uart", | |
276 | "fsl,imx6q-uart"; | |
277 | reg = <0x02024000 0x4000>; | |
278 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
279 | clocks = <&clks IMX6UL_CLK_UART8_IPG>, | |
280 | <&clks IMX6UL_CLK_UART8_SERIAL>; | |
281 | clock-names = "ipg", "per"; | |
282 | status = "disabled"; | |
283 | }; | |
36e2edf6 LW |
284 | |
285 | sai1: sai@02028000 { | |
286 | #sound-dai-cells = <0>; | |
287 | compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; | |
288 | reg = <0x02028000 0x4000>; | |
289 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
290 | clocks = <&clks IMX6UL_CLK_SAI1_IPG>, | |
291 | <&clks IMX6UL_CLK_SAI1>, | |
292 | <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; | |
293 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
294 | dmas = <&sdma 35 24 0>, | |
295 | <&sdma 36 24 0>; | |
296 | dma-names = "rx", "tx"; | |
297 | status = "disabled"; | |
298 | }; | |
299 | ||
300 | sai2: sai@0202c000 { | |
301 | #sound-dai-cells = <0>; | |
302 | compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; | |
303 | reg = <0x0202c000 0x4000>; | |
304 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
305 | clocks = <&clks IMX6UL_CLK_SAI2_IPG>, | |
306 | <&clks IMX6UL_CLK_SAI2>, | |
307 | <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; | |
308 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
309 | dmas = <&sdma 37 24 0>, | |
310 | <&sdma 38 24 0>; | |
311 | dma-names = "rx", "tx"; | |
312 | status = "disabled"; | |
313 | }; | |
314 | ||
315 | sai3: sai@02030000 { | |
316 | #sound-dai-cells = <0>; | |
317 | compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; | |
318 | reg = <0x02030000 0x4000>; | |
319 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
320 | clocks = <&clks IMX6UL_CLK_SAI3_IPG>, | |
321 | <&clks IMX6UL_CLK_SAI3>, | |
322 | <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; | |
323 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
324 | dmas = <&sdma 39 24 0>, | |
325 | <&sdma 40 24 0>; | |
326 | dma-names = "rx", "tx"; | |
327 | status = "disabled"; | |
328 | }; | |
a5fcccbc FL |
329 | }; |
330 | ||
302e01b2 LW |
331 | tsc: tsc@02040000 { |
332 | compatible = "fsl,imx6ul-tsc"; | |
333 | reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; | |
334 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
335 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
336 | clocks = <&clks IMX6UL_CLK_IPG>, | |
337 | <&clks IMX6UL_CLK_ADC2>; | |
338 | clock-names = "tsc", "adc"; | |
339 | status = "disabled"; | |
340 | }; | |
341 | ||
b9901fe8 LW |
342 | pwm1: pwm@02080000 { |
343 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
344 | reg = <0x02080000 0x4000>; | |
345 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
346 | clocks = <&clks IMX6UL_CLK_PWM1>, | |
347 | <&clks IMX6UL_CLK_PWM1>; | |
348 | clock-names = "ipg", "per"; | |
349 | #pwm-cells = <2>; | |
350 | status = "disabled"; | |
351 | }; | |
352 | ||
353 | pwm2: pwm@02084000 { | |
354 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
355 | reg = <0x02084000 0x4000>; | |
356 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
357 | clocks = <&clks IMX6UL_CLK_PWM2>, | |
358 | <&clks IMX6UL_CLK_PWM2>; | |
359 | clock-names = "ipg", "per"; | |
360 | #pwm-cells = <2>; | |
361 | status = "disabled"; | |
362 | }; | |
363 | ||
364 | pwm3: pwm@02088000 { | |
365 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
366 | reg = <0x02088000 0x4000>; | |
367 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
368 | clocks = <&clks IMX6UL_CLK_PWM3>, | |
369 | <&clks IMX6UL_CLK_PWM3>; | |
370 | clock-names = "ipg", "per"; | |
371 | #pwm-cells = <2>; | |
372 | status = "disabled"; | |
373 | }; | |
374 | ||
375 | pwm4: pwm@0208c000 { | |
376 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
377 | reg = <0x0208c000 0x4000>; | |
378 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
379 | clocks = <&clks IMX6UL_CLK_PWM4>, | |
380 | <&clks IMX6UL_CLK_PWM4>; | |
381 | clock-names = "ipg", "per"; | |
382 | #pwm-cells = <2>; | |
383 | status = "disabled"; | |
384 | }; | |
385 | ||
c4aac1b1 LW |
386 | can1: flexcan@02090000 { |
387 | compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; | |
388 | reg = <0x02090000 0x4000>; | |
389 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
390 | clocks = <&clks IMX6UL_CLK_CAN1_IPG>, | |
391 | <&clks IMX6UL_CLK_CAN1_SERIAL>; | |
392 | clock-names = "ipg", "per"; | |
393 | status = "disabled"; | |
394 | }; | |
395 | ||
396 | can2: flexcan@02094000 { | |
397 | compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; | |
398 | reg = <0x02094000 0x4000>; | |
399 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
400 | clocks = <&clks IMX6UL_CLK_CAN2_IPG>, | |
401 | <&clks IMX6UL_CLK_CAN2_SERIAL>; | |
402 | clock-names = "ipg", "per"; | |
403 | status = "disabled"; | |
404 | }; | |
405 | ||
a5fcccbc FL |
406 | gpt1: gpt@02098000 { |
407 | compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; | |
408 | reg = <0x02098000 0x4000>; | |
409 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
410 | clocks = <&clks IMX6UL_CLK_GPT1_BUS>, | |
411 | <&clks IMX6UL_CLK_GPT1_SERIAL>; | |
412 | clock-names = "ipg", "per"; | |
413 | }; | |
414 | ||
415 | gpio1: gpio@0209c000 { | |
416 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
417 | reg = <0x0209c000 0x4000>; | |
418 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, | |
419 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
420 | gpio-controller; | |
421 | #gpio-cells = <2>; | |
422 | interrupt-controller; | |
423 | #interrupt-cells = <2>; | |
bb728d66 VZ |
424 | gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, |
425 | <&iomuxc 16 33 16>; | |
a5fcccbc FL |
426 | }; |
427 | ||
428 | gpio2: gpio@020a0000 { | |
429 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
430 | reg = <0x020a0000 0x4000>; | |
431 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
432 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
433 | gpio-controller; | |
434 | #gpio-cells = <2>; | |
435 | interrupt-controller; | |
436 | #interrupt-cells = <2>; | |
bb728d66 | 437 | gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; |
a5fcccbc FL |
438 | }; |
439 | ||
440 | gpio3: gpio@020a4000 { | |
441 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
442 | reg = <0x020a4000 0x4000>; | |
443 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, | |
444 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
445 | gpio-controller; | |
446 | #gpio-cells = <2>; | |
447 | interrupt-controller; | |
448 | #interrupt-cells = <2>; | |
bb728d66 | 449 | gpio-ranges = <&iomuxc 0 65 29>; |
a5fcccbc FL |
450 | }; |
451 | ||
452 | gpio4: gpio@020a8000 { | |
453 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
454 | reg = <0x020a8000 0x4000>; | |
455 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
456 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
457 | gpio-controller; | |
458 | #gpio-cells = <2>; | |
459 | interrupt-controller; | |
460 | #interrupt-cells = <2>; | |
bb728d66 | 461 | gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; |
a5fcccbc FL |
462 | }; |
463 | ||
464 | gpio5: gpio@020ac000 { | |
465 | compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
466 | reg = <0x020ac000 0x4000>; | |
467 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | |
468 | <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
469 | gpio-controller; | |
470 | #gpio-cells = <2>; | |
471 | interrupt-controller; | |
472 | #interrupt-cells = <2>; | |
bb728d66 | 473 | gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; |
a5fcccbc FL |
474 | }; |
475 | ||
01f3dc7d FD |
476 | fec2: ethernet@020b4000 { |
477 | compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; | |
478 | reg = <0x020b4000 0x4000>; | |
479 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, | |
480 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
481 | clocks = <&clks IMX6UL_CLK_ENET>, | |
482 | <&clks IMX6UL_CLK_ENET_AHB>, | |
483 | <&clks IMX6UL_CLK_ENET_PTP>, | |
484 | <&clks IMX6UL_CLK_ENET2_REF_125M>, | |
485 | <&clks IMX6UL_CLK_ENET2_REF_125M>; | |
486 | clock-names = "ipg", "ahb", "ptp", | |
487 | "enet_clk_ref", "enet_out"; | |
488 | fsl,num-tx-queues=<1>; | |
489 | fsl,num-rx-queues=<1>; | |
490 | status = "disabled"; | |
491 | }; | |
492 | ||
ea1c1752 LW |
493 | kpp: kpp@020b8000 { |
494 | compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; | |
495 | reg = <0x020b8000 0x4000>; | |
496 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
497 | clocks = <&clks IMX6UL_CLK_KPP>; | |
498 | status = "disabled"; | |
499 | }; | |
500 | ||
a5fcccbc FL |
501 | wdog1: wdog@020bc000 { |
502 | compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; | |
503 | reg = <0x020bc000 0x4000>; | |
504 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
505 | clocks = <&clks IMX6UL_CLK_WDOG1>; | |
506 | }; | |
507 | ||
508 | wdog2: wdog@020c0000 { | |
509 | compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; | |
510 | reg = <0x020c0000 0x4000>; | |
511 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
512 | clocks = <&clks IMX6UL_CLK_WDOG2>; | |
513 | status = "disabled"; | |
514 | }; | |
515 | ||
516 | clks: ccm@020c4000 { | |
517 | compatible = "fsl,imx6ul-ccm"; | |
518 | reg = <0x020c4000 0x4000>; | |
519 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
520 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
521 | #clock-cells = <1>; | |
522 | clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; | |
523 | clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; | |
524 | }; | |
525 | ||
526 | anatop: anatop@020c8000 { | |
527 | compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", | |
528 | "syscon", "simple-bus"; | |
529 | reg = <0x020c8000 0x1000>; | |
530 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
531 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
532 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
533 | ||
298701ec | 534 | reg_3p0: regulator-3p0 { |
a5fcccbc FL |
535 | compatible = "fsl,anatop-regulator"; |
536 | regulator-name = "vdd3p0"; | |
537 | regulator-min-microvolt = <2625000>; | |
538 | regulator-max-microvolt = <3400000>; | |
539 | anatop-reg-offset = <0x120>; | |
540 | anatop-vol-bit-shift = <8>; | |
541 | anatop-vol-bit-width = <5>; | |
542 | anatop-min-bit-val = <0>; | |
543 | anatop-min-voltage = <2625000>; | |
544 | anatop-max-voltage = <3400000>; | |
545 | anatop-enable-bit = <0>; | |
546 | }; | |
547 | ||
298701ec | 548 | reg_arm: regulator-vddcore { |
a5fcccbc FL |
549 | compatible = "fsl,anatop-regulator"; |
550 | regulator-name = "cpu"; | |
551 | regulator-min-microvolt = <725000>; | |
552 | regulator-max-microvolt = <1450000>; | |
553 | regulator-always-on; | |
554 | anatop-reg-offset = <0x140>; | |
555 | anatop-vol-bit-shift = <0>; | |
556 | anatop-vol-bit-width = <5>; | |
557 | anatop-delay-reg-offset = <0x170>; | |
558 | anatop-delay-bit-shift = <24>; | |
559 | anatop-delay-bit-width = <2>; | |
560 | anatop-min-bit-val = <1>; | |
561 | anatop-min-voltage = <725000>; | |
562 | anatop-max-voltage = <1450000>; | |
563 | }; | |
564 | ||
298701ec | 565 | reg_soc: regulator-vddsoc { |
a5fcccbc FL |
566 | compatible = "fsl,anatop-regulator"; |
567 | regulator-name = "vddsoc"; | |
568 | regulator-min-microvolt = <725000>; | |
569 | regulator-max-microvolt = <1450000>; | |
570 | regulator-always-on; | |
571 | anatop-reg-offset = <0x140>; | |
572 | anatop-vol-bit-shift = <18>; | |
573 | anatop-vol-bit-width = <5>; | |
574 | anatop-delay-reg-offset = <0x170>; | |
575 | anatop-delay-bit-shift = <28>; | |
576 | anatop-delay-bit-width = <2>; | |
577 | anatop-min-bit-val = <1>; | |
578 | anatop-min-voltage = <725000>; | |
579 | anatop-max-voltage = <1450000>; | |
580 | }; | |
581 | }; | |
582 | ||
583 | usbphy1: usbphy@020c9000 { | |
584 | compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; | |
585 | reg = <0x020c9000 0x1000>; | |
586 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; | |
587 | clocks = <&clks IMX6UL_CLK_USBPHY1>; | |
588 | phy-3p0-supply = <®_3p0>; | |
589 | fsl,anatop = <&anatop>; | |
590 | }; | |
591 | ||
592 | usbphy2: usbphy@020ca000 { | |
593 | compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; | |
594 | reg = <0x020ca000 0x1000>; | |
595 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
596 | clocks = <&clks IMX6UL_CLK_USBPHY2>; | |
597 | phy-3p0-supply = <®_3p0>; | |
598 | fsl,anatop = <&anatop>; | |
599 | }; | |
600 | ||
5b032872 AH |
601 | snvs: snvs@020cc000 { |
602 | compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; | |
603 | reg = <0x020cc000 0x4000>; | |
604 | ||
605 | snvs_rtc: snvs-rtc-lp { | |
606 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
607 | regmap = <&snvs>; | |
608 | offset = <0x34>; | |
609 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, | |
610 | <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
611 | }; | |
36032575 | 612 | |
ab0a05d8 AH |
613 | snvs_poweroff: snvs-poweroff { |
614 | compatible = "syscon-poweroff"; | |
615 | regmap = <&snvs>; | |
616 | offset = <0x38>; | |
617 | mask = <0x60>; | |
618 | status = "disabled"; | |
619 | }; | |
620 | ||
36032575 AH |
621 | snvs_pwrkey: snvs-powerkey { |
622 | compatible = "fsl,sec-v4.0-pwrkey"; | |
623 | regmap = <&snvs>; | |
624 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
625 | linux,keycode = <KEY_POWER>; | |
626 | wakeup-source; | |
627 | }; | |
5b032872 AH |
628 | }; |
629 | ||
a5fcccbc FL |
630 | epit1: epit@020d0000 { |
631 | reg = <0x020d0000 0x4000>; | |
632 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
633 | }; | |
634 | ||
635 | epit2: epit@020d4000 { | |
636 | reg = <0x020d4000 0x4000>; | |
637 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
638 | }; | |
639 | ||
640 | src: src@020d8000 { | |
641 | compatible = "fsl,imx6ul-src", "fsl,imx51-src"; | |
642 | reg = <0x020d8000 0x4000>; | |
643 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, | |
644 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
645 | #reset-cells = <1>; | |
646 | }; | |
647 | ||
648 | gpc: gpc@020dc000 { | |
649 | compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; | |
650 | reg = <0x020dc000 0x4000>; | |
18619ff5 AH |
651 | interrupt-controller; |
652 | #interrupt-cells = <3>; | |
a5fcccbc | 653 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
18619ff5 | 654 | interrupt-parent = <&intc>; |
a5fcccbc FL |
655 | }; |
656 | ||
657 | iomuxc: iomuxc@020e0000 { | |
658 | compatible = "fsl,imx6ul-iomuxc"; | |
659 | reg = <0x020e0000 0x4000>; | |
660 | }; | |
661 | ||
662 | gpr: iomuxc-gpr@020e4000 { | |
0f39c504 AH |
663 | compatible = "fsl,imx6ul-iomuxc-gpr", |
664 | "fsl,imx6q-iomuxc-gpr", "syscon"; | |
a5fcccbc FL |
665 | reg = <0x020e4000 0x4000>; |
666 | }; | |
667 | ||
668 | gpt2: gpt@020e8000 { | |
669 | compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; | |
670 | reg = <0x020e8000 0x4000>; | |
671 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
d97ca99f LW |
672 | clocks = <&clks IMX6UL_CLK_GPT2_BUS>, |
673 | <&clks IMX6UL_CLK_GPT2_SERIAL>; | |
a5fcccbc FL |
674 | clock-names = "ipg", "per"; |
675 | }; | |
676 | ||
76758c6a LW |
677 | sdma: sdma@020ec000 { |
678 | compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", | |
679 | "fsl,imx35-sdma"; | |
680 | reg = <0x020ec000 0x4000>; | |
681 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
682 | clocks = <&clks IMX6UL_CLK_SDMA>, | |
683 | <&clks IMX6UL_CLK_SDMA>; | |
684 | clock-names = "ipg", "ahb"; | |
685 | #dma-cells = <3>; | |
686 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; | |
687 | }; | |
688 | ||
a5fcccbc FL |
689 | pwm5: pwm@020f0000 { |
690 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
691 | reg = <0x020f0000 0x4000>; | |
692 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
c530d23a LW |
693 | clocks = <&clks IMX6UL_CLK_PWM5>, |
694 | <&clks IMX6UL_CLK_PWM5>; | |
a5fcccbc FL |
695 | clock-names = "ipg", "per"; |
696 | #pwm-cells = <2>; | |
dd135095 | 697 | status = "disabled"; |
a5fcccbc FL |
698 | }; |
699 | ||
700 | pwm6: pwm@020f4000 { | |
701 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
702 | reg = <0x020f4000 0x4000>; | |
703 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
c530d23a LW |
704 | clocks = <&clks IMX6UL_CLK_PWM6>, |
705 | <&clks IMX6UL_CLK_PWM6>; | |
a5fcccbc FL |
706 | clock-names = "ipg", "per"; |
707 | #pwm-cells = <2>; | |
dd135095 | 708 | status = "disabled"; |
a5fcccbc FL |
709 | }; |
710 | ||
711 | pwm7: pwm@020f8000 { | |
712 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
713 | reg = <0x020f8000 0x4000>; | |
714 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
c530d23a LW |
715 | clocks = <&clks IMX6UL_CLK_PWM7>, |
716 | <&clks IMX6UL_CLK_PWM7>; | |
a5fcccbc FL |
717 | clock-names = "ipg", "per"; |
718 | #pwm-cells = <2>; | |
dd135095 | 719 | status = "disabled"; |
a5fcccbc FL |
720 | }; |
721 | ||
722 | pwm8: pwm@020fc000 { | |
723 | compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
724 | reg = <0x020fc000 0x4000>; | |
725 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
c530d23a LW |
726 | clocks = <&clks IMX6UL_CLK_PWM8>, |
727 | <&clks IMX6UL_CLK_PWM8>; | |
a5fcccbc FL |
728 | clock-names = "ipg", "per"; |
729 | #pwm-cells = <2>; | |
dd135095 | 730 | status = "disabled"; |
a5fcccbc FL |
731 | }; |
732 | }; | |
733 | ||
734 | aips2: aips-bus@02100000 { | |
735 | compatible = "fsl,aips-bus", "simple-bus"; | |
736 | #address-cells = <1>; | |
737 | #size-cells = <1>; | |
738 | reg = <0x02100000 0x100000>; | |
739 | ranges; | |
740 | ||
cad2cb69 FL |
741 | usbotg1: usb@02184000 { |
742 | compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; | |
743 | reg = <0x02184000 0x200>; | |
744 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
745 | clocks = <&clks IMX6UL_CLK_USBOH3>; | |
746 | fsl,usbphy = <&usbphy1>; | |
747 | fsl,usbmisc = <&usbmisc 0>; | |
748 | fsl,anatop = <&anatop>; | |
9493bf54 | 749 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
750 | tx-burst-size-dword = <0x10>; |
751 | rx-burst-size-dword = <0x10>; | |
cad2cb69 FL |
752 | status = "disabled"; |
753 | }; | |
754 | ||
755 | usbotg2: usb@02184200 { | |
756 | compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; | |
757 | reg = <0x02184200 0x200>; | |
758 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
759 | clocks = <&clks IMX6UL_CLK_USBOH3>; | |
760 | fsl,usbphy = <&usbphy2>; | |
761 | fsl,usbmisc = <&usbmisc 1>; | |
9493bf54 | 762 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
763 | tx-burst-size-dword = <0x10>; |
764 | rx-burst-size-dword = <0x10>; | |
cad2cb69 FL |
765 | status = "disabled"; |
766 | }; | |
767 | ||
768 | usbmisc: usbmisc@02184800 { | |
769 | #index-cells = <1>; | |
770 | compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; | |
771 | reg = <0x02184800 0x200>; | |
772 | }; | |
773 | ||
01f3dc7d FD |
774 | fec1: ethernet@02188000 { |
775 | compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; | |
776 | reg = <0x02188000 0x4000>; | |
777 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
778 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
779 | clocks = <&clks IMX6UL_CLK_ENET>, | |
780 | <&clks IMX6UL_CLK_ENET_AHB>, | |
781 | <&clks IMX6UL_CLK_ENET_PTP>, | |
782 | <&clks IMX6UL_CLK_ENET_REF>, | |
783 | <&clks IMX6UL_CLK_ENET_REF>; | |
784 | clock-names = "ipg", "ahb", "ptp", | |
785 | "enet_clk_ref", "enet_out"; | |
786 | fsl,num-tx-queues=<1>; | |
787 | fsl,num-rx-queues=<1>; | |
788 | status = "disabled"; | |
789 | }; | |
790 | ||
a5fcccbc FL |
791 | usdhc1: usdhc@02190000 { |
792 | compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; | |
793 | reg = <0x02190000 0x4000>; | |
794 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
795 | clocks = <&clks IMX6UL_CLK_USDHC1>, | |
796 | <&clks IMX6UL_CLK_USDHC1>, | |
797 | <&clks IMX6UL_CLK_USDHC1>; | |
798 | clock-names = "ipg", "ahb", "per"; | |
799 | bus-width = <4>; | |
800 | status = "disabled"; | |
801 | }; | |
802 | ||
803 | usdhc2: usdhc@02194000 { | |
804 | compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; | |
805 | reg = <0x02194000 0x4000>; | |
806 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
807 | clocks = <&clks IMX6UL_CLK_USDHC2>, | |
808 | <&clks IMX6UL_CLK_USDHC2>, | |
809 | <&clks IMX6UL_CLK_USDHC2>; | |
810 | clock-names = "ipg", "ahb", "per"; | |
811 | bus-width = <4>; | |
812 | status = "disabled"; | |
813 | }; | |
814 | ||
aab8ec0c FE |
815 | adc1: adc@02198000 { |
816 | compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; | |
817 | reg = <0x02198000 0x4000>; | |
818 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
819 | clocks = <&clks IMX6UL_CLK_ADC1>; | |
820 | num-channels = <2>; | |
821 | clock-names = "adc"; | |
822 | fsl,adck-max-frequency = <30000000>, <40000000>, | |
823 | <20000000>; | |
824 | status = "disabled"; | |
825 | }; | |
826 | ||
a5fcccbc FL |
827 | i2c1: i2c@021a0000 { |
828 | #address-cells = <1>; | |
829 | #size-cells = <0>; | |
830 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
831 | reg = <0x021a0000 0x4000>; | |
832 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
833 | clocks = <&clks IMX6UL_CLK_I2C1>; | |
834 | status = "disabled"; | |
835 | }; | |
836 | ||
837 | i2c2: i2c@021a4000 { | |
838 | #address-cells = <1>; | |
839 | #size-cells = <0>; | |
840 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
841 | reg = <0x021a4000 0x4000>; | |
842 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
843 | clocks = <&clks IMX6UL_CLK_I2C2>; | |
844 | status = "disabled"; | |
845 | }; | |
846 | ||
847 | i2c3: i2c@021a8000 { | |
848 | #address-cells = <1>; | |
849 | #size-cells = <0>; | |
850 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
851 | reg = <0x021a8000 0x4000>; | |
852 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
853 | clocks = <&clks IMX6UL_CLK_I2C3>; | |
854 | status = "disabled"; | |
855 | }; | |
856 | ||
51a37443 AH |
857 | mmdc: mmdc@021b0000 { |
858 | compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; | |
859 | reg = <0x021b0000 0x4000>; | |
860 | }; | |
861 | ||
6fe01eb7 LW |
862 | lcdif: lcdif@021c8000 { |
863 | compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; | |
864 | reg = <0x021c8000 0x4000>; | |
865 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
866 | clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, | |
867 | <&clks IMX6UL_CLK_LCDIF_APB>, | |
868 | <&clks IMX6UL_CLK_DUMMY>; | |
869 | clock-names = "pix", "axi", "disp_axi"; | |
870 | status = "disabled"; | |
871 | }; | |
872 | ||
5ff807a5 FL |
873 | qspi: qspi@021e0000 { |
874 | #address-cells = <1>; | |
875 | #size-cells = <0>; | |
876 | compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; | |
877 | reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; | |
878 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
879 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
880 | clocks = <&clks IMX6UL_CLK_QSPI>, | |
881 | <&clks IMX6UL_CLK_QSPI>; | |
882 | clock-names = "qspi_en", "qspi"; | |
883 | status = "disabled"; | |
884 | }; | |
885 | ||
a5fcccbc FL |
886 | uart2: serial@021e8000 { |
887 | compatible = "fsl,imx6ul-uart", | |
888 | "fsl,imx6q-uart"; | |
889 | reg = <0x021e8000 0x4000>; | |
890 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
891 | clocks = <&clks IMX6UL_CLK_UART2_IPG>, | |
892 | <&clks IMX6UL_CLK_UART2_SERIAL>; | |
893 | clock-names = "ipg", "per"; | |
894 | status = "disabled"; | |
895 | }; | |
896 | ||
897 | uart3: serial@021ec000 { | |
898 | compatible = "fsl,imx6ul-uart", | |
899 | "fsl,imx6q-uart"; | |
900 | reg = <0x021ec000 0x4000>; | |
901 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
902 | clocks = <&clks IMX6UL_CLK_UART3_IPG>, | |
903 | <&clks IMX6UL_CLK_UART3_SERIAL>; | |
904 | clock-names = "ipg", "per"; | |
905 | status = "disabled"; | |
906 | }; | |
907 | ||
908 | uart4: serial@021f0000 { | |
909 | compatible = "fsl,imx6ul-uart", | |
910 | "fsl,imx6q-uart"; | |
911 | reg = <0x021f0000 0x4000>; | |
912 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
913 | clocks = <&clks IMX6UL_CLK_UART4_IPG>, | |
914 | <&clks IMX6UL_CLK_UART4_SERIAL>; | |
915 | clock-names = "ipg", "per"; | |
916 | status = "disabled"; | |
917 | }; | |
918 | ||
919 | uart5: serial@021f4000 { | |
920 | compatible = "fsl,imx6ul-uart", | |
921 | "fsl,imx6q-uart"; | |
922 | reg = <0x021f4000 0x4000>; | |
923 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
924 | clocks = <&clks IMX6UL_CLK_UART5_IPG>, | |
925 | <&clks IMX6UL_CLK_UART5_SERIAL>; | |
926 | clock-names = "ipg", "per"; | |
927 | status = "disabled"; | |
928 | }; | |
929 | ||
930 | i2c4: i2c@021f8000 { | |
931 | #address-cells = <1>; | |
932 | #size-cells = <0>; | |
933 | compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
934 | reg = <0x021f8000 0x4000>; | |
935 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
936 | clocks = <&clks IMX6UL_CLK_I2C4>; | |
937 | status = "disabled"; | |
938 | }; | |
939 | ||
940 | uart6: serial@021fc000 { | |
941 | compatible = "fsl,imx6ul-uart", | |
942 | "fsl,imx6q-uart"; | |
943 | reg = <0x021fc000 0x4000>; | |
944 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
945 | clocks = <&clks IMX6UL_CLK_UART6_IPG>, | |
946 | <&clks IMX6UL_CLK_UART6_SERIAL>; | |
947 | clock-names = "ipg", "per"; | |
948 | status = "disabled"; | |
949 | }; | |
950 | }; | |
951 | }; | |
952 | }; |