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Merge tag 'omap-for-v5.1/dt-cpsw-phy' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / imx7-colibri.dtsi
CommitLineData
b326629f
SA		 1/*
2 * Copyright 2016 Toradex AG
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/ {
44 bl: backlight {
45 compatible = "pwm-backlight";
6deb2260
SA		 46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_gpio_bl_on>;
9be48d2d 48 pwms = <&pwm1 0 5000000 0>;
6deb2260 49 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
b326629f
SA		 50 };
51
8e901935 52 reg_module_3v3: regulator-module-3v3 {
b326629f 53 compatible = "regulator-fixed";
8e901935
SA		 54 regulator-name = "+V3.3";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 };
58
59 reg_module_3v3_avdd: regulator-module-3v3-avdd {
60 compatible = "regulator-fixed";
61 regulator-name = "+V3.3_AVDD_AUDIO";
b326629f
SA		 62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
b326629f
SA		 64 };
65
3dc3336b
SA		 66 sound {
67 compatible = "simple-audio-card";
68 simple-audio-card,name = "imx7-sgtl5000";
69 simple-audio-card,format = "i2s";
70 simple-audio-card,bitclock-master = <&dailink_master>;
71 simple-audio-card,frame-master = <&dailink_master>;
72 simple-audio-card,cpu {
73 sound-dai = <&sai1>;
74 };
75
76 dailink_master: simple-audio-card,codec {
77 sound-dai = <&codec>;
78 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
79 };
80 };
b326629f
SA		 81};
82
83&adc1 {
c9171bb5 84 vref-supply = <&reg_DCDC3>;
b326629f
SA		 85};
86
87&adc2 {
c9171bb5 88 vref-supply = <&reg_DCDC3>;
b326629f
SA		 89};
90
91&cpu0 {
5dc2dcf5 92 cpu-supply = <&reg_DCDC2>;
b326629f
SA		 93};
94
66d59b67
SA		 95&ecspi3 {
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
98 cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
99};
100
b326629f
SA		 101&fec1 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_enet1>;
104 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
105 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
106 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
107 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
108 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
109 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
110 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
111 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
112 assigned-clock-rates = <0>, <100000000>;
113 phy-mode = "rmii";
114 phy-supply = <&reg_LDO1>;
115 fsl,magic-packet;
116};
117
8528181d
SA		 118&gpmi {
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_gpmi_nand>;
121 fsl,use-minimum-ecc;
122 nand-on-flash-bbt;
123 nand-ecc-mode = "hw";
8528181d
SA		 124};
125
b326629f
SA		 126&i2c1 {
127 clock-frequency = <100000>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
130 status = "okay";
131
8dccafaa 132 codec: sgtl5000@a {
3dc3336b
SA		 133 compatible = "fsl,sgtl5000";
134 #sound-dai-cells = <0>;
135 reg = <0x0a>;
136 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_sai1_mclk>;
139 VDDA-supply = <&reg_module_3v3_avdd>;
140 VDDIO-supply = <&reg_module_3v3>;
141 VDDD-supply = <&reg_DCDC3>;
142 };
143
b326629f
SA		 144 ad7879@2c {
145 compatible = "adi,ad7879-1";
146 reg = <0x2c>;
147 interrupt-parent = <&gpio1>;
148 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
149 touchscreen-max-pressure = <4096>;
150 adi,resistance-plate-x = <120>;
151 adi,first-conversion-delay = /bits/ 8 <3>;
152 adi,acquisition-time = /bits/ 8 <1>;
153 adi,median-filter-size = /bits/ 8 <2>;
154 adi,averaging = /bits/ 8 <1>;
155 adi,conversion-interval = /bits/ 8 <255>;
156 };
157
158 pmic@33 {
159 compatible = "ricoh,rn5t567";
160 reg = <0x33>;
161
162 regulators {
163 reg_DCDC1: DCDC1 { /* V1.0_SOC */
55dfc902
SA		 164 regulator-min-microvolt = <1000000>;
165 regulator-max-microvolt = <1100000>;
b326629f
SA		 166 regulator-boot-on;
167 regulator-always-on;
168 };
169
170 reg_DCDC2: DCDC2 { /* V1.1_ARM */
55dfc902
SA		 171 regulator-min-microvolt = <975000>;
172 regulator-max-microvolt = <1100000>;
b326629f
SA		 173 regulator-boot-on;
174 regulator-always-on;
175 };
176
177 reg_DCDC3: DCDC3 { /* V1.8 */
55dfc902
SA		 178 regulator-min-microvolt = <1800000>;
179 regulator-max-microvolt = <1800000>;
b326629f
SA		 180 regulator-boot-on;
181 regulator-always-on;
182 };
183
184 reg_DCDC4: DCDC4 { /* V1.35_DRAM */
55dfc902
SA		 185 regulator-min-microvolt = <1350000>;
186 regulator-max-microvolt = <1350000>;
b326629f
SA		 187 regulator-boot-on;
188 regulator-always-on;
189 };
190
191 reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
192 regulator-min-microvolt = <1800000>;
193 regulator-max-microvolt = <3300000>;
8f4c8bd9 194 regulator-boot-on;
b326629f
SA		 195 };
196
197 reg_LDO2: LDO2 { /* +V1.8_SD */
55dfc902
SA		 198 regulator-min-microvolt = <1800000>;
199 regulator-max-microvolt = <3300000>;
b326629f
SA		 200 regulator-boot-on;
201 regulator-always-on;
202 };
203
204 reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
55dfc902
SA		 205 regulator-min-microvolt = <3300000>;
206 regulator-max-microvolt = <3300000>;
b326629f
SA		 207 regulator-boot-on;
208 regulator-always-on;
209 };
210
211 reg_LDO4: LDO4 { /* V1.8_LPSR */
55dfc902
SA		 212 regulator-min-microvolt = <1800000>;
213 regulator-max-microvolt = <1800000>;
b326629f
SA		 214 regulator-boot-on;
215 regulator-always-on;
216 };
217
218 reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
55dfc902
SA		 219 regulator-min-microvolt = <3300000>;
220 regulator-max-microvolt = <3300000>;
b326629f
SA		 221 regulator-boot-on;
222 regulator-always-on;
223 };
224 };
225 };
226};
227
228&i2c4 {
229 clock-frequency = <100000>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_i2c4>;
232};
233
234&lcdif {
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_lcdif_dat
237 &pinctrl_lcdif_ctrl>;
238};
239
240&pwm1 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_pwm1>;
243};
244
245&pwm2 {
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_pwm2>;
248};
249
250&pwm3 {
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_pwm3>;
253};
254
255&pwm4 {
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_pwm4>;
258};
259
260&reg_1p0d {
261 vin-supply = <&reg_DCDC3>;
262};
263
3dc3336b
SA		 264&sai1 {
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_sai1>;
267 status = "okay";
268};
269
b326629f
SA		 270&snvs_pwrkey {
271 status = "disabled";
272};
273
274&uart1 {
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
277 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
278 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
279 uart-has-rtscts;
280 fsl,dte-mode;
281};
282
283&uart2 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_uart2>;
286 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
287 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
288 uart-has-rtscts;
289 fsl,dte-mode;
290};
291
292&uart3 {
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_uart3>;
295 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
296 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
297 fsl,dte-mode;
298};
299
300&usbotg1 {
301 dr_mode = "host";
302};
303
987a2250
SA		 304&usdhc1 {
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
307 no-1-8-v;
308 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
309 disable-wp;
49e6ce61 310 vqmmc-supply = <&reg_LDO2>;
987a2250
SA		 311};
312
f928a4a3
SA		 313&usdhc3 {
314 pinctrl-names = "default", "state_100mhz", "state_200mhz";
315 pinctrl-0 = <&pinctrl_usdhc3>;
316 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
317 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
318 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
319 assigned-clock-rates = <400000000>;
320 bus-width = <8>;
321 fsl,tuning-step = <2>;
322 max-frequency = <100000000>;
323 vmmc-supply = <&reg_module_3v3>;
324 vqmmc-supply = <&reg_DCDC3>;
325 non-removable;
326};
327
b326629f
SA		 328&iomuxc {
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
331
332 pinctrl_gpio1: gpio1-grp {
333 fsl,pins = <
ffb2e259
SA		 334 MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */
335 MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x74 /* SODIMM 63 */
ffb2e259 336 MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
b326629f 337 MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
ffb2e259 338 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
b326629f
SA		 339 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
340 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
341 MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
ffb2e259
SA		 342 MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
343 MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 */
b326629f
SA		 344 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
345 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
346 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
347 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */
348 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */
349 MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */
350 MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */
351 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */
352 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
353 MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
354 MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
c2e70bbb 355 MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
b326629f
SA		 356 MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
357 MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
358 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
359 MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
ffb2e259 360 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x74 /* SODIMM 106 */
b326629f
SA		 361 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
362 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
363 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
364 MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */
365 MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */
366 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */
367 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */
368 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */
369 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */
370 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */
371 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */
372 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */
373 MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */
374 MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */
375 MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */
376 MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */
377 MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */
378 >;
379 };
380
381 pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
382 fsl,pins = <
383 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
ffb2e259 384 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */
b326629f
SA		 385 MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
386 MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
387 MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */
388 MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */
389 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */
390 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */
391 MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */
392 MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */
393 MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */
394 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */
395 >;
396 };
397
398 pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
399 fsl,pins = <
400 MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */
401 MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
402 MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
403 MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
ffb2e259
SA		 404 MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */
405 MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */
b326629f
SA		 406 >;
407 };
408
409 pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
410 fsl,pins = <
411 MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */
412 MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */
413 >;
414 };
415
416 pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
417 fsl,pins = <
418 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
419 >;
420 };
421
66d59b67
SA		 422 pinctrl_can_int: can-int-grp {
423 fsl,pins = <
424 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
425 >;
426 };
427
b326629f
SA		 428 pinctrl_enet1: enet1grp {
429 fsl,pins = <
430 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
431 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
432 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
433 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
434 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73
435
436 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
437 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73
438 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73
439 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73
440 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
441 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
442 >;
443 };
444
445 pinctrl_ecspi3_cs: ecspi3-cs-grp {
446 fsl,pins = <
447 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
448 >;
449 };
450
451 pinctrl_ecspi3: ecspi3-grp {
452 fsl,pins = <
453 MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
454 MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
455 MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
456 >;
457 };
458
459 pinctrl_flexcan2: flexcan2-grp {
460 fsl,pins = <
461 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
462 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
463 >;
464 };
465
6deb2260
SA		 466 pinctrl_gpio_bl_on: gpio-bl-on {
467 fsl,pins = <
468 MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */
469 >;
470 };
471
b326629f
SA		 472 pinctrl_gpmi_nand: gpmi-nand-grp {
473 fsl,pins = <
474 MX7D_PAD_SD3_CLK__NAND_CLE 0x71
475 MX7D_PAD_SD3_CMD__NAND_ALE 0x71
476 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
b326629f
SA		 477 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
478 MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
479 MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
480 MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
481 MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
482 MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
483 MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
484 MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
485 MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
486 MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
487 MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
488 >;
489 };
490
491 pinctrl_i2c4: i2c4-grp {
492 fsl,pins = <
493 MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
494 MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
495 >;
496 };
497
498 pinctrl_lcdif_dat: lcdif-dat-grp {
499 fsl,pins = <
500 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
501 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
502 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
503 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
504 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
505 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
506 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
507 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
508 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
509 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
510 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
511 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
512 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
513 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
514 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
515 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
516 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
517 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
518 >;
519 };
520
521 pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
522 fsl,pins = <
523 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
524 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
525 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
526 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
527 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
528 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
529 >;
530 };
531
532 pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
533 fsl,pins = <
534 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
535 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
536 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
537 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
538 >;
539 };
540
541 pinctrl_pwm1: pwm1-grp {
542 fsl,pins = <
543 MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79
e95723b5 544 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4
b326629f
SA		 545 >;
546 };
547
548 pinctrl_pwm2: pwm2-grp {
549 fsl,pins = <
550 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79
551 >;
552 };
553
554 pinctrl_pwm3: pwm3-grp {
555 fsl,pins = <
556 MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79
557 >;
558 };
559
560 pinctrl_pwm4: pwm4-grp {
561 fsl,pins = <
562 MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79
e95723b5 563 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4
b326629f
SA		 564 >;
565 };
566
567 pinctrl_uart1: uart1-grp {
568 fsl,pins = <
569 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
570 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
571 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
572 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
573 >;
574 };
575
576 pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
577 fsl,pins = <
578 MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
579 MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
580 >;
581 };
582
583 pinctrl_uart2: uart2-grp {
584 fsl,pins = <
585 MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
586 MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
587 MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
588 MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
589 >;
590 };
591 pinctrl_uart3: uart3-grp {
592 fsl,pins = <
593 MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
594 MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
595 >;
596 };
597
7e81cb3d 598 pinctrl_usbh_reg: gpio-usbh-vbus {
b326629f
SA		 599 fsl,pins = <
600 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
601 >;
602 };
603
604 pinctrl_usdhc1: usdhc1-grp {
605 fsl,pins = <
606 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
607 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
608 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
609 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
610 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
611 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
612 >;
613 };
614
f928a4a3
SA		 615 pinctrl_usdhc3: usdhc3grp {
616 fsl,pins = <
617 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
618 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
619 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
620 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
621 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
622 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
623 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
624 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
625 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
626 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
627 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
628 >;
629 };
630
631 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
632 fsl,pins = <
633 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
634 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
635 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
636 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
637 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
638 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
639 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
640 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
641 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
642 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
643 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
644 >;
645 };
646
647 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
648 fsl,pins = <
649 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
650 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
651 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
652 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
653 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
654 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
655 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
656 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
657 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
658 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
659 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
660 >;
661 };
662
b326629f
SA		 663 pinctrl_sai1: sai1-grp {
664 fsl,pins = <
b326629f
SA		 665 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
666 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
667 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
668 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
669 >;
670 };
3dc3336b
SA		 671
672 pinctrl_sai1_mclk: sai1grp_mclk {
673 fsl,pins = <
674 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
675 >;
676 };
b326629f
SA		 677};
678
679&iomuxc_lpsr {
680 pinctrl-names = "default";
681 pinctrl-0 = <&pinctrl_gpio_lpsr>;
682
683 pinctrl_gpio_lpsr: gpio1-grp {
684 fsl,pins = <
213e51ca
SH		 685 MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x59
686 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59
687 MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59
b326629f
SA		 688 >;
689 };
690
691 pinctrl_i2c1: i2c1-grp {
692 fsl,pins = <
213e51ca
SH		 693 MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
694 MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
b326629f
SA		 695 >;
696 };
697
698 pinctrl_cd_usdhc1: usdhc1-cd-grp {
699 fsl,pins = <
213e51ca 700 MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */
b326629f
SA		 701 >;
702 };
703
704 pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
705 fsl,pins = <
213e51ca
SH		 706 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */
707 MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */
b326629f
SA		 708 >;
709 };
710};
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