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b326629f SA |
1 | /* |
2 | * Copyright 2016 Toradex AG | |
3 | * | |
4 | * This file is dual-licensed: you can use it either under the terms | |
5 | * of the GPL or the X11 license, at your option. Note that this dual | |
6 | * licensing only applies to this file, and not this project as a | |
7 | * whole. | |
8 | * | |
9 | * a) This file is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of the | |
12 | * License, or (at your option) any later version. | |
13 | * | |
14 | * This file is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * Or, alternatively, | |
20 | * | |
21 | * b) Permission is hereby granted, free of charge, to any person | |
22 | * obtaining a copy of this software and associated documentation | |
23 | * files (the "Software"), to deal in the Software without | |
24 | * restriction, including without limitation the rights to use, | |
25 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
26 | * sell copies of the Software, and to permit persons to whom the | |
27 | * Software is furnished to do so, subject to the following | |
28 | * conditions: | |
29 | * | |
30 | * The above copyright notice and this permission notice shall be | |
31 | * included in all copies or substantial portions of the Software. | |
32 | * | |
33 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
34 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
35 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
36 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
37 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
38 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
39 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
40 | * OTHER DEALINGS IN THE SOFTWARE. | |
41 | */ | |
42 | ||
43 | / { | |
44 | bl: backlight { | |
45 | compatible = "pwm-backlight"; | |
46 | pwms = <&pwm1 0 5000000>; | |
47 | }; | |
48 | ||
49 | reg_3p3v: regulator-3p3v { | |
50 | compatible = "regulator-fixed"; | |
51 | regulator-name = "3P3V"; | |
52 | regulator-min-microvolt = <3300000>; | |
53 | regulator-max-microvolt = <3300000>; | |
54 | regulator-always-on; | |
55 | }; | |
56 | ||
57 | reg_vref_1v8: regulator-vref-1v8 { | |
58 | compatible = "regulator-fixed"; | |
59 | regulator-name = "vref-1v8"; | |
60 | regulator-min-microvolt = <1800000>; | |
61 | regulator-max-microvolt = <1800000>; | |
62 | }; | |
63 | }; | |
64 | ||
65 | &adc1 { | |
66 | vref-supply = <®_vref_1v8>; | |
67 | }; | |
68 | ||
69 | &adc2 { | |
70 | vref-supply = <®_vref_1v8>; | |
71 | }; | |
72 | ||
73 | &cpu0 { | |
74 | arm-supply = <®_DCDC2>; | |
75 | }; | |
76 | ||
77 | &fec1 { | |
78 | pinctrl-names = "default"; | |
79 | pinctrl-0 = <&pinctrl_enet1>; | |
80 | clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, | |
81 | <&clks IMX7D_ENET_AXI_ROOT_CLK>, | |
82 | <&clks IMX7D_ENET1_TIME_ROOT_CLK>, | |
83 | <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; | |
84 | clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; | |
85 | assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, | |
86 | <&clks IMX7D_ENET1_TIME_ROOT_CLK>; | |
87 | assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; | |
88 | assigned-clock-rates = <0>, <100000000>; | |
89 | phy-mode = "rmii"; | |
90 | phy-supply = <®_LDO1>; | |
91 | fsl,magic-packet; | |
92 | }; | |
93 | ||
94 | &i2c1 { | |
95 | clock-frequency = <100000>; | |
96 | pinctrl-names = "default"; | |
97 | pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; | |
98 | status = "okay"; | |
99 | ||
100 | ad7879@2c { | |
101 | compatible = "adi,ad7879-1"; | |
102 | reg = <0x2c>; | |
103 | interrupt-parent = <&gpio1>; | |
104 | interrupts = <13 IRQ_TYPE_EDGE_FALLING>; | |
105 | touchscreen-max-pressure = <4096>; | |
106 | adi,resistance-plate-x = <120>; | |
107 | adi,first-conversion-delay = /bits/ 8 <3>; | |
108 | adi,acquisition-time = /bits/ 8 <1>; | |
109 | adi,median-filter-size = /bits/ 8 <2>; | |
110 | adi,averaging = /bits/ 8 <1>; | |
111 | adi,conversion-interval = /bits/ 8 <255>; | |
112 | }; | |
113 | ||
114 | pmic@33 { | |
115 | compatible = "ricoh,rn5t567"; | |
116 | reg = <0x33>; | |
117 | ||
118 | regulators { | |
119 | reg_DCDC1: DCDC1 { /* V1.0_SOC */ | |
120 | regulator-min-microvolt = <975000>; | |
121 | regulator-max-microvolt = <1125000>; | |
122 | regulator-boot-on; | |
123 | regulator-always-on; | |
124 | }; | |
125 | ||
126 | reg_DCDC2: DCDC2 { /* V1.1_ARM */ | |
127 | regulator-min-microvolt = <975000>; | |
128 | regulator-max-microvolt = <1125000>; | |
129 | regulator-boot-on; | |
130 | regulator-always-on; | |
131 | }; | |
132 | ||
133 | reg_DCDC3: DCDC3 { /* V1.8 */ | |
134 | regulator-min-microvolt = <1775000>; | |
135 | regulator-max-microvolt = <1825000>; | |
136 | regulator-boot-on; | |
137 | regulator-always-on; | |
138 | }; | |
139 | ||
140 | reg_DCDC4: DCDC4 { /* V1.35_DRAM */ | |
141 | regulator-min-microvolt = <1325000>; | |
142 | regulator-max-microvolt = <1375000>; | |
143 | regulator-boot-on; | |
144 | regulator-always-on; | |
145 | }; | |
146 | ||
147 | reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */ | |
148 | regulator-min-microvolt = <1800000>; | |
149 | regulator-max-microvolt = <3300000>; | |
150 | regulator-always-on; | |
151 | }; | |
152 | ||
153 | reg_LDO2: LDO2 { /* +V1.8_SD */ | |
154 | regulator-min-microvolt = <1775000>; | |
155 | regulator-max-microvolt = <3325000>; | |
156 | regulator-boot-on; | |
157 | regulator-always-on; | |
158 | }; | |
159 | ||
160 | reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */ | |
161 | regulator-min-microvolt = <3275000>; | |
162 | regulator-max-microvolt = <3325000>; | |
163 | regulator-boot-on; | |
164 | regulator-always-on; | |
165 | }; | |
166 | ||
167 | reg_LDO4: LDO4 { /* V1.8_LPSR */ | |
168 | regulator-min-microvolt = <1775000>; | |
169 | regulator-max-microvolt = <1825000>; | |
170 | regulator-boot-on; | |
171 | regulator-always-on; | |
172 | }; | |
173 | ||
174 | reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */ | |
175 | regulator-min-microvolt = <1775000>; | |
176 | regulator-max-microvolt = <1825000>; | |
177 | regulator-boot-on; | |
178 | regulator-always-on; | |
179 | }; | |
180 | }; | |
181 | }; | |
182 | }; | |
183 | ||
184 | &i2c4 { | |
185 | clock-frequency = <100000>; | |
186 | pinctrl-names = "default"; | |
187 | pinctrl-0 = <&pinctrl_i2c4>; | |
188 | }; | |
189 | ||
190 | &lcdif { | |
191 | pinctrl-names = "default"; | |
192 | pinctrl-0 = <&pinctrl_lcdif_dat | |
193 | &pinctrl_lcdif_ctrl>; | |
194 | }; | |
195 | ||
196 | &pwm1 { | |
197 | pinctrl-names = "default"; | |
198 | pinctrl-0 = <&pinctrl_pwm1>; | |
199 | }; | |
200 | ||
201 | &pwm2 { | |
202 | pinctrl-names = "default"; | |
203 | pinctrl-0 = <&pinctrl_pwm2>; | |
204 | }; | |
205 | ||
206 | &pwm3 { | |
207 | pinctrl-names = "default"; | |
208 | pinctrl-0 = <&pinctrl_pwm3>; | |
209 | }; | |
210 | ||
211 | &pwm4 { | |
212 | pinctrl-names = "default"; | |
213 | pinctrl-0 = <&pinctrl_pwm4>; | |
214 | }; | |
215 | ||
216 | ®_1p0d { | |
217 | vin-supply = <®_DCDC3>; | |
218 | }; | |
219 | ||
220 | &snvs_pwrkey { | |
221 | status = "disabled"; | |
222 | }; | |
223 | ||
224 | &uart1 { | |
225 | pinctrl-names = "default"; | |
226 | pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>; | |
227 | assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; | |
228 | assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; | |
229 | uart-has-rtscts; | |
230 | fsl,dte-mode; | |
231 | }; | |
232 | ||
233 | &uart2 { | |
234 | pinctrl-names = "default"; | |
235 | pinctrl-0 = <&pinctrl_uart2>; | |
236 | assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; | |
237 | assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; | |
238 | uart-has-rtscts; | |
239 | fsl,dte-mode; | |
240 | }; | |
241 | ||
242 | &uart3 { | |
243 | pinctrl-names = "default"; | |
244 | pinctrl-0 = <&pinctrl_uart3>; | |
245 | assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; | |
246 | assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; | |
247 | fsl,dte-mode; | |
248 | }; | |
249 | ||
250 | &usbotg1 { | |
251 | dr_mode = "host"; | |
252 | }; | |
253 | ||
254 | &iomuxc { | |
255 | pinctrl-names = "default"; | |
256 | pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; | |
257 | ||
258 | pinctrl_gpio1: gpio1-grp { | |
259 | fsl,pins = < | |
260 | MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ | |
261 | MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ | |
262 | MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ | |
263 | MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0X14 /* SODIMM 77 */ | |
264 | MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ | |
265 | MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x14 /* SODIMM 91 */ | |
266 | MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ | |
267 | MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ | |
268 | MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ | |
269 | MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x14 /* SODIMM 105 */ | |
270 | MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x14 /* SODIMM 107 */ | |
271 | MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ | |
272 | MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ | |
273 | MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ | |
274 | MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */ | |
275 | MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */ | |
276 | MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */ | |
277 | MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */ | |
278 | MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */ | |
279 | MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ | |
280 | MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ | |
281 | MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ | |
282 | MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ | |
283 | MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ | |
284 | MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ | |
285 | MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ | |
286 | MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 */ | |
287 | MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ | |
288 | MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ | |
289 | MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ | |
290 | MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */ | |
291 | MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */ | |
292 | MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */ | |
293 | MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */ | |
294 | MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */ | |
295 | MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */ | |
296 | MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */ | |
297 | MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */ | |
298 | MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */ | |
299 | MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */ | |
300 | MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */ | |
301 | MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */ | |
302 | MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */ | |
303 | MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */ | |
304 | >; | |
305 | }; | |
306 | ||
307 | pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */ | |
308 | fsl,pins = < | |
309 | MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ | |
310 | MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x14 /* SODIMM 69 */ | |
311 | MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ | |
312 | MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ | |
313 | MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ | |
314 | MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ | |
315 | MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */ | |
316 | MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */ | |
317 | MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */ | |
318 | MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */ | |
319 | MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */ | |
320 | MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */ | |
321 | MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */ | |
322 | >; | |
323 | }; | |
324 | ||
325 | pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */ | |
326 | fsl,pins = < | |
327 | MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */ | |
328 | MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ | |
329 | MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ | |
330 | MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ | |
331 | MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x14 /* SODIMM 146 */ | |
332 | MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x14 /* SODIMM 148 */ | |
333 | >; | |
334 | }; | |
335 | ||
336 | pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */ | |
337 | fsl,pins = < | |
338 | MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */ | |
339 | MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */ | |
340 | >; | |
341 | }; | |
342 | ||
343 | pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */ | |
344 | fsl,pins = < | |
345 | MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 | |
346 | >; | |
347 | }; | |
348 | ||
349 | pinctrl_enet1: enet1grp { | |
350 | fsl,pins = < | |
351 | MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 | |
352 | MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 | |
353 | MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73 | |
354 | MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73 | |
355 | MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 | |
356 | ||
357 | MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73 | |
358 | MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73 | |
359 | MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73 | |
360 | MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73 | |
361 | MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 | |
362 | MX7D_PAD_SD2_WP__ENET1_MDC 0x3 | |
363 | >; | |
364 | }; | |
365 | ||
366 | pinctrl_ecspi3_cs: ecspi3-cs-grp { | |
367 | fsl,pins = < | |
368 | MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 | |
369 | >; | |
370 | }; | |
371 | ||
372 | pinctrl_ecspi3: ecspi3-grp { | |
373 | fsl,pins = < | |
374 | MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 | |
375 | MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 | |
376 | MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 | |
377 | >; | |
378 | }; | |
379 | ||
380 | pinctrl_flexcan2: flexcan2-grp { | |
381 | fsl,pins = < | |
382 | MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 | |
383 | MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 | |
384 | >; | |
385 | }; | |
386 | ||
387 | pinctrl_gpmi_nand: gpmi-nand-grp { | |
388 | fsl,pins = < | |
389 | MX7D_PAD_SD3_CLK__NAND_CLE 0x71 | |
390 | MX7D_PAD_SD3_CMD__NAND_ALE 0x71 | |
391 | MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 | |
392 | MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 | |
393 | MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 | |
394 | MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 | |
395 | MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 | |
396 | MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 | |
397 | MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 | |
398 | MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 | |
399 | MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 | |
400 | MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 | |
401 | MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 | |
402 | MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 | |
403 | MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 | |
404 | >; | |
405 | }; | |
406 | ||
407 | pinctrl_i2c4: i2c4-grp { | |
408 | fsl,pins = < | |
409 | MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f | |
410 | MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f | |
411 | >; | |
412 | }; | |
413 | ||
414 | pinctrl_lcdif_dat: lcdif-dat-grp { | |
415 | fsl,pins = < | |
416 | MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 | |
417 | MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 | |
418 | MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 | |
419 | MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 | |
420 | MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 | |
421 | MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 | |
422 | MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 | |
423 | MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 | |
424 | MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 | |
425 | MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 | |
426 | MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 | |
427 | MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 | |
428 | MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 | |
429 | MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 | |
430 | MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 | |
431 | MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 | |
432 | MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 | |
433 | MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 | |
434 | >; | |
435 | }; | |
436 | ||
437 | pinctrl_lcdif_dat_24: lcdif-dat-24-grp { | |
438 | fsl,pins = < | |
439 | MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 | |
440 | MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 | |
441 | MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 | |
442 | MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 | |
443 | MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 | |
444 | MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 | |
445 | >; | |
446 | }; | |
447 | ||
448 | pinctrl_lcdif_ctrl: lcdif-ctrl-grp { | |
449 | fsl,pins = < | |
450 | MX7D_PAD_LCD_CLK__LCD_CLK 0x79 | |
451 | MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 | |
452 | MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 | |
453 | MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 | |
454 | >; | |
455 | }; | |
456 | ||
457 | pinctrl_pwm1: pwm1-grp { | |
458 | fsl,pins = < | |
459 | MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 | |
460 | >; | |
461 | }; | |
462 | ||
463 | pinctrl_pwm2: pwm2-grp { | |
464 | fsl,pins = < | |
465 | MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79 | |
466 | >; | |
467 | }; | |
468 | ||
469 | pinctrl_pwm3: pwm3-grp { | |
470 | fsl,pins = < | |
471 | MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79 | |
472 | >; | |
473 | }; | |
474 | ||
475 | pinctrl_pwm4: pwm4-grp { | |
476 | fsl,pins = < | |
477 | MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 | |
478 | >; | |
479 | }; | |
480 | ||
481 | pinctrl_uart1: uart1-grp { | |
482 | fsl,pins = < | |
483 | MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 | |
484 | MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 | |
485 | MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 | |
486 | MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 | |
487 | >; | |
488 | }; | |
489 | ||
490 | pinctrl_uart1_ctrl1: uart1-ctrl1-grp { | |
491 | fsl,pins = < | |
492 | MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ | |
493 | MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ | |
494 | >; | |
495 | }; | |
496 | ||
497 | pinctrl_uart2: uart2-grp { | |
498 | fsl,pins = < | |
499 | MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79 | |
500 | MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79 | |
501 | MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79 | |
502 | MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79 | |
503 | >; | |
504 | }; | |
505 | pinctrl_uart3: uart3-grp { | |
506 | fsl,pins = < | |
507 | MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 | |
508 | MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 | |
509 | >; | |
510 | }; | |
511 | ||
512 | pinctrl_usbotg2_reg: gpio-usbotg2-vbus { | |
513 | fsl,pins = < | |
514 | MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */ | |
515 | >; | |
516 | }; | |
517 | ||
518 | pinctrl_usdhc1: usdhc1-grp { | |
519 | fsl,pins = < | |
520 | MX7D_PAD_SD1_CMD__SD1_CMD 0x59 | |
521 | MX7D_PAD_SD1_CLK__SD1_CLK 0x19 | |
522 | MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 | |
523 | MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 | |
524 | MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 | |
525 | MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 | |
526 | >; | |
527 | }; | |
528 | ||
529 | pinctrl_sai1: sai1-grp { | |
530 | fsl,pins = < | |
531 | MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f | |
532 | MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f | |
533 | MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f | |
534 | MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 | |
535 | MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f | |
536 | >; | |
537 | }; | |
538 | }; | |
539 | ||
540 | &iomuxc_lpsr { | |
541 | pinctrl-names = "default"; | |
542 | pinctrl-0 = <&pinctrl_gpio_lpsr>; | |
543 | ||
544 | pinctrl_gpio_lpsr: gpio1-grp { | |
545 | fsl,pins = < | |
546 | MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x59 | |
547 | MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x59 | |
548 | MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x59 | |
549 | >; | |
550 | }; | |
551 | ||
552 | pinctrl_i2c1: i2c1-grp { | |
553 | fsl,pins = < | |
554 | MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f | |
555 | MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f | |
556 | >; | |
557 | }; | |
558 | ||
559 | pinctrl_cd_usdhc1: usdhc1-cd-grp { | |
560 | fsl,pins = < | |
561 | MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */ | |
562 | >; | |
563 | }; | |
564 | ||
565 | pinctrl_uart1_ctrl2: uart1-ctrl2-grp { | |
566 | fsl,pins = < | |
567 | MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */ | |
568 | MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */ | |
569 | >; | |
570 | }; | |
571 | }; |