[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / imx7d-sdb.dts

/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include "imx7d.dtsi"

/ {
	model = "Freescale i.MX7 SabreSD Board";
	compatible = "fsl,imx7d-sdb", "fsl,imx7d";

	memory {
		reg = <0x80000000 0x80000000>;
	};

	spi4 {
		compatible = "spi-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_spi4>;
		gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
		gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
		cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		num-chipselects = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		extended_io: gpio-expander@0 {
			compatible = "fairchild,74hc595";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0>;
			registers-number = <1>;
			spi-max-frequency = <100000>;
		};
	};

	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb_otg1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usb_otg2_vbus: regulator-usb-otg1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb_otg2_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can2_3v3: regulator-can2-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "can2-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
	};

	reg_vref_1v8: regulator-vref-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "vref-1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_brcm: regulator-brcm {
		compatible = "regulator-fixed";
		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-name = "brcm_reg";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_brcm_reg>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <200000>;
	};
};

&adc1 {
	vref-supply = <&reg_vref_1v8>;
	status = "okay";
};

&adc2 {
	vref-supply = <&reg_vref_1v8>;
	status = "okay";
};

&cpu0 {
	arm-supply = <&sw1a_reg>;
};

&ecspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
	status = "okay";

	tsc2046@0 {
		compatible = "ti,tsc2046";
		reg = <0>;
		spi-max-frequency = <1000000>;
		pinctrl-names ="default";
		pinctrl-0 = <&pinctrl_tsc2046_pendown>;
		interrupt-parent = <&gpio2>;
		interrupts = <29 0>;
		pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
		ti,x-min = /bits/ 16 <0>;
		ti,x-max = /bits/ 16 <0>;
		ti,y-min = /bits/ 16 <0>;
		ti,y-max = /bits/ 16 <0>;
		ti,pressure-max = /bits/ 16 <0>;
		ti,x-plate-ohms = /bits/ 16 <400>;
		wakeup-source;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	assigned-clock-rates = <0>, <100000000>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			reg = <1>;
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	assigned-clock-rates = <0>, <100000000>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	status = "okay";
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic: pfuze3000@08 {
		compatible = "fsl,pfuze3000";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1a {
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1475000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			/* use sw1c_reg to align with pfuze100/pfuze200 */
			sw1c_reg: sw1b {
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1475000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3a_reg: sw3 {
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1650000>;
				regulator-boot-on;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen1_reg: vldo1 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen2_reg: vldo2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen3_reg: vccsd {
				regulator-min-microvolt = <2850000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen4_reg: v33 {
				regulator-min-microvolt = <2850000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen5_reg: vldo3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen6_reg: vldo4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	codec: wm8960@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
		clock-names = "mclk";
		wlf,shared-lrclk;
	};
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif>;
	display = <&display0>;
	status = "okay";

	display0: display {
		bits-per-pixel = <16>;
		bus-width = <24>;

		display-timings {
			native-mode = <&timing0>;

			timing0: timing0 {
				clock-frequency = <9200000>;
				hactive = <480>;
				vactive = <272>;
				hfront-porch = <8>;
				hback-porch = <4>;
				hsync-len = <41>;
				vback-porch = <2>;
				vfront-porch = <4>;
				vsync-len = <10>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};
	};
};

&pcie {
	reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usb_otg2_vbus>;
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
	wakeup-source;
	keep-power-in-suspend;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	wakeup-source;
	keep-power-in-suspend;
	non-removable;
	vmmc-supply = <&reg_brcm>;
	fsl,tuning-step = <2>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	assigned-clock-rates = <400000000>;
	bus-width = <8>;
	fsl,tuning-step = <2>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx7d-sdb {
		pinctrl_brcm_reg: brcmreggrp {
			fsl,pins = <
				MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x14
			>;
		};

		pinctrl_ecspi3: ecspi3grp {
			fsl,pins = <
				MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO	0x2
				MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI	0x2
				MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK	0x2
				MX7D_PAD_SD2_CD_B__GPIO5_IO9		0x59
			>;
		};

		pinctrl_enet1: enet1grp {
			fsl,pins = <
				MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x3
				MX7D_PAD_GPIO1_IO11__ENET1_MDC			0x3
				MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
				MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
				MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
				MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
				MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
				MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
				MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
				MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
				MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
				MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
				MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
				MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
			>;
		};

		pinctrl_enet2: enet2grp {
			fsl,pins = <
				MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x1
				MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x1
				MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x1
				MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2		0x1
				MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3		0x1
				MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL		0x1
				MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC		0x1
				MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0		0x1
				MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x1
				MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x1
				MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x1
				MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL		0x1
			>;
		};

		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX7D_PAD_UART3_CTS_B__GPIO4_IO7		0x14
				MX7D_PAD_ECSPI2_SS0__GPIO4_IO23		0x34  /* bt reg on */
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX7D_PAD_I2C1_SDA__I2C1_SDA		0x4000007f
				MX7D_PAD_I2C1_SCL__I2C1_SCL		0x4000007f
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX7D_PAD_I2C2_SDA__I2C2_SDA		0x4000007f
				MX7D_PAD_I2C2_SCL__I2C2_SCL		0x4000007f
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX7D_PAD_I2C3_SDA__I2C3_SDA		0x4000007f
				MX7D_PAD_I2C3_SCL__I2C3_SCL		0x4000007f
			>;
		};

		pinctrl_i2c4: i2c4grp {
			fsl,pins = <
				MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA		0x4000007f
				MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL		0x4000007f
			>;
		};

		pinctrl_lcdif: lcdifgrp {
			fsl,pins = <
				MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
				MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79
				MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79
				MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79
				MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79
				MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79
				MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79
				MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79
				MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79
				MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79
				MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79
				MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79
				MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79
				MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79
				MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79
				MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79
				MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79
				MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79
				MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79
				MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79
				MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79
				MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79
				MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79
				MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79
				MX7D_PAD_LCD_CLK__LCD_CLK		0x79
				MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x79
				MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x79
				MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x79
				MX7D_PAD_LCD_RESET__LCD_RESET		0x79
			>;
		};

		pinctrl_tsc2046_pendown: tsc2046_pendown {
			fsl,pins = <
				MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x59
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
				MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x79
			>;
		};

		pinctrl_uart5: uart5grp {
			fsl,pins = <
				MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX	0x79
				MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX	0x79
				MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS	0x79
				MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS	0x79
			>;
		};

		pinctrl_uart6: uart6grp {
			fsl,pins = <
				MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX	0x79
				MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX	0x79
				MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS	0x79
				MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS	0x79
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX7D_PAD_SD1_CMD__SD1_CMD		0x59
				MX7D_PAD_SD1_CLK__SD1_CLK		0x19
				MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
				MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
				MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */
				MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX7D_PAD_SD2_CMD__SD2_CMD		0x59
				MX7D_PAD_SD2_CLK__SD2_CLK		0x19
				MX7D_PAD_SD2_DATA0__SD2_DATA0		0x59
				MX7D_PAD_SD2_DATA1__SD2_DATA1		0x59
				MX7D_PAD_SD2_DATA2__SD2_DATA2		0x59
				MX7D_PAD_SD2_DATA3__SD2_DATA3		0x59
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
			fsl,pins = <
				MX7D_PAD_SD2_CMD__SD2_CMD		0x5a
				MX7D_PAD_SD2_CLK__SD2_CLK		0x1a
				MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5a
				MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5a
				MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5a
				MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5a
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
			fsl,pins = <
				MX7D_PAD_SD2_CMD__SD2_CMD		0x5b
				MX7D_PAD_SD2_CLK__SD2_CLK		0x1b
				MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5b
				MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5b
				MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5b
				MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5b
			>;
		};


		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX7D_PAD_SD3_CMD__SD3_CMD		0x59
				MX7D_PAD_SD3_CLK__SD3_CLK		0x19
				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x19
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
			fsl,pins = <
				MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
				MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1a
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
			fsl,pins = <
				MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
				MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1b
			>;
		};
	};
};

&iomuxc_lpsr {
	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B		0x74
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT		0x110b0
		>;

		pinctrl_spi4: spi4grp {
			fsl,pins = <
				MX7D_PAD_GPIO1_IO09__GPIO1_IO9	0x59
				MX7D_PAD_GPIO1_IO12__GPIO1_IO12	0x59
				MX7D_PAD_GPIO1_IO13__GPIO1_IO13	0x59
			>;
		};
	};
};
Commit	Line	Data
5db106bc FL	1	/*
	2	* Copyright (C) 2015 Freescale Semiconductor, Inc.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This file is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	/dts-v1/;
	44
a67970a2	45	#include "imx7d.dtsi"
5db106bc FL	46
	47	/ {
	48	model = "Freescale i.MX7 SabreSD Board";
	49	compatible = "fsl,imx7d-sdb", "fsl,imx7d";
	50
	51	memory {
	52	reg = <0x80000000 0x80000000>;
	53	};
	54
184f39b5 AS	55	spi4 {
	56	compatible = "spi-gpio";
	57	pinctrl-names = "default";
	58	pinctrl-0 = <&pinctrl_spi4>;
	59	gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
	60	gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
	61	cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	62	num-chipselects = <1>;
	63	#address-cells = <1>;
	64	#size-cells = <0>;
	65
	66	extended_io: gpio-expander@0 {
	67	compatible = "fairchild,74hc595";
	68	gpio-controller;
	69	#gpio-cells = <2>;
	70	reg = <0>;
	71	registers-number = <1>;
	72	spi-max-frequency = <100000>;
	73	};
	74	};
	75
b877039a FE	76	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
	77	compatible = "regulator-fixed";
	78	regulator-name = "usb_otg1_vbus";
	79	regulator-min-microvolt = <5000000>;
	80	regulator-max-microvolt = <5000000>;
	81	gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	82	enable-active-high;
	83	};
5db106bc	84
b877039a FE	85	reg_usb_otg2_vbus: regulator-usb-otg1-vbus {
	86	compatible = "regulator-fixed";
	87	regulator-name = "usb_otg2_vbus";
	88	regulator-min-microvolt = <5000000>;
	89	regulator-max-microvolt = <5000000>;
	90	gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
	91	enable-active-high;
	92	};
5db106bc	93
b877039a FE	94	reg_can2_3v3: regulator-can2-3v3 {
	95	compatible = "regulator-fixed";
	96	regulator-name = "can2-3v3";
	97	regulator-min-microvolt = <3300000>;
	98	regulator-max-microvolt = <3300000>;
	99	gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
	100	};
5db106bc	101
b877039a FE	102	reg_vref_1v8: regulator-vref-1v8 {
	103	compatible = "regulator-fixed";
	104	regulator-name = "vref-1v8";
	105	regulator-min-microvolt = <1800000>;
	106	regulator-max-microvolt = <1800000>;
5db106bc	107	};
6e823e97 FE	108
	109	reg_brcm: regulator-brcm {
	110	compatible = "regulator-fixed";
	111	gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
	112	enable-active-high;
	113	regulator-name = "brcm_reg";
	114	pinctrl-names = "default";
	115	pinctrl-0 = <&pinctrl_brcm_reg>;
	116	regulator-min-microvolt = <3300000>;
	117	regulator-max-microvolt = <3300000>;
	118	startup-delay-us = <200000>;
	119	};
5db106bc FL	120	};
5db106bc FL	121
64b83432 HC	122	&adc1 {
	123	vref-supply = <&reg_vref_1v8>;
	124	status = "okay";
	125	};
	126
	127	&adc2 {
	128	vref-supply = <&reg_vref_1v8>;
	129	status = "okay";
	130	};
	131
5db106bc FL	132	&cpu0 {
	133	arm-supply = <&sw1a_reg>;
	134	};
	135
d09e6bea	136	&ecspi3 {
d09e6bea DD	137	pinctrl-names = "default";
	138	pinctrl-0 = <&pinctrl_ecspi3>;
	139	cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
	140	status = "okay";
	141
	142	tsc2046@0 {
	143	compatible = "ti,tsc2046";
	144	reg = <0>;
	145	spi-max-frequency = <1000000>;
	146	pinctrl-names ="default";
	147	pinctrl-0 = <&pinctrl_tsc2046_pendown>;
	148	interrupt-parent = <&gpio2>;
	149	interrupts = <29 0>;
	150	pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
	151	ti,x-min = /bits/ 16 <0>;
	152	ti,x-max = /bits/ 16 <0>;
	153	ti,y-min = /bits/ 16 <0>;
	154	ti,y-max = /bits/ 16 <0>;
	155	ti,pressure-max = /bits/ 16 <0>;
f7d3586f	156	ti,x-plate-ohms = /bits/ 16 <400>;
d09e6bea DD	157	wakeup-source;
	158	};
	159	};
	160
47bcc8c0 FD	161	&fec1 {
	162	pinctrl-names = "default";
	163	pinctrl-0 = <&pinctrl_enet1>;
	164	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
	165	<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
	166	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	167	assigned-clock-rates = <0>, <100000000>;
	168	phy-mode = "rgmii";
	169	phy-handle = <&ethphy0>;
	170	fsl,magic-packet;
	171	status = "okay";
	172
	173	mdio {
	174	#address-cells = <1>;
	175	#size-cells = <0>;
	176
	177	ethphy0: ethernet-phy@0 {
	178	reg = <0>;
	179	};
	180
	181	ethphy1: ethernet-phy@1 {
	182	reg = <1>;
	183	};
	184	};
	185	};
	186
	187	&fec2 {
	188	pinctrl-names = "default";
	189	pinctrl-0 = <&pinctrl_enet2>;
	190	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
	191	<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
	192	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	193	assigned-clock-rates = <0>, <100000000>;
	194	phy-mode = "rgmii";
	195	phy-handle = <&ethphy1>;
	196	fsl,magic-packet;
	197	status = "okay";
	198	};
	199
5db106bc FL	200	&i2c1 {
	201	pinctrl-names = "default";
	202	pinctrl-0 = <&pinctrl_i2c1>;
	203	status = "okay";
	204
	205	pmic: pfuze3000@08 {
	206	compatible = "fsl,pfuze3000";
	207	reg = <0x08>;
	208
	209	regulators {
	210	sw1a_reg: sw1a {
	211	regulator-min-microvolt = <700000>;
	212	regulator-max-microvolt = <1475000>;
	213	regulator-boot-on;
	214	regulator-always-on;
	215	regulator-ramp-delay = <6250>;
	216	};
	217
	218	/* use sw1c_reg to align with pfuze100/pfuze200 */
	219	sw1c_reg: sw1b {
	220	regulator-min-microvolt = <700000>;
	221	regulator-max-microvolt = <1475000>;
	222	regulator-boot-on;
	223	regulator-always-on;
	224	regulator-ramp-delay = <6250>;
	225	};
	226
	227	sw2_reg: sw2 {
	228	regulator-min-microvolt = <1500000>;
	229	regulator-max-microvolt = <1850000>;
	230	regulator-boot-on;
	231	regulator-always-on;
	232	};
	233
	234	sw3a_reg: sw3 {
	235	regulator-min-microvolt = <900000>;
	236	regulator-max-microvolt = <1650000>;
	237	regulator-boot-on;
	238	regulator-always-on;
	239	};
	240
	241	swbst_reg: swbst {
	242	regulator-min-microvolt = <5000000>;
	243	regulator-max-microvolt = <5150000>;
	244	};
	245
	246	snvs_reg: vsnvs {
	247	regulator-min-microvolt = <1000000>;
	248	regulator-max-microvolt = <3000000>;
	249	regulator-boot-on;
	250	regulator-always-on;
	251	};
	252
	253	vref_reg: vrefddr {
	254	regulator-boot-on;
	255	regulator-always-on;
	256	};
	257
	258	vgen1_reg: vldo1 {
	259	regulator-min-microvolt = <1800000>;
	260	regulator-max-microvolt = <3300000>;
	261	regulator-always-on;
	262	};
	263
264	vgen2_reg: vldo2 {
265	regulator-min-microvolt = <800000>;
266	regulator-max-microvolt = <1550000>;
267	};
268
269	vgen3_reg: vccsd {
270	regulator-min-microvolt = <2850000>;
271	regulator-max-microvolt = <3300000>;
272	regulator-always-on;
273	};
274
275	vgen4_reg: v33 {
276	regulator-min-microvolt = <2850000>;
277	regulator-max-microvolt = <3300000>;
278	regulator-always-on;
279	};
280
281	vgen5_reg: vldo3 {
282	regulator-min-microvolt = <1800000>;
283	regulator-max-microvolt = <3300000>;
284	regulator-always-on;
285	};
286
287	vgen6_reg: vldo4 {
288	regulator-min-microvolt = <1800000>;
289	regulator-max-microvolt = <3300000>;
290	regulator-always-on;
291	};
292	};
293	};
294	};
295
296	&i2c2 {
297	pinctrl-names = "default";
298	pinctrl-0 = <&pinctrl_i2c2>;
299	status = "okay";
300	};
301
302	&i2c3 {
303	pinctrl-names = "default";
304	pinctrl-0 = <&pinctrl_i2c3>;
305	status = "okay";
306	};
307
308	&i2c4 {
309	pinctrl-names = "default";
310	pinctrl-0 = <&pinctrl_i2c4>;
311	status = "okay";
312
313	codec: wm8960@1a {
314	compatible = "wlf,wm8960";
315	reg = <0x1a>;
316	clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
317	clock-names = "mclk";
318	wlf,shared-lrclk;
319	};
320	};
321
41969055 DD	322	&lcdif {
	323	pinctrl-names = "default";
	324	pinctrl-0 = <&pinctrl_lcdif>;
	325	display = <&display0>;
	326	status = "okay";
	327
	328	display0: display {
	329	bits-per-pixel = <16>;
	330	bus-width = <24>;
	331
	332	display-timings {
	333	native-mode = <&timing0>;
	334
	335	timing0: timing0 {
	336	clock-frequency = <9200000>;
	337	hactive = <480>;
	338	vactive = <272>;
	339	hfront-porch = <8>;
	340	hback-porch = <4>;
	341	hsync-len = <41>;
	342	vback-porch = <2>;
	343	vfront-porch = <4>;
	344	vsync-len = <10>;
	345	hsync-active = <0>;
	346	vsync-active = <0>;
	347	de-active = <1>;
	348	pixelclk-active = <0>;
	349	};
	350	};
	351	};
	352	};
	353
34adfaa3 AS	354	&pcie {
	355	reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
	356	status = "okay";
	357	};
	358
41969055 DD	359	&pwm1 {
	360	pinctrl-names = "default";
	361	pinctrl-0 = <&pinctrl_pwm1>;
	362	status = "okay";
	363	};
	364
5db106bc FL	365	&uart1 {
	366	pinctrl-names = "default";
	367	pinctrl-0 = <&pinctrl_uart1>;
	368	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	369	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	370	status = "okay";
	371	};
	372
a81fd34d FE	373	&usbotg1 {
	374	vbus-supply = <&reg_usb_otg1_vbus>;
	375	status = "okay";
	376	};
	377
	378	&usbotg2 {
	379	vbus-supply = <&reg_usb_otg2_vbus>;
	380	dr_mode = "host";
	381	status = "okay";
	382	};
	383
5db106bc FL	384	&usdhc1 {
	385	pinctrl-names = "default";
	386	pinctrl-0 = <&pinctrl_usdhc1>;
1cd55947 DA	387	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
1cd55947 DA	388	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
26cefdd1	389	wakeup-source;
5db106bc FL	390	keep-power-in-suspend;
	391	status = "okay";
	392	};
	393
6e823e97 FE	394	&usdhc2 {
	395	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	396	pinctrl-0 = <&pinctrl_usdhc2>;
	397	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	398	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	399	wakeup-source;
	400	keep-power-in-suspend;
	401	non-removable;
	402	vmmc-supply = <&reg_brcm>;
	403	fsl,tuning-step = <2>;
	404	status = "okay";
	405	};
	406
f651d781 HC	407	&usdhc3 {
	408	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	409	pinctrl-0 = <&pinctrl_usdhc3>;
	410	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	411	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	412	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	413	assigned-clock-rates = <400000000>;
	414	bus-width = <8>;
	415	fsl,tuning-step = <2>;
	416	non-removable;
	417	status = "okay";
	418	};
	419
51fd0323 FE	420	&wdog1 {
	421	pinctrl-names = "default";
	422	pinctrl-0 = <&pinctrl_wdog>;
	423	fsl,ext-reset-output;
	424	};
	425
5db106bc FL	426	&iomuxc {
	427	pinctrl-names = "default";
	428	pinctrl-0 = <&pinctrl_hog>;
	429
	430	imx7d-sdb {
6e823e97 FE	431	pinctrl_brcm_reg: brcmreggrp {
	432	fsl,pins = <
	433	MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
	434	>;
	435	};
	436
d09e6bea DD	437	pinctrl_ecspi3: ecspi3grp {
	438	fsl,pins = <
	439	MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
	440	MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
	441	MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
	442	MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
	443	>;
	444	};
	445
47bcc8c0 FD	446	pinctrl_enet1: enet1grp {
	447	fsl,pins = <
	448	MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
	449	MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
	450	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
	451	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
	452	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
	453	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
	454	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
	455	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
	456	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
	457	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
	458	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
	459	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
	460	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
	461	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
	462	>;
	463	};
	464
	465	pinctrl_enet2: enet2grp {
	466	fsl,pins = <
	467	MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
	468	MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
	469	MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
	470	MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
	471	MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
	472	MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
	473	MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
	474	MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
	475	MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
	476	MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
	477	MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
	478	MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
	479	>;
	480	};
	481
5db106bc FL	482	pinctrl_hog: hoggrp {
	483	fsl,pins = <
	484	MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
	485	MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
	486	>;
	487	};
	488
	489	pinctrl_i2c1: i2c1grp {
	490	fsl,pins = <
	491	MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
	492	MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
	493	>;
	494	};
	495
	496	pinctrl_i2c2: i2c2grp {
	497	fsl,pins = <
	498	MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
	499	MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
	500	>;
	501	};
	502
	503	pinctrl_i2c3: i2c3grp {
	504	fsl,pins = <
	505	MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
	506	MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
	507	>;
	508	};
	509
	510	pinctrl_i2c4: i2c4grp {
	511	fsl,pins = <
	512	MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
	513	MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
	514	>;
	515	};
	516
41969055 DD	517	pinctrl_lcdif: lcdifgrp {
	518	fsl,pins = <
	519	MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
	520	MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
	521	MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
	522	MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
	523	MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
	524	MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
	525	MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
	526	MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
	527	MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
	528	MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
	529	MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
	530	MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
	531	MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
	532	MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
	533	MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
	534	MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
	535	MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
	536	MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
	537	MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
	538	MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
	539	MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
	540	MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
	541	MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
	542	MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
	543	MX7D_PAD_LCD_CLK__LCD_CLK 0x79
	544	MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
	545	MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
	546	MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
	547	MX7D_PAD_LCD_RESET__LCD_RESET 0x79
	548	>;
	549	};
	550
d09e6bea DD	551	pinctrl_tsc2046_pendown: tsc2046_pendown {
	552	fsl,pins = <
	553	MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
	554	>;
	555	};
	556
5db106bc FL	557	pinctrl_uart1: uart1grp {
	558	fsl,pins = <
	559	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
	560	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
	561	>;
	562	};
	563
	564	pinctrl_uart5: uart5grp {
	565	fsl,pins = <
	566	MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
	567	MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
	568	MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
	569	MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
	570	>;
	571	};
	572
	573	pinctrl_uart6: uart6grp {
	574	fsl,pins = <
	575	MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
	576	MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
	577	MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
	578	MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
	579	>;
	580	};
	581
	582	pinctrl_usdhc1: usdhc1grp {
	583	fsl,pins = <
	584	MX7D_PAD_SD1_CMD__SD1_CMD 0x59
	585	MX7D_PAD_SD1_CLK__SD1_CLK 0x19
	586	MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
	587	MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
	588	MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
	589	MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
	590	MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
	591	MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
	592	MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
	593	>;
	594	};
	595
	596	pinctrl_usdhc2: usdhc2grp {
	597	fsl,pins = <
	598	MX7D_PAD_SD2_CMD__SD2_CMD 0x59
	599	MX7D_PAD_SD2_CLK__SD2_CLK 0x19
	600	MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
	601	MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
	602	MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
	603	MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
5db106bc FL	604	>;
	605	};
	606
	607	pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
	608	fsl,pins = <
	609	MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
	610	MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
	611	MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
	612	MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
	613	MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
	614	MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
	615	>;
	616	};
	617
	618	pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
	619	fsl,pins = <
	620	MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
	621	MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
	622	MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
	623	MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
	624	MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
	625	MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
	626	>;
	627	};
	628
	629
	630	pinctrl_usdhc3: usdhc3grp {
	631	fsl,pins = <
	632	MX7D_PAD_SD3_CMD__SD3_CMD 0x59
	633	MX7D_PAD_SD3_CLK__SD3_CLK 0x19
	634	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
	635	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
	636	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
	637	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
	638	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
	639	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
	640	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
	641	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
	642	MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
	643	>;
	644	};
	645
	646	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
	647	fsl,pins = <
	648	MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
	649	MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
	650	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
	651	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
	652	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
	653	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
	654	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
	655	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
	656	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
	657	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
	658	MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
	659	>;
	660	};
	661
	662	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
	663	fsl,pins = <
	664	MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
	665	MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
	666	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
	667	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
668	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
669	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
670	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
671	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
672	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
673	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
674	MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
675	>;
676	};
9a20aa26 SH	677	};
9a20aa26 SH	678	};
5db106bc	679
9a20aa26 SH	680	&iomuxc_lpsr {
	681	pinctrl_wdog: wdoggrp {
	682	fsl,pins = <
37de44f2	683	MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
9a20aa26 SH	684	>;
	685	};
	686
	687	pinctrl_pwm1: pwm1grp {
	688	fsl,pins = <
213e51ca	689	MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0
9a20aa26	690	>;
184f39b5 AS	691
	692	pinctrl_spi4: spi4grp {
	693	fsl,pins = <
	694	MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
	695	MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
	696	MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
	697	>;
	698	};
5db106bc FL	699	};
5db106bc FL	700	};