[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx7s-warp.dts

/*
 * Copyright (C) 2016 NXP Semiconductors.
 * Author: Fabio Estevam <fabio.estevam@nxp.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include "imx7s.dtsi"

/ {
	model = "Warp i.MX7 Board";
	compatible = "warp,imx7s-warp", "fsl,imx7s";

	memory@80000000 {
		reg = <0x80000000 0x20000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&pinctrl_gpio>;
		autorepeat;

		back {
			label = "Back";
			gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_BACK>;
			wakeup-source;
		};
	};

	reg_brcm: regulator-brcm {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_brcm_reg>;
		regulator-name = "brcm_reg";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <200000>;
	};

	reg_bt: regulator-bt {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_bt_reg>;
		enable-active-high;
		gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
		regulator-name = "bt_reg";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "imx7-sgtl5000";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,cpu {
			sound-dai = <&sai1>;
		};

		dailink_master: simple-audio-card,codec {
			sound-dai = <&codec>;
			clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
		};
	};
};

&clks {
	assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
	assigned-clock-rates = <884736000>;
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic: pfuze3000@8 {
		compatible = "fsl,pfuze3000";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1a {
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1475000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			/* use sw1c_reg to align with pfuze100/pfuze200 */
			sw1c_reg: sw1b {
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1475000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3a_reg: sw3 {
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1650000>;
				regulator-boot-on;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen1_reg: vldo1 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen2_reg: vldo2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen3_reg: vccsd {
				regulator-min-microvolt = <2850000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen4_reg: v33 {
				regulator-min-microvolt = <2850000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen5_reg: vldo3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen6_reg: vldo4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	codec: sgtl5000@a {
		#sound-dai-cells = <0>;
		reg = <0x0a>;
		compatible = "fsl,sgtl5000";
		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sai1_mclk>;
		VDDA-supply = <&vgen4_reg>;
		VDDIO-supply = <&vgen4_reg>;
		VDDD-supply = <&vgen2_reg>;
	};

	mpl3115@60 {
		compatible = "fsl,mpl3115";
		reg = <0x60>;
	};
};

&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
			  <&clks IMX7D_SAI1_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
	assigned-clock-rates = <0>, <36864000>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	status = "okay";
};

&uart3  {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	uart-has-rtscts;
	status = "okay";
};

&uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	fsl,dte-mode;
	status = "okay";
};

&usbotg1 {
	dr_mode = "peripheral";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <4>;
	keep-power-in-suspend;
	no-1-8-v;
	non-removable;
	vmmc-supply = <&reg_brcm>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	assigned-clock-rates = <400000000>;
	bus-width = <8>;
	no-1-8-v;
	fsl,tuning-step = <2>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_brcm_reg: brcmreggrp {
		fsl,pins = <
			MX7D_PAD_SD2_WP__GPIO5_IO10	0x14 /* WL_REG_ON */
		>;
	};

	pinctrl_bt_reg: btreggrp {
		fsl,pins = <
			MX7D_PAD_SD2_DATA3__GPIO5_IO17	0x14 /* BT_REG_ON */
		>;
	};

	pinctrl_gpio: gpiogrp {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1	0x14
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX7D_PAD_I2C1_SDA__I2C1_SDA		0x4000007f
			MX7D_PAD_I2C1_SCL__I2C1_SCL		0x4000007f
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX7D_PAD_I2C2_SDA__I2C2_SDA	0x4000007f
			MX7D_PAD_I2C2_SCL__I2C2_SCL	0x4000007f
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX7D_PAD_I2C4_SCL__I2C4_SCL	0x4000007f
			MX7D_PAD_I2C4_SDA__I2C4_SDA	0x4000007f
		>;
	};

	pinctrl_sai1: sai1grp {
		fsl,pins = <
			MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0	0x1f
			MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK	0x1f
			MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x1f
			MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0	0x30
		>;
	};

	pinctrl_sai1_mclk: sai1mclkgrp {
		fsl,pins = <
			MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
			MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x79
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x79
			MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x79
			MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS	0x79
			MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS	0x79
		>;
	};

	pinctrl_uart6: uart6grp {
		fsl,pins = <
			MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX	0x79
			MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX	0x79
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX7D_PAD_SD1_CMD__SD1_CMD	0x59
			MX7D_PAD_SD1_CLK__SD1_CLK	0x19
			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x59
			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x59
			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x59
			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x59
			MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x19
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
		fsl,pins = <
			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x1a
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
		fsl,pins = <
			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x1b
		>;
	};
};

&iomuxc_lpsr {
	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x74
		>;
	};
};
Commit	Line	Data
ffebc8c0 FE	1	/*
	2	* Copyright (C) 2016 NXP Semiconductors.
	3	* Author: Fabio Estevam <fabio.estevam@nxp.com>
	4	*
	5	* This file is dual-licensed: you can use it either under the terms
	6	* of the GPL or the X11 license, at your option. Note that this dual
	7	* licensing only applies to this file, and not this project as a
	8	* whole.
	9	*
	10	* a) This file is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of the
	13	* License, or (at your option) any later version.
	14	*
	15	* This file is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* Or, alternatively,
	21	*
	22	* b) Permission is hereby granted, free of charge, to any person
	23	* obtaining a copy of this software and associated documentation
	24	* files (the "Software"), to deal in the Software without
	25	* restriction, including without limitation the rights to use,
	26	* copy, modify, merge, publish, distribute, sublicense, and/or
	27	* sell copies of the Software, and to permit persons to whom the
	28	* Software is furnished to do so, subject to the following
	29	* conditions:
	30	*
	31	* The above copyright notice and this permission notice shall be
	32	* included in all copies or substantial portions of the Software.
	33	*
	34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	35	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	36	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	37	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	38	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	39	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	40	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	41	* OTHER DEALINGS IN THE SOFTWARE.
	42	*/
	43
	44	/dts-v1/;
	45
	46	#include <dt-bindings/input/input.h>
	47	#include "imx7s.dtsi"
	48
	49	/ {
	50	model = "Warp i.MX7 Board";
	51	compatible = "warp,imx7s-warp", "fsl,imx7s";
	52
ad00e080	53	memory@80000000 {
ffebc8c0 FE	54	reg = <0x80000000 0x20000000>;
ffebc8c0 FE	55	};
9a3bb943	56
d142a207 VM	57	gpio-keys {
	58	compatible = "gpio-keys";
	59	pinctrl-0 = <&pinctrl_gpio>;
	60	autorepeat;
	61
	62	back {
	63	label = "Back";
	64	gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
	65	linux,code = <KEY_BACK>;
	66	wakeup-source;
	67	};
	68	};
	69
44e645fa FE	70	reg_brcm: regulator-brcm {
	71	compatible = "regulator-fixed";
	72	enable-active-high;
	73	gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
	74	pinctrl-names = "default";
	75	pinctrl-0 = <&pinctrl_brcm_reg>;
	76	regulator-name = "brcm_reg";
	77	regulator-min-microvolt = <3300000>;
	78	regulator-max-microvolt = <3300000>;
	79	startup-delay-us = <200000>;
	80	};
	81
9fa7a2a4 VM	82	reg_bt: regulator-bt {
	83	compatible = "regulator-fixed";
	84	pinctrl-names = "default";
	85	pinctrl-0 = <&pinctrl_bt_reg>;
	86	enable-active-high;
	87	gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
	88	regulator-name = "bt_reg";
	89	regulator-min-microvolt = <3300000>;
	90	regulator-max-microvolt = <3300000>;
	91	regulator-always-on;
	92	};
	93
9a3bb943 FE	94	sound {
	95	compatible = "simple-audio-card";
	96	simple-audio-card,name = "imx7-sgtl5000";
	97	simple-audio-card,format = "i2s";
	98	simple-audio-card,bitclock-master = <&dailink_master>;
	99	simple-audio-card,frame-master = <&dailink_master>;
	100	simple-audio-card,cpu {
	101	sound-dai = <&sai1>;
	102	};
	103
	104	dailink_master: simple-audio-card,codec {
	105	sound-dai = <&codec>;
	106	clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
	107	};
	108	};
	109	};
	110
	111	&clks {
	112	assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
	113	assigned-clock-rates = <884736000>;
ffebc8c0 FE	114	};
ffebc8c0 FE	115
ffebc8c0 FE	116	&i2c1 {
	117	pinctrl-names = "default";
	118	pinctrl-0 = <&pinctrl_i2c1>;
	119	status = "okay";
	120
8dccafaa	121	pmic: pfuze3000@8 {
ffebc8c0 FE	122	compatible = "fsl,pfuze3000";
	123	reg = <0x08>;
	124
	125	regulators {
	126	sw1a_reg: sw1a {
	127	regulator-min-microvolt = <700000>;
	128	regulator-max-microvolt = <1475000>;
	129	regulator-boot-on;
	130	regulator-always-on;
	131	regulator-ramp-delay = <6250>;
	132	};
	133
	134	/* use sw1c_reg to align with pfuze100/pfuze200 */
	135	sw1c_reg: sw1b {
	136	regulator-min-microvolt = <700000>;
	137	regulator-max-microvolt = <1475000>;
	138	regulator-boot-on;
	139	regulator-always-on;
	140	regulator-ramp-delay = <6250>;
	141	};
	142
	143	sw2_reg: sw2 {
	144	regulator-min-microvolt = <1500000>;
	145	regulator-max-microvolt = <1850000>;
	146	regulator-boot-on;
	147	regulator-always-on;
	148	};
	149
	150	sw3a_reg: sw3 {
	151	regulator-min-microvolt = <900000>;
	152	regulator-max-microvolt = <1650000>;
	153	regulator-boot-on;
	154	regulator-always-on;
	155	};
	156
	157	swbst_reg: swbst {
	158	regulator-min-microvolt = <5000000>;
	159	regulator-max-microvolt = <5150000>;
	160	};
	161
	162	snvs_reg: vsnvs {
	163	regulator-min-microvolt = <1000000>;
	164	regulator-max-microvolt = <3000000>;
	165	regulator-boot-on;
	166	regulator-always-on;
	167	};
	168
	169	vref_reg: vrefddr {
	170	regulator-boot-on;
	171	regulator-always-on;
	172	};
	173
	174	vgen1_reg: vldo1 {
	175	regulator-min-microvolt = <1800000>;
	176	regulator-max-microvolt = <3300000>;
	177	regulator-always-on;
	178	};
	179
	180	vgen2_reg: vldo2 {
	181	regulator-min-microvolt = <800000>;
	182	regulator-max-microvolt = <1550000>;
	183	};
	184
	185	vgen3_reg: vccsd {
186	regulator-min-microvolt = <2850000>;
187	regulator-max-microvolt = <3300000>;
188	regulator-always-on;
189	};
190
191	vgen4_reg: v33 {
192	regulator-min-microvolt = <2850000>;
193	regulator-max-microvolt = <3300000>;
194	regulator-always-on;
195	};
196
197	vgen5_reg: vldo3 {
198	regulator-min-microvolt = <1800000>;
199	regulator-max-microvolt = <3300000>;
200	regulator-always-on;
201	};
202
203	vgen6_reg: vldo4 {
204	regulator-min-microvolt = <1800000>;
205	regulator-max-microvolt = <3300000>;
206	regulator-always-on;
207	};
208	};
209	};
210	};
211
c2bf9589 VM	212	&i2c2 {
	213	clock-frequency = <100000>;
	214	pinctrl-names = "default";
	215	pinctrl-0 = <&pinctrl_i2c2>;
	216	status = "okay";
	217	};
	218
171befef BL	219	&i2c4 {
	220	clock-frequency = <100000>;
	221	pinctrl-names = "default";
	222	pinctrl-0 = <&pinctrl_i2c4>;
	223	status = "okay";
	224
8dccafaa	225	codec: sgtl5000@a {
9a3bb943 FE	226	#sound-dai-cells = <0>;
	227	reg = <0x0a>;
	228	compatible = "fsl,sgtl5000";
	229	clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
b9dea861 FE	230	pinctrl-names = "default";
b9dea861 FE	231	pinctrl-0 = <&pinctrl_sai1_mclk>;
9a3bb943 FE	232	VDDA-supply = <&vgen4_reg>;
	233	VDDIO-supply = <&vgen4_reg>;
	234	VDDD-supply = <&vgen2_reg>;
	235	};
	236
171befef BL	237	mpl3115@60 {
	238	compatible = "fsl,mpl3115";
	239	reg = <0x60>;
	240	};
	241	};
	242
9a3bb943 FE	243	&sai1 {
	244	pinctrl-names = "default";
	245	pinctrl-0 = <&pinctrl_sai1>;
	246	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
	247	<&clks IMX7D_SAI1_ROOT_CLK>;
	248	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
	249	assigned-clock-rates = <0>, <36864000>;
	250	status = "okay";
	251	};
	252
ffebc8c0 FE	253	&uart1 {
	254	pinctrl-names = "default";
	255	pinctrl-0 = <&pinctrl_uart1>;
	256	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	257	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	258	status = "okay";
	259	};
	260
9fa7a2a4 VM	261	&uart3 {
	262	pinctrl-names = "default";
	263	pinctrl-0 = <&pinctrl_uart3>;
	264	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
	265	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	266	uart-has-rtscts;
	267	status = "okay";
	268	};
	269
9acb15e1 RH	270	&uart6 {
	271	pinctrl-names = "default";
	272	pinctrl-0 = <&pinctrl_uart6>;
	273	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
	274	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	275	fsl,dte-mode;
	276	status = "okay";
	277	};
	278
ffebc8c0 FE	279	&usbotg1 {
	280	dr_mode = "peripheral";
	281	status = "okay";
	282	};
	283
44e645fa FE	284	&usdhc1 {
	285	pinctrl-names = "default";
	286	pinctrl-0 = <&pinctrl_usdhc1>;
	287	bus-width = <4>;
	288	keep-power-in-suspend;
	289	no-1-8-v;
	290	non-removable;
	291	vmmc-supply = <&reg_brcm>;
	292	status = "okay";
	293	};
	294
ffebc8c0 FE	295	&usdhc3 {
	296	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	297	pinctrl-0 = <&pinctrl_usdhc3>;
	298	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	299	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	300	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	301	assigned-clock-rates = <400000000>;
	302	bus-width = <8>;
60490d0a	303	no-1-8-v;
ffebc8c0 FE	304	fsl,tuning-step = <2>;
	305	non-removable;
	306	status = "okay";
	307	};
	308
a7311c0c FE	309	&wdog1 {
	310	pinctrl-names = "default";
	311	pinctrl-0 = <&pinctrl_wdog>;
	312	fsl,ext-reset-output;
	313	status = "okay";
	314	};
	315
ffebc8c0	316	&iomuxc {
44e645fa FE	317	pinctrl_brcm_reg: brcmreggrp {
	318	fsl,pins = <
	319	MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
	320	>;
	321	};
	322
9fa7a2a4 VM	323	pinctrl_bt_reg: btreggrp {
	324	fsl,pins = <
	325	MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
	326	>;
	327	};
	328
d142a207 VM	329	pinctrl_gpio: gpiogrp {
	330	fsl,pins = <
	331	MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
	332	>;
	333	};
	334
ffebc8c0 FE	335	pinctrl_i2c1: i2c1grp {
	336	fsl,pins = <
	337	MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
	338	MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
	339	>;
	340	};
	341
c2bf9589 VM	342	pinctrl_i2c2: i2c2grp {
	343	fsl,pins = <
	344	MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
	345	MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
	346	>;
	347	};
	348
171befef BL	349	pinctrl_i2c4: i2c4grp {
	350	fsl,pins = <
	351	MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
	352	MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
	353	>;
	354	};
	355
9a3bb943 FE	356	pinctrl_sai1: sai1grp {
	357	fsl,pins = <
	358	MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
	359	MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
	360	MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
	361	MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
b9dea861 FE	362	>;
	363	};
	364
	365	pinctrl_sai1_mclk: sai1mclkgrp {
	366	fsl,pins = <
	367	MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
9a3bb943 FE	368	>;
	369	};
	370
ffebc8c0 FE	371	pinctrl_uart1: uart1grp {
	372	fsl,pins = <
	373	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
	374	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
	375	>;
	376	};
	377
9fa7a2a4 VM	378	pinctrl_uart3: uart3grp {
	379	fsl,pins = <
	380	MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
	381	MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
	382	MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
	383	MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
	384	>;
	385	};
	386
9acb15e1 RH	387	pinctrl_uart6: uart6grp {
	388	fsl,pins = <
	389	MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79
	390	MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79
	391	>;
	392	};
	393
44e645fa FE	394	pinctrl_usdhc1: usdhc1grp {
	395	fsl,pins = <
	396	MX7D_PAD_SD1_CMD__SD1_CMD 0x59
	397	MX7D_PAD_SD1_CLK__SD1_CLK 0x19
	398	MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
	399	MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
	400	MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
	401	MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
	402	MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
	403	>;
	404	};
	405
ffebc8c0 FE	406	pinctrl_usdhc3: usdhc3grp {
	407	fsl,pins = <
	408	MX7D_PAD_SD3_CMD__SD3_CMD 0x59
	409	MX7D_PAD_SD3_CLK__SD3_CLK 0x19
	410	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
	411	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
	412	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
	413	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
	414	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
	415	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
	416	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
	417	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
	418	MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
	419	>;
	420	};
	421
	422	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
	423	fsl,pins = <
	424	MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
	425	MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
	426	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
	427	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
	428	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
	429	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
	430	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
	431	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
	432	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
	433	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
	434	MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
	435	>;
	436	};
	437
	438	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
	439	fsl,pins = <
	440	MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
	441	MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
	442	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
	443	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
	444	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
	445	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
	446	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
	447	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
	448	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
	449	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
	450	MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
	451	>;
	452	};
1d4a5943	453	};
a7311c0c	454
1d4a5943	455	&iomuxc_lpsr {
a7311c0c FE	456	pinctrl_wdog: wdoggrp {
a7311c0c FE	457	fsl,pins = <
37de44f2	458	MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
a7311c0c FE	459	>;
a7311c0c FE	460	};
ffebc8c0	461	};