[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx7s-warp.dts

/*
 * Copyright (C) 2016 NXP Semiconductors.
 * Author: Fabio Estevam <fabio.estevam@nxp.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include "imx7s.dtsi"

/ {
	model = "Warp i.MX7 Board";
	compatible = "warp,imx7s-warp", "fsl,imx7s";

	memory {
		reg = <0x80000000 0x20000000>;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "imx7-sgtl5000";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,cpu {
			sound-dai = <&sai1>;
		};

		dailink_master: simple-audio-card,codec {
			sound-dai = <&codec>;
			clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
		};
	};
};

&clks {
	assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
	assigned-clock-rates = <884736000>;
};

&cpu0 {
	arm-supply = <&sw1a_reg>;
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic: pfuze3000@08 {
		compatible = "fsl,pfuze3000";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1a {
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1475000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			/* use sw1c_reg to align with pfuze100/pfuze200 */
			sw1c_reg: sw1b {
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1475000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <1850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3a_reg: sw3 {
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1650000>;
				regulator-boot-on;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen1_reg: vldo1 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen2_reg: vldo2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen3_reg: vccsd {
				regulator-min-microvolt = <2850000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen4_reg: v33 {
				regulator-min-microvolt = <2850000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen5_reg: vldo3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen6_reg: vldo4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};
};

&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	codec: sgtl5000@0a {
		#sound-dai-cells = <0>;
		reg = <0x0a>;
		compatible = "fsl,sgtl5000";
		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
		VDDA-supply = <&vgen4_reg>;
		VDDIO-supply = <&vgen4_reg>;
		VDDD-supply = <&vgen2_reg>;
	};

	mpl3115@60 {
		compatible = "fsl,mpl3115";
		reg = <0x60>;
	};
};

&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
			  <&clks IMX7D_SAI1_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
	assigned-clock-rates = <0>, <36864000>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "peripheral";
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	assigned-clock-rates = <400000000>;
	bus-width = <8>;
	fsl,tuning-step = <2>;
	non-removable;
	status = "okay";
};

&iomuxc {
	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX7D_PAD_I2C1_SDA__I2C1_SDA		0x4000007f
			MX7D_PAD_I2C1_SCL__I2C1_SCL		0x4000007f
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX7D_PAD_I2C4_SCL__I2C4_SCL	0x4000007f
			MX7D_PAD_I2C4_SDA__I2C4_SDA	0x4000007f
		>;
	};

	pinctrl_sai1: sai1grp {
		fsl,pins = <
			MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0	0x1f
			MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK	0x1f
			MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x1f
			MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0	0x30
			MX7D_PAD_SAI1_MCLK__SAI1_MCLK		0x1f
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
			MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x79
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x19
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
		fsl,pins = <
			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x1a
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
		fsl,pins = <
			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x1b
		>;
	};
};
Commit	Line	Data
ffebc8c0 FE	1	/*
	2	* Copyright (C) 2016 NXP Semiconductors.
	3	* Author: Fabio Estevam <fabio.estevam@nxp.com>
	4	*
	5	* This file is dual-licensed: you can use it either under the terms
	6	* of the GPL or the X11 license, at your option. Note that this dual
	7	* licensing only applies to this file, and not this project as a
	8	* whole.
	9	*
	10	* a) This file is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of the
	13	* License, or (at your option) any later version.
	14	*
	15	* This file is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* Or, alternatively,
	21	*
	22	* b) Permission is hereby granted, free of charge, to any person
	23	* obtaining a copy of this software and associated documentation
	24	* files (the "Software"), to deal in the Software without
	25	* restriction, including without limitation the rights to use,
	26	* copy, modify, merge, publish, distribute, sublicense, and/or
	27	* sell copies of the Software, and to permit persons to whom the
	28	* Software is furnished to do so, subject to the following
	29	* conditions:
	30	*
	31	* The above copyright notice and this permission notice shall be
	32	* included in all copies or substantial portions of the Software.
	33	*
	34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	35	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	36	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	37	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	38	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	39	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	40	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	41	* OTHER DEALINGS IN THE SOFTWARE.
	42	*/
	43
	44	/dts-v1/;
	45
	46	#include <dt-bindings/input/input.h>
	47	#include "imx7s.dtsi"
	48
	49	/ {
	50	model = "Warp i.MX7 Board";
	51	compatible = "warp,imx7s-warp", "fsl,imx7s";
	52
	53	memory {
	54	reg = <0x80000000 0x20000000>;
	55	};
9a3bb943 FE	56
	57	sound {
	58	compatible = "simple-audio-card";
	59	simple-audio-card,name = "imx7-sgtl5000";
	60	simple-audio-card,format = "i2s";
	61	simple-audio-card,bitclock-master = <&dailink_master>;
	62	simple-audio-card,frame-master = <&dailink_master>;
	63	simple-audio-card,cpu {
	64	sound-dai = <&sai1>;
	65	};
	66
	67	dailink_master: simple-audio-card,codec {
	68	sound-dai = <&codec>;
	69	clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
	70	};
	71	};
	72	};
	73
	74	&clks {
	75	assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
	76	assigned-clock-rates = <884736000>;
ffebc8c0 FE	77	};
	78
	79	&cpu0 {
	80	arm-supply = <&sw1a_reg>;
	81	};
	82
	83	&i2c1 {
	84	pinctrl-names = "default";
	85	pinctrl-0 = <&pinctrl_i2c1>;
	86	status = "okay";
	87
	88	pmic: pfuze3000@08 {
	89	compatible = "fsl,pfuze3000";
	90	reg = <0x08>;
	91
	92	regulators {
	93	sw1a_reg: sw1a {
	94	regulator-min-microvolt = <700000>;
	95	regulator-max-microvolt = <1475000>;
	96	regulator-boot-on;
	97	regulator-always-on;
	98	regulator-ramp-delay = <6250>;
	99	};
	100
	101	/* use sw1c_reg to align with pfuze100/pfuze200 */
	102	sw1c_reg: sw1b {
	103	regulator-min-microvolt = <700000>;
	104	regulator-max-microvolt = <1475000>;
	105	regulator-boot-on;
	106	regulator-always-on;
	107	regulator-ramp-delay = <6250>;
	108	};
	109
	110	sw2_reg: sw2 {
	111	regulator-min-microvolt = <1500000>;
	112	regulator-max-microvolt = <1850000>;
	113	regulator-boot-on;
	114	regulator-always-on;
	115	};
	116
	117	sw3a_reg: sw3 {
	118	regulator-min-microvolt = <900000>;
	119	regulator-max-microvolt = <1650000>;
	120	regulator-boot-on;
	121	regulator-always-on;
	122	};
	123
	124	swbst_reg: swbst {
	125	regulator-min-microvolt = <5000000>;
	126	regulator-max-microvolt = <5150000>;
	127	};
	128
	129	snvs_reg: vsnvs {
	130	regulator-min-microvolt = <1000000>;
	131	regulator-max-microvolt = <3000000>;
	132	regulator-boot-on;
	133	regulator-always-on;
	134	};
	135
	136	vref_reg: vrefddr {
	137	regulator-boot-on;
	138	regulator-always-on;
	139	};
	140
141	vgen1_reg: vldo1 {
142	regulator-min-microvolt = <1800000>;
143	regulator-max-microvolt = <3300000>;
144	regulator-always-on;
145	};
146
147	vgen2_reg: vldo2 {
148	regulator-min-microvolt = <800000>;
149	regulator-max-microvolt = <1550000>;
150	};
151
152	vgen3_reg: vccsd {
153	regulator-min-microvolt = <2850000>;
154	regulator-max-microvolt = <3300000>;
155	regulator-always-on;
156	};
157
158	vgen4_reg: v33 {
159	regulator-min-microvolt = <2850000>;
160	regulator-max-microvolt = <3300000>;
161	regulator-always-on;
162	};
163
164	vgen5_reg: vldo3 {
165	regulator-min-microvolt = <1800000>;
166	regulator-max-microvolt = <3300000>;
167	regulator-always-on;
168	};
169
170	vgen6_reg: vldo4 {
171	regulator-min-microvolt = <1800000>;
172	regulator-max-microvolt = <3300000>;
173	regulator-always-on;
174	};
175	};
176	};
177	};
178
171befef BL	179	&i2c4 {
	180	clock-frequency = <100000>;
	181	pinctrl-names = "default";
	182	pinctrl-0 = <&pinctrl_i2c4>;
	183	status = "okay";
	184
9a3bb943 FE	185	codec: sgtl5000@0a {
	186	#sound-dai-cells = <0>;
	187	reg = <0x0a>;
	188	compatible = "fsl,sgtl5000";
	189	clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
	190	VDDA-supply = <&vgen4_reg>;
	191	VDDIO-supply = <&vgen4_reg>;
	192	VDDD-supply = <&vgen2_reg>;
	193	};
	194
171befef BL	195	mpl3115@60 {
	196	compatible = "fsl,mpl3115";
	197	reg = <0x60>;
	198	};
	199	};
	200
9a3bb943 FE	201	&sai1 {
	202	pinctrl-names = "default";
	203	pinctrl-0 = <&pinctrl_sai1>;
	204	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
	205	<&clks IMX7D_SAI1_ROOT_CLK>;
	206	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
	207	assigned-clock-rates = <0>, <36864000>;
	208	status = "okay";
	209	};
	210
ffebc8c0 FE	211	&uart1 {
	212	pinctrl-names = "default";
	213	pinctrl-0 = <&pinctrl_uart1>;
	214	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	215	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
	216	status = "okay";
	217	};
	218
	219	&usbotg1 {
	220	dr_mode = "peripheral";
	221	status = "okay";
	222	};
	223
	224	&usdhc3 {
	225	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	226	pinctrl-0 = <&pinctrl_usdhc3>;
	227	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	228	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	229	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	230	assigned-clock-rates = <400000000>;
	231	bus-width = <8>;
	232	fsl,tuning-step = <2>;
	233	non-removable;
	234	status = "okay";
	235	};
	236
	237	&iomuxc {
	238	pinctrl_i2c1: i2c1grp {
	239	fsl,pins = <
	240	MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
	241	MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
	242	>;
	243	};
	244
171befef BL	245	pinctrl_i2c4: i2c4grp {
	246	fsl,pins = <
	247	MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
	248	MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
	249	>;
	250	};
	251
9a3bb943 FE	252	pinctrl_sai1: sai1grp {
	253	fsl,pins = <
	254	MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
	255	MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
	256	MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
	257	MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
	258	MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
	259	>;
	260	};
	261
ffebc8c0 FE	262	pinctrl_uart1: uart1grp {
	263	fsl,pins = <
	264	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
	265	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
	266	>;
	267	};
	268
	269	pinctrl_usdhc3: usdhc3grp {
	270	fsl,pins = <
	271	MX7D_PAD_SD3_CMD__SD3_CMD 0x59
	272	MX7D_PAD_SD3_CLK__SD3_CLK 0x19
	273	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
	274	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
	275	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
	276	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
	277	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
	278	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
	279	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
	280	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
	281	MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
	282	>;
	283	};
	284
	285	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
	286	fsl,pins = <
	287	MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
	288	MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
	289	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
	290	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
	291	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
	292	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
	293	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
	294	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
	295	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
	296	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
	297	MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
	298	>;
	299	};
	300
	301	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
	302	fsl,pins = <
	303	MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
	304	MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
	305	MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
	306	MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
	307	MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
	308	MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
	309	MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
	310	MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
	311	MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
	312	MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
	313	MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
	314	>;
	315	};
	316	};