[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx7ulp.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2018 NXP
 *   Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx7ulp-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "imx7ulp-pinfunc.h"

/ {
	interrupt-parent = <&intc>;

	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		gpio0 = &gpio_ptc;
		gpio1 = &gpio_ptd;
		gpio2 = &gpio_pte;
		gpio3 = &gpio_ptf;
		i2c0 = &lpi2c6;
		i2c1 = &lpi2c7;
		mmc0 = &usdhc0;
		mmc1 = &usdhc1;
		serial0 = &lpuart4;
		serial1 = &lpuart5;
		serial2 = &lpuart6;
		serial3 = &lpuart7;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};
	};

	intc: interrupt-controller@40021000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x40021000 0x1000>,
		      <0x40022000 0x1000>;
	};

	rosc: clock-rosc {
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "rosc";
		#clock-cells = <0>;
	};

	sosc: clock-sosc {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "sosc";
		#clock-cells = <0>;
	};

	sirc: clock-sirc {
		compatible = "fixed-clock";
		clock-frequency = <16000000>;
		clock-output-names = "sirc";
		#clock-cells = <0>;
	};

	firc: clock-firc {
		compatible = "fixed-clock";
		clock-frequency = <48000000>;
		clock-output-names = "firc";
		#clock-cells = <0>;
	};

	upll: clock-upll {
		compatible = "fixed-clock";
		clock-frequency = <480000000>;
		clock-output-names = "upll";
		#clock-cells = <0>;
	};

	mpll: clock-mpll {
		compatible = "fixed-clock";
		clock-frequency = <480000000>;
		clock-output-names = "mpll";
		#clock-cells = <0>;
	};

	ahbbridge0: bus@40000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x40000000 0x800000>;
		ranges;

		lpuart4: serial@402d0000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x402d0000 0x1000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
			clock-names = "ipg";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
			assigned-clock-rates = <24000000>;
			status = "disabled";
		};

		lpuart5: serial@402e0000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x402e0000 0x1000>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
			clock-names = "ipg";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		tpm5: tpm@40260000 {
			compatible = "fsl,imx7ulp-tpm";
			reg = <0x40260000 0x1000>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
			clock-names = "ipg", "per";
		};

		usdhc0: mmc@40370000 {
			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
			reg = <0x40370000 0x10000>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&pcc2 IMX7ULP_CLK_USDHC0>;
			clock-names ="ipg", "ahb", "per";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
			bus-width = <4>;
			fsl,tuning-start-tap = <20>;
			fsl,tuning-step= <2>;
			status = "disabled";
		};

		usdhc1: mmc@40380000 {
			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
			reg = <0x40380000 0x10000>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&pcc2 IMX7ULP_CLK_USDHC1>;
			clock-names ="ipg", "ahb", "per";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
			bus-width = <4>;
			fsl,tuning-start-tap = <20>;
			fsl,tuning-step= <2>;
			status = "disabled";
		};

		scg1: clock-controller@403e0000 {
			compatible = "fsl,imx7ulp-scg1";
			reg = <0x403e0000 0x10000>;
			clocks = <&rosc>, <&sosc>, <&sirc>,
				 <&firc>, <&upll>, <&mpll>;
			clock-names = "rosc", "sosc", "sirc",
				      "firc", "upll", "mpll";
			#clock-cells = <1>;
		};

		pcc2: clock-controller@403f0000 {
			compatible = "fsl,imx7ulp-pcc2";
			reg = <0x403f0000 0x10000>;
			#clock-cells = <1>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&scg1 IMX7ULP_CLK_DDR_DIV>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
				 <&scg1 IMX7ULP_CLK_UPLL>,
				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_ROSC>,
				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
			clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
				      "apll_pfd2", "apll_pfd1", "apll_pfd0",
				      "upll", "sosc_bus_clk", "mpll",
				      "firc_bus_clk", "rosc", "spll_bus_clk";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
		};

		smc1: clock-controller@40410000 {
			compatible = "fsl,imx7ulp-smc1";
			reg = <0x40410000 0x1000>;
			#clock-cells = <1>;
			clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
				 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
			clock-names = "divcore", "hsrun_divcore";
		};

		pcc3: clock-controller@40b30000 {
			compatible = "fsl,imx7ulp-pcc3";
			reg = <0x40b30000 0x10000>;
			#clock-cells = <1>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&scg1 IMX7ULP_CLK_DDR_DIV>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
				 <&scg1 IMX7ULP_CLK_UPLL>,
				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_ROSC>,
				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
			clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
				      "apll_pfd2", "apll_pfd1", "apll_pfd0",
				      "upll", "sosc_bus_clk", "mpll",
				      "firc_bus_clk", "rosc", "spll_bus_clk";
		};
	};

	ahbbridge1: bus@40800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x40800000 0x800000>;
		ranges;

		lpi2c6: i2c@40a40000 {
			compatible = "fsl,imx7ulp-lpi2c";
			reg = <0x40a40000 0x10000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
			clock-names = "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		lpi2c7: i2c@40a50000 {
			compatible = "fsl,imx7ulp-lpi2c";
			reg = <0x40a50000 0x10000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
			clock-names = "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		lpuart6: serial@40a60000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x40a60000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
			clock-names = "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		lpuart7: serial@40a70000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x40a70000 0x1000>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
			clock-names = "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		iomuxc1: pinctrl@40ac0000 {
			compatible = "fsl,imx7ulp-iomuxc1";
			reg = <0x40ac0000 0x1000>;
		};

		gpio_ptc: gpio@40ae0000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLC>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 0 32>;
		};

		gpio_ptd: gpio@40af0000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40af0000 0x1000 0x400f0040 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLD>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 32 32>;
		};

		gpio_pte: gpio@40b00000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40b00000 0x1000 0x400f0080 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLE>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 64 32>;
		};

		gpio_ptf: gpio@40b10000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLF>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 96 32>;
		};
	};

	m4aips1: bus@41080000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x41080000 0x80000>;
		ranges;

		sim: sim@410a3000 {
			compatible = "fsl,imx7ulp-sim", "syscon";
			reg = <0x410a3000 0x1000>;
		};
	};
};
Commit	Line	Data
20434dc9 D	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2016 Freescale Semiconductor, Inc.
	4	* Copyright 2017-2018 NXP
	5	* Dong Aisheng <aisheng.dong@nxp.com>
	6	*/
	7
	8	#include <dt-bindings/clock/imx7ulp-clock.h>
	9	#include <dt-bindings/gpio/gpio.h>
	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
	11
	12	#include "imx7ulp-pinfunc.h"
	13
	14	/ {
	15	interrupt-parent = <&intc>;
	16
	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
	20	aliases {
	21	gpio0 = &gpio_ptc;
	22	gpio1 = &gpio_ptd;
	23	gpio2 = &gpio_pte;
	24	gpio3 = &gpio_ptf;
	25	i2c0 = &lpi2c6;
	26	i2c1 = &lpi2c7;
	27	mmc0 = &usdhc0;
	28	mmc1 = &usdhc1;
	29	serial0 = &lpuart4;
	30	serial1 = &lpuart5;
	31	serial2 = &lpuart6;
	32	serial3 = &lpuart7;
	33	};
	34
	35	cpus {
	36	#address-cells = <1>;
	37	#size-cells = <0>;
	38
	39	cpu0: cpu@0 {
	40	compatible = "arm,cortex-a7";
	41	device_type = "cpu";
	42	reg = <0>;
	43	};
	44	};
	45
	46	intc: interrupt-controller@40021000 {
	47	compatible = "arm,cortex-a7-gic";
	48	#interrupt-cells = <3>;
	49	interrupt-controller;
	50	reg = <0x40021000 0x1000>,
	51	<0x40022000 0x1000>;
	52	};
	53
	54	rosc: clock-rosc {
	55	compatible = "fixed-clock";
	56	clock-frequency = <32768>;
	57	clock-output-names = "rosc";
	58	#clock-cells = <0>;
	59	};
	60
	61	sosc: clock-sosc {
	62	compatible = "fixed-clock";
	63	clock-frequency = <24000000>;
	64	clock-output-names = "sosc";
65	#clock-cells = <0>;
66	};
67
68	sirc: clock-sirc {
69	compatible = "fixed-clock";
70	clock-frequency = <16000000>;
71	clock-output-names = "sirc";
72	#clock-cells = <0>;
73	};
74
75	firc: clock-firc {
76	compatible = "fixed-clock";
77	clock-frequency = <48000000>;
78	clock-output-names = "firc";
79	#clock-cells = <0>;
80	};
81
82	upll: clock-upll {
83	compatible = "fixed-clock";
84	clock-frequency = <480000000>;
85	clock-output-names = "upll";
86	#clock-cells = <0>;
87	};
88
89	mpll: clock-mpll {
90	compatible = "fixed-clock";
91	clock-frequency = <480000000>;
92	clock-output-names = "mpll";
93	#clock-cells = <0>;
94	};
95
96	ahbbridge0: bus@40000000 {
97	compatible = "simple-bus";
98	#address-cells = <1>;
99	#size-cells = <1>;
100	reg = <0x40000000 0x800000>;
101	ranges;
102
103	lpuart4: serial@402d0000 {
104	compatible = "fsl,imx7ulp-lpuart";
105	reg = <0x402d0000 0x1000>;
106	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
107	clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
108	clock-names = "ipg";
109	assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
110	assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
111	assigned-clock-rates = <24000000>;
112	status = "disabled";
113	};
114
115	lpuart5: serial@402e0000 {
116	compatible = "fsl,imx7ulp-lpuart";
117	reg = <0x402e0000 0x1000>;
118	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
119	clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
120	clock-names = "ipg";
121	assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
122	assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
123	assigned-clock-rates = <48000000>;
124	status = "disabled";
125	};
126
127	tpm5: tpm@40260000 {
128	compatible = "fsl,imx7ulp-tpm";
129	reg = <0x40260000 0x1000>;
130	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
131	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
132	<&pcc2 IMX7ULP_CLK_LPTPM5>;
133	clock-names = "ipg", "per";
134	};
135
136	usdhc0: mmc@40370000 {
137	compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
138	reg = <0x40370000 0x10000>;
139	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
140	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
141	<&scg1 IMX7ULP_CLK_NIC1_DIV>,
142	<&pcc2 IMX7ULP_CLK_USDHC0>;
143	clock-names ="ipg", "ahb", "per";
144	assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
145	assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
146	bus-width = <4>;
147	fsl,tuning-start-tap = <20>;
148	fsl,tuning-step= <2>;
149	status = "disabled";
150	};
151
152	usdhc1: mmc@40380000 {
153	compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
154	reg = <0x40380000 0x10000>;
155	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
156	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
157	<&scg1 IMX7ULP_CLK_NIC1_DIV>,
158	<&pcc2 IMX7ULP_CLK_USDHC1>;
159	clock-names ="ipg", "ahb", "per";
160	assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
161	assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
162	bus-width = <4>;
163	fsl,tuning-start-tap = <20>;
164	fsl,tuning-step= <2>;
165	status = "disabled";
166	};
167
168	scg1: clock-controller@403e0000 {
169	compatible = "fsl,imx7ulp-scg1";
170	reg = <0x403e0000 0x10000>;
171	clocks = <&rosc>, <&sosc>, <&sirc>,
172	<&firc>, <&upll>, <&mpll>;
173	clock-names = "rosc", "sosc", "sirc",
174	"firc", "upll", "mpll";
175	#clock-cells = <1>;
176	};
177
178	pcc2: clock-controller@403f0000 {
179	compatible = "fsl,imx7ulp-pcc2";
180	reg = <0x403f0000 0x10000>;
181	#clock-cells = <1>;
182	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
183	<&scg1 IMX7ULP_CLK_NIC1_DIV>,
184	<&scg1 IMX7ULP_CLK_DDR_DIV>,
185	<&scg1 IMX7ULP_CLK_APLL_PFD2>,
186	<&scg1 IMX7ULP_CLK_APLL_PFD1>,
187	<&scg1 IMX7ULP_CLK_APLL_PFD0>,
188	<&scg1 IMX7ULP_CLK_UPLL>,
189	<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
190	<&scg1 IMX7ULP_CLK_MIPI_PLL>,
191	<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
192	<&scg1 IMX7ULP_CLK_ROSC>,
193	<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
194	clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
195	"apll_pfd2", "apll_pfd1", "apll_pfd0",
196	"upll", "sosc_bus_clk", "mpll",
197	"firc_bus_clk", "rosc", "spll_bus_clk";
198	assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
199	assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
200	};
201
13c033bc	202	smc1: clock-controller@40410000 {
20434dc9 D	203	compatible = "fsl,imx7ulp-smc1";
20434dc9 D	204	reg = <0x40410000 0x1000>;
13c033bc AH	205	#clock-cells = <1>;
	206	clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
	207	<&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
	208	clock-names = "divcore", "hsrun_divcore";
20434dc9 D	209	};
	210
	211	pcc3: clock-controller@40b30000 {
	212	compatible = "fsl,imx7ulp-pcc3";
	213	reg = <0x40b30000 0x10000>;
	214	#clock-cells = <1>;
	215	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
	216	<&scg1 IMX7ULP_CLK_NIC1_DIV>,
	217	<&scg1 IMX7ULP_CLK_DDR_DIV>,
	218	<&scg1 IMX7ULP_CLK_APLL_PFD2>,
	219	<&scg1 IMX7ULP_CLK_APLL_PFD1>,
	220	<&scg1 IMX7ULP_CLK_APLL_PFD0>,
	221	<&scg1 IMX7ULP_CLK_UPLL>,
	222	<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
	223	<&scg1 IMX7ULP_CLK_MIPI_PLL>,
	224	<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
	225	<&scg1 IMX7ULP_CLK_ROSC>,
	226	<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
	227	clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
	228	"apll_pfd2", "apll_pfd1", "apll_pfd0",
	229	"upll", "sosc_bus_clk", "mpll",
	230	"firc_bus_clk", "rosc", "spll_bus_clk";
	231	};
	232	};
	233
	234	ahbbridge1: bus@40800000 {
	235	compatible = "simple-bus";
	236	#address-cells = <1>;
	237	#size-cells = <1>;
	238	reg = <0x40800000 0x800000>;
	239	ranges;
	240
	241	lpi2c6: i2c@40a40000 {
	242	compatible = "fsl,imx7ulp-lpi2c";
	243	reg = <0x40a40000 0x10000>;
	244	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	245	clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
	246	clock-names = "ipg";
	247	assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
	248	assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
	249	assigned-clock-rates = <48000000>;
	250	status = "disabled";
	251	};
	252
	253	lpi2c7: i2c@40a50000 {
	254	compatible = "fsl,imx7ulp-lpi2c";
	255	reg = <0x40a50000 0x10000>;
	256	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	257	clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
	258	clock-names = "ipg";
	259	assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
	260	assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
	261	assigned-clock-rates = <48000000>;
	262	status = "disabled";
	263	};
	264
	265	lpuart6: serial@40a60000 {
	266	compatible = "fsl,imx7ulp-lpuart";
	267	reg = <0x40a60000 0x1000>;
	268	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	269	clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
	270	clock-names = "ipg";
	271	assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
	272	assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
273	assigned-clock-rates = <48000000>;
274	status = "disabled";
275	};
276
277	lpuart7: serial@40a70000 {
278	compatible = "fsl,imx7ulp-lpuart";
279	reg = <0x40a70000 0x1000>;
280	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
281	clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
282	clock-names = "ipg";
283	assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
284	assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
285	assigned-clock-rates = <48000000>;
286	status = "disabled";
287	};
288
289	iomuxc1: pinctrl@40ac0000 {
290	compatible = "fsl,imx7ulp-iomuxc1";
291	reg = <0x40ac0000 0x1000>;
292	};
293
294	gpio_ptc: gpio@40ae0000 {
295	compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
296	reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
297	gpio-controller;
298	#gpio-cells = <2>;
299	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
300	interrupt-controller;
301	#interrupt-cells = <2>;
302	clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
303	<&pcc3 IMX7ULP_CLK_PCTLC>;
304	clock-names = "gpio", "port";
305	gpio-ranges = <&iomuxc1 0 0 32>;
306	};
307
308	gpio_ptd: gpio@40af0000 {
309	compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
310	reg = <0x40af0000 0x1000 0x400f0040 0x40>;
311	gpio-controller;
312	#gpio-cells = <2>;
313	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
314	interrupt-controller;
315	#interrupt-cells = <2>;
316	clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
317	<&pcc3 IMX7ULP_CLK_PCTLD>;
318	clock-names = "gpio", "port";
319	gpio-ranges = <&iomuxc1 0 32 32>;
320	};
321
322	gpio_pte: gpio@40b00000 {
323	compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
324	reg = <0x40b00000 0x1000 0x400f0080 0x40>;
325	gpio-controller;
326	#gpio-cells = <2>;
327	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
328	interrupt-controller;
329	#interrupt-cells = <2>;
330	clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
331	<&pcc3 IMX7ULP_CLK_PCTLE>;
332	clock-names = "gpio", "port";
333	gpio-ranges = <&iomuxc1 0 64 32>;
334	};
335
336	gpio_ptf: gpio@40b10000 {
337	compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
338	reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
339	gpio-controller;
340	#gpio-cells = <2>;
341	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
342	interrupt-controller;
343	#interrupt-cells = <2>;
344	clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
345	<&pcc3 IMX7ULP_CLK_PCTLF>;
346	clock-names = "gpio", "port";
347	gpio-ranges = <&iomuxc1 0 96 32>;
348	};
349	};
cc077d00 AH	350
	351	m4aips1: bus@41080000 {
	352	compatible = "simple-bus";
	353	#address-cells = <1>;
	354	#size-cells = <1>;
	355	reg = <0x41080000 0x80000>;
	356	ranges;
	357
	358	sim: sim@410a3000 {
	359	compatible = "fsl,imx7ulp-sim", "syscon";
	360	reg = <0x410a3000 0x1000>;
	361	};
	362	};
20434dc9	363	};