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Commit | Line | Data |
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4980f9bc LW |
1 | /* |
2 | * Device Tree for the ARM Integrator/AP platform | |
3 | */ | |
4 | ||
5 | /dts-v1/; | |
6 | /include/ "integrator.dtsi" | |
7 | ||
8 | / { | |
9 | model = "ARM Integrator/AP"; | |
10 | compatible = "arm,integrator-ap"; | |
11 | ||
12 | aliases { | |
13 | arm,timer-primary = &timer2; | |
14 | arm,timer-secondary = &timer1; | |
15 | }; | |
16 | ||
17 | chosen { | |
18 | bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; | |
19 | }; | |
20 | ||
b7929852 LW |
21 | /* 24 MHz chrystal on the core module */ |
22 | xtal24mhz: xtal24mhz@24M { | |
23 | #clock-cells = <0>; | |
24 | compatible = "fixed-clock"; | |
25 | clock-frequency = <24000000>; | |
26 | }; | |
27 | ||
28 | pclk: pclk@0 { | |
29 | #clock-cells = <0>; | |
30 | compatible = "fixed-factor-clock"; | |
31 | clock-div = <1>; | |
32 | clock-mult = <1>; | |
33 | clocks = <&xtal24mhz>; | |
34 | }; | |
35 | ||
36 | /* The UART clock is 14.74 MHz divided by an ICS525 */ | |
37 | uartclk: uartclk@14.74M { | |
38 | #clock-cells = <0>; | |
39 | compatible = "fixed-clock"; | |
40 | clock-frequency = <14745600>; | |
41 | }; | |
42 | ||
e67ae6be | 43 | syscon { |
df36680f | 44 | compatible = "arm,integrator-ap-syscon"; |
e67ae6be | 45 | reg = <0x11000000 0x100>; |
a6720258 LW |
46 | interrupt-parent = <&pic>; |
47 | /* These are the logical module IRQs */ | |
48 | interrupts = <9>, <10>, <11>, <12>; | |
e67ae6be LW |
49 | }; |
50 | ||
4980f9bc LW |
51 | timer0: timer@13000000 { |
52 | compatible = "arm,integrator-timer"; | |
b7929852 | 53 | clocks = <&xtal24mhz>; |
4980f9bc LW |
54 | }; |
55 | ||
56 | timer1: timer@13000100 { | |
57 | compatible = "arm,integrator-timer"; | |
b7929852 | 58 | clocks = <&xtal24mhz>; |
4980f9bc LW |
59 | }; |
60 | ||
61 | timer2: timer@13000200 { | |
62 | compatible = "arm,integrator-timer"; | |
b7929852 | 63 | clocks = <&xtal24mhz>; |
4980f9bc LW |
64 | }; |
65 | ||
66 | pic: pic@14000000 { | |
67 | valid-mask = <0x003fffff>; | |
68 | }; | |
4672cddf | 69 | |
f55b2b56 LW |
70 | pci: pciv3@62000000 { |
71 | compatible = "v3,v360epc-pci"; | |
72 | #interrupt-cells = <1>; | |
73 | #size-cells = <2>; | |
74 | #address-cells = <3>; | |
75 | reg = <0x62000000 0x10000>; | |
76 | interrupt-parent = <&pic>; | |
77 | interrupts = <17>; /* Bus error IRQ */ | |
78 | ranges = <0x00000000 0 0x61000000 /* config space */ | |
79 | 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */ | |
56ce3ffb | 80 | 0x01000000 0 0x0 /* I/O space */ |
f55b2b56 | 81 | 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */ |
56ce3ffb | 82 | 0x02000000 0 0x00000000 /* non-prefectable memory */ |
f55b2b56 | 83 | 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */ |
56ce3ffb | 84 | 0x42000000 0 0x10000000 /* prefetchable memory */ |
f55b2b56 LW |
85 | 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */ |
86 | interrupt-map-mask = <0xf800 0 0 0x7>; | |
87 | interrupt-map = < | |
88 | /* IDSEL 9 */ | |
89 | 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ | |
90 | 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ | |
91 | 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ | |
92 | 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ | |
93 | /* IDSEL 10 */ | |
94 | 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ | |
95 | 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ | |
96 | 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ | |
97 | 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ | |
98 | /* IDSEL 11 */ | |
99 | 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ | |
100 | 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ | |
101 | 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ | |
102 | 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ | |
103 | /* IDSEL 12 */ | |
104 | 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ | |
105 | 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ | |
106 | 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ | |
107 | 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ | |
108 | >; | |
109 | }; | |
110 | ||
4672cddf LW |
111 | fpga { |
112 | /* | |
113 | * The Integator/AP predates the idea to have magic numbers | |
114 | * identifying the PrimeCell in hardware, thus we have to | |
115 | * supply these from the device tree. | |
116 | */ | |
117 | rtc: rtc@15000000 { | |
118 | compatible = "arm,pl030", "arm,primecell"; | |
119 | arm,primecell-periphid = <0x00041030>; | |
b7929852 LW |
120 | clocks = <&pclk>; |
121 | clock-names = "apb_pclk"; | |
4672cddf LW |
122 | }; |
123 | ||
124 | uart0: uart@16000000 { | |
125 | compatible = "arm,pl010", "arm,primecell"; | |
126 | arm,primecell-periphid = <0x00041010>; | |
b7929852 LW |
127 | clocks = <&uartclk>, <&pclk>; |
128 | clock-names = "uartclk", "apb_pclk"; | |
4672cddf LW |
129 | }; |
130 | ||
131 | uart1: uart@17000000 { | |
132 | compatible = "arm,pl010", "arm,primecell"; | |
133 | arm,primecell-periphid = <0x00041010>; | |
b7929852 LW |
134 | clocks = <&uartclk>, <&pclk>; |
135 | clock-names = "uartclk", "apb_pclk"; | |
4672cddf LW |
136 | }; |
137 | ||
138 | kmi0: kmi@18000000 { | |
139 | compatible = "arm,pl050", "arm,primecell"; | |
140 | arm,primecell-periphid = <0x00041050>; | |
b7929852 LW |
141 | clocks = <&xtal24mhz>, <&pclk>; |
142 | clock-names = "KMIREFCLK", "apb_pclk"; | |
4672cddf LW |
143 | }; |
144 | ||
145 | kmi1: kmi@19000000 { | |
146 | compatible = "arm,pl050", "arm,primecell"; | |
147 | arm,primecell-periphid = <0x00041050>; | |
b7929852 LW |
148 | clocks = <&xtal24mhz>, <&pclk>; |
149 | clock-names = "KMIREFCLK", "apb_pclk"; | |
4672cddf LW |
150 | }; |
151 | }; | |
4980f9bc | 152 | }; |