[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / integratorap.dts

/*
 * Device Tree for the ARM Integrator/AP platform
 */

/dts-v1/;
/include/ "integrator.dtsi"

/ {
	model = "ARM Integrator/AP";
	compatible = "arm,integrator-ap";
	dma-ranges = <0x80000000 0x0 0x80000000>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			/*
			 * Since the board has pluggable CPU modules, we
			 * cannot define a proper compatible here. Let the
			 * boot loader fill in the apropriate compatible
			 * string if necessary.
			 */
			/* compatible = "arm,arm926ej-s"; */
			reg = <0>;
			/*
			 * The documentation in ARM DUI 0138E page 3-12 states
			 * that the maximum frequency for this clock is 200 MHz
			 * but painful trial-and-error has proved to me that it
			 * is actually just hanging the system above 71 MHz.
			 * Sad but true.
			 */
					 /* kHz     uV   */
			operating-points = <71000  0
					    66000  0
					    60000  0
					    48000  0
					    36000  0
					    24000  0
					    12000  0>;
			clocks = <&cmosc>;
			clock-names = "cpu";
			clock-latency = <1000000>; /* 1 ms */
		};
	};

	aliases {
		arm,timer-primary = &timer2;
		arm,timer-secondary = &timer1;
	};

	chosen {
		bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
	};

	/* 24 MHz chrystal on the Integrator/AP development board */
	xtal24mhz: xtal24mhz@24M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
	};

	pclk: pclk@0 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	/* The UART clock is 14.74 MHz divided by an ICS525 */
	uartclk: uartclk@14.74M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <14745600>;
		clocks = <&xtal24mhz>;
	};

	core-module@10000000 {
		/* 24 MHz chrystal on the core module */
		cm24mhz: cm24mhz@24M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		/* Oscillator on the core module, clocks the CPU core */
		cmosc: cmosc@24M {
			compatible = "arm,syscon-icst525-integratorap-cm";
			#clock-cells = <0>;
			lock-offset = <0x14>;
			vco-offset = <0x08>;
			clocks = <&cm24mhz>;
		};

		/* Auxilary oscillator on the core module, 32.369MHz at boot */
		auxosc: auxosc@24M {
			compatible = "arm,syscon-icst525";
			#clock-cells = <0>;
			lock-offset = <0x14>;
			vco-offset = <0x1c>;
			clocks = <&cm24mhz>;
		};
	};

	syscon {
		compatible = "arm,integrator-ap-syscon", "syscon";
		reg = <0x11000000 0x100>;
		interrupt-parent = <&pic>;
		/* These are the logical module IRQs */
		interrupts = <9>, <10>, <11>, <12>;

		/*
		 * SYSCLK clocks PCIv3 bridge, system controller and the
		 * logic modules.
		 */
		sysclk: apsys@24M {
			compatible = "arm,syscon-icst525-integratorap-sys";
			#clock-cells = <0>;
			lock-offset = <0x1c>;
			vco-offset = <0x04>;
			clocks = <&xtal24mhz>;
		};

		/* One-bit control for the PCI bus clock (33 or 25 MHz) */
		pciclk: pciclk@24M {
			compatible = "arm,syscon-icst525-integratorap-pci";
			#clock-cells = <0>;
			lock-offset = <0x1c>;
			vco-offset = <0x04>;
			clocks = <&xtal24mhz>;
		};
	};

	timer0: timer@13000000 {
		compatible = "arm,integrator-timer";
		clocks = <&xtal24mhz>;
	};

	timer1: timer@13000100 {
		compatible = "arm,integrator-timer";
		clocks = <&xtal24mhz>;
	};

	timer2: timer@13000200 {
		compatible = "arm,integrator-timer";
		clocks = <&xtal24mhz>;
	};

	pic: pic@14000000 {
		valid-mask = <0x003fffff>;
	};

	pci: pciv3@62000000 {
		compatible = "v3,v360epc-pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0x62000000 0x10000>;
		interrupt-parent = <&pic>;
		interrupts = <17>; /* Bus error IRQ */
		ranges = <0x00000000 0 0x61000000 /* config space */
			0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
			0x01000000 0 0x0 /* I/O space */
			0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
			0x02000000 0 0x00000000 /* non-prefectable memory */
			0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
			0x42000000 0 0x10000000 /* prefetchable memory */
			0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
		interrupt-map-mask = <0xf800 0 0 0x7>;
		interrupt-map = <
		/* IDSEL 9 */
		0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
		0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
		0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
		0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
		/* IDSEL 10 */
		0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
		0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
		0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
		0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
		/* IDSEL 11 */
		0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
		0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
		0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
		0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
		/* IDSEL 12 */
		0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
		0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
		0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
		0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
		>;
	};

	fpga {
		/*
		 * The Integator/AP predates the idea to have magic numbers
		 * identifying the PrimeCell in hardware, thus we have to
		 * supply these from the device tree.
		 */
		rtc: rtc@15000000 {
			compatible = "arm,pl030", "arm,primecell";
			arm,primecell-periphid = <0x00041030>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		uart0: uart@16000000 {
			compatible = "arm,pl010", "arm,primecell";
			arm,primecell-periphid = <0x00041010>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart1: uart@17000000 {
			compatible = "arm,pl010", "arm,primecell";
			arm,primecell-periphid = <0x00041010>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		kmi0: kmi@18000000 {
			compatible = "arm,pl050", "arm,primecell";
			arm,primecell-periphid = <0x00041050>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};

		kmi1: kmi@19000000 {
			compatible = "arm,pl050", "arm,primecell";
			arm,primecell-periphid = <0x00041050>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};
	};
};
Commit	Line	Data
4980f9bc LW	1	/*
	2	* Device Tree for the ARM Integrator/AP platform
	3	*/
	4
	5	/dts-v1/;
	6	/include/ "integrator.dtsi"
	7
	8	/ {
	9	model = "ARM Integrator/AP";
	10	compatible = "arm,integrator-ap";
e6dc195c	11	dma-ranges = <0x80000000 0x0 0x80000000>;
4980f9bc	12
964971c8 LW	13	cpus {
	14	#address-cells = <1>;
	15	#size-cells = <0>;
	16
	17	cpu@0 {
	18	device_type = "cpu";
	19	/*
	20	* Since the board has pluggable CPU modules, we
	21	* cannot define a proper compatible here. Let the
	22	* boot loader fill in the apropriate compatible
	23	* string if necessary.
	24	*/
	25	/* compatible = "arm,arm926ej-s"; */
	26	reg = <0>;
	27	/*
	28	* The documentation in ARM DUI 0138E page 3-12 states
	29	* that the maximum frequency for this clock is 200 MHz
	30	* but painful trial-and-error has proved to me that it
	31	* is actually just hanging the system above 71 MHz.
	32	* Sad but true.
	33	*/
	34	/* kHz uV */
	35	operating-points = <71000 0
	36	66000 0
	37	60000 0
	38	48000 0
	39	36000 0
	40	24000 0
	41	12000 0>;
	42	clocks = <&cmosc>;
	43	clock-names = "cpu";
	44	clock-latency = <1000000>; /* 1 ms */
	45	};
	46	};
	47
4980f9bc LW	48	aliases {
	49	arm,timer-primary = &timer2;
	50	arm,timer-secondary = &timer1;
	51	};
	52
	53	chosen {
	54	bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
	55	};
	56
257417ec	57	/* 24 MHz chrystal on the Integrator/AP development board */
b7929852 LW	58	xtal24mhz: xtal24mhz@24M {
	59	#clock-cells = <0>;
	60	compatible = "fixed-clock";
	61	clock-frequency = <24000000>;
	62	};
	63
	64	pclk: pclk@0 {
	65	#clock-cells = <0>;
	66	compatible = "fixed-factor-clock";
	67	clock-div = <1>;
	68	clock-mult = <1>;
	69	clocks = <&xtal24mhz>;
	70	};
	71
	72	/* The UART clock is 14.74 MHz divided by an ICS525 */
	73	uartclk: uartclk@14.74M {
	74	#clock-cells = <0>;
	75	compatible = "fixed-clock";
	76	clock-frequency = <14745600>;
e272b7ee	77	clocks = <&xtal24mhz>;
b7929852 LW	78	};
b7929852 LW	79
257417ec LW	80	core-module@10000000 {
	81	/* 24 MHz chrystal on the core module */
	82	cm24mhz: cm24mhz@24M {
	83	#clock-cells = <0>;
	84	compatible = "fixed-clock";
	85	clock-frequency = <24000000>;
	86	};
	87
	88	/* Oscillator on the core module, clocks the CPU core */
	89	cmosc: cmosc@24M {
	90	compatible = "arm,syscon-icst525-integratorap-cm";
	91	#clock-cells = <0>;
	92	lock-offset = <0x14>;
	93	vco-offset = <0x08>;
	94	clocks = <&cm24mhz>;
	95	};
	96
	97	/* Auxilary oscillator on the core module, 32.369MHz at boot */
	98	auxosc: auxosc@24M {
	99	compatible = "arm,syscon-icst525";
	100	#clock-cells = <0>;
	101	lock-offset = <0x14>;
	102	vco-offset = <0x1c>;
	103	clocks = <&cm24mhz>;
	104	};
b7929852 LW	105	};
b7929852 LW	106
e67ae6be	107	syscon {
f2b54191	108	compatible = "arm,integrator-ap-syscon", "syscon";
e67ae6be	109	reg = <0x11000000 0x100>;
a6720258 LW	110	interrupt-parent = <&pic>;
	111	/* These are the logical module IRQs */
	112	interrupts = <9>, <10>, <11>, <12>;
49eb1efa LW	113
	114	/*
	115	* SYSCLK clocks PCIv3 bridge, system controller and the
	116	* logic modules.
	117	*/
	118	sysclk: apsys@24M {
	119	compatible = "arm,syscon-icst525-integratorap-sys";
	120	#clock-cells = <0>;
	121	lock-offset = <0x1c>;
	122	vco-offset = <0x04>;
	123	clocks = <&xtal24mhz>;
	124	};
	125
	126	/* One-bit control for the PCI bus clock (33 or 25 MHz) */
	127	pciclk: pciclk@24M {
	128	compatible = "arm,syscon-icst525-integratorap-pci";
	129	#clock-cells = <0>;
	130	lock-offset = <0x1c>;
	131	vco-offset = <0x04>;
	132	clocks = <&xtal24mhz>;
	133	};
e67ae6be LW	134	};
e67ae6be LW	135
4980f9bc LW	136	timer0: timer@13000000 {
4980f9bc LW	137	compatible = "arm,integrator-timer";
b7929852	138	clocks = <&xtal24mhz>;
4980f9bc LW	139	};
	140
	141	timer1: timer@13000100 {
	142	compatible = "arm,integrator-timer";
b7929852	143	clocks = <&xtal24mhz>;
4980f9bc LW	144	};
	145
	146	timer2: timer@13000200 {
	147	compatible = "arm,integrator-timer";
b7929852	148	clocks = <&xtal24mhz>;
4980f9bc LW	149	};
	150
	151	pic: pic@14000000 {
	152	valid-mask = <0x003fffff>;
	153	};
4672cddf	154
f55b2b56 LW	155	pci: pciv3@62000000 {
	156	compatible = "v3,v360epc-pci";
	157	#interrupt-cells = <1>;
	158	#size-cells = <2>;
	159	#address-cells = <3>;
	160	reg = <0x62000000 0x10000>;
	161	interrupt-parent = <&pic>;
	162	interrupts = <17>; /* Bus error IRQ */
	163	ranges = <0x00000000 0 0x61000000 /* config space */
	164	0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
56ce3ffb	165	0x01000000 0 0x0 /* I/O space */
f55b2b56	166	0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
56ce3ffb	167	0x02000000 0 0x00000000 /* non-prefectable memory */
f55b2b56	168	0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
56ce3ffb	169	0x42000000 0 0x10000000 /* prefetchable memory */
f55b2b56 LW	170	0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
	171	interrupt-map-mask = <0xf800 0 0 0x7>;
	172	interrupt-map = <
	173	/* IDSEL 9 */
	174	0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
	175	0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
	176	0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
	177	0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
	178	/* IDSEL 10 */
	179	0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
	180	0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
	181	0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
	182	0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
	183	/* IDSEL 11 */
	184	0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
	185	0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
	186	0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
	187	0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
	188	/* IDSEL 12 */
	189	0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
	190	0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
	191	0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
	192	0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
	193	>;
	194	};
	195
4672cddf LW	196	fpga {
	197	/*
	198	* The Integator/AP predates the idea to have magic numbers
	199	* identifying the PrimeCell in hardware, thus we have to
	200	* supply these from the device tree.
	201	*/
	202	rtc: rtc@15000000 {
	203	compatible = "arm,pl030", "arm,primecell";
	204	arm,primecell-periphid = <0x00041030>;
b7929852 LW	205	clocks = <&pclk>;
b7929852 LW	206	clock-names = "apb_pclk";
4672cddf LW	207	};
	208
	209	uart0: uart@16000000 {
	210	compatible = "arm,pl010", "arm,primecell";
	211	arm,primecell-periphid = <0x00041010>;
b7929852 LW	212	clocks = <&uartclk>, <&pclk>;
b7929852 LW	213	clock-names = "uartclk", "apb_pclk";
4672cddf LW	214	};
	215
	216	uart1: uart@17000000 {
	217	compatible = "arm,pl010", "arm,primecell";
	218	arm,primecell-periphid = <0x00041010>;
b7929852 LW	219	clocks = <&uartclk>, <&pclk>;
b7929852 LW	220	clock-names = "uartclk", "apb_pclk";
4672cddf LW	221	};
	222
	223	kmi0: kmi@18000000 {
	224	compatible = "arm,pl050", "arm,primecell";
	225	arm,primecell-periphid = <0x00041050>;
b7929852 LW	226	clocks = <&xtal24mhz>, <&pclk>;
b7929852 LW	227	clock-names = "KMIREFCLK", "apb_pclk";
4672cddf LW	228	};
	229
	230	kmi1: kmi@19000000 {
	231	compatible = "arm,pl050", "arm,primecell";
	232	arm,primecell-periphid = <0x00041050>;
b7929852 LW	233	clocks = <&xtal24mhz>, <&pclk>;
b7929852 LW	234	clock-names = "KMIREFCLK", "apb_pclk";
4672cddf LW	235	};
4672cddf LW	236	};
4980f9bc	237	};