]>
Commit | Line | Data |
---|---|---|
4980f9bc LW |
1 | /* |
2 | * Device Tree for the ARM Integrator/AP platform | |
3 | */ | |
4 | ||
5 | /dts-v1/; | |
6 | /include/ "integrator.dtsi" | |
7 | ||
8 | / { | |
9 | model = "ARM Integrator/AP"; | |
10 | compatible = "arm,integrator-ap"; | |
e6dc195c | 11 | dma-ranges = <0x80000000 0x0 0x80000000>; |
4980f9bc LW |
12 | |
13 | aliases { | |
14 | arm,timer-primary = &timer2; | |
15 | arm,timer-secondary = &timer1; | |
16 | }; | |
17 | ||
18 | chosen { | |
19 | bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk"; | |
20 | }; | |
21 | ||
b7929852 LW |
22 | /* 24 MHz chrystal on the core module */ |
23 | xtal24mhz: xtal24mhz@24M { | |
24 | #clock-cells = <0>; | |
25 | compatible = "fixed-clock"; | |
26 | clock-frequency = <24000000>; | |
27 | }; | |
28 | ||
29 | pclk: pclk@0 { | |
30 | #clock-cells = <0>; | |
31 | compatible = "fixed-factor-clock"; | |
32 | clock-div = <1>; | |
33 | clock-mult = <1>; | |
34 | clocks = <&xtal24mhz>; | |
35 | }; | |
36 | ||
37 | /* The UART clock is 14.74 MHz divided by an ICS525 */ | |
38 | uartclk: uartclk@14.74M { | |
39 | #clock-cells = <0>; | |
40 | compatible = "fixed-clock"; | |
41 | clock-frequency = <14745600>; | |
e272b7ee | 42 | clocks = <&xtal24mhz>; |
b7929852 LW |
43 | }; |
44 | ||
e67ae6be | 45 | syscon { |
df36680f | 46 | compatible = "arm,integrator-ap-syscon"; |
e67ae6be | 47 | reg = <0x11000000 0x100>; |
a6720258 LW |
48 | interrupt-parent = <&pic>; |
49 | /* These are the logical module IRQs */ | |
50 | interrupts = <9>, <10>, <11>, <12>; | |
e67ae6be LW |
51 | }; |
52 | ||
4980f9bc LW |
53 | timer0: timer@13000000 { |
54 | compatible = "arm,integrator-timer"; | |
b7929852 | 55 | clocks = <&xtal24mhz>; |
4980f9bc LW |
56 | }; |
57 | ||
58 | timer1: timer@13000100 { | |
59 | compatible = "arm,integrator-timer"; | |
b7929852 | 60 | clocks = <&xtal24mhz>; |
4980f9bc LW |
61 | }; |
62 | ||
63 | timer2: timer@13000200 { | |
64 | compatible = "arm,integrator-timer"; | |
b7929852 | 65 | clocks = <&xtal24mhz>; |
4980f9bc LW |
66 | }; |
67 | ||
68 | pic: pic@14000000 { | |
69 | valid-mask = <0x003fffff>; | |
70 | }; | |
4672cddf | 71 | |
f55b2b56 LW |
72 | pci: pciv3@62000000 { |
73 | compatible = "v3,v360epc-pci"; | |
74 | #interrupt-cells = <1>; | |
75 | #size-cells = <2>; | |
76 | #address-cells = <3>; | |
77 | reg = <0x62000000 0x10000>; | |
78 | interrupt-parent = <&pic>; | |
79 | interrupts = <17>; /* Bus error IRQ */ | |
80 | ranges = <0x00000000 0 0x61000000 /* config space */ | |
81 | 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */ | |
56ce3ffb | 82 | 0x01000000 0 0x0 /* I/O space */ |
f55b2b56 | 83 | 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */ |
56ce3ffb | 84 | 0x02000000 0 0x00000000 /* non-prefectable memory */ |
f55b2b56 | 85 | 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */ |
56ce3ffb | 86 | 0x42000000 0 0x10000000 /* prefetchable memory */ |
f55b2b56 LW |
87 | 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */ |
88 | interrupt-map-mask = <0xf800 0 0 0x7>; | |
89 | interrupt-map = < | |
90 | /* IDSEL 9 */ | |
91 | 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ | |
92 | 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ | |
93 | 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ | |
94 | 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ | |
95 | /* IDSEL 10 */ | |
96 | 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ | |
97 | 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ | |
98 | 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ | |
99 | 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ | |
100 | /* IDSEL 11 */ | |
101 | 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ | |
102 | 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ | |
103 | 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ | |
104 | 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ | |
105 | /* IDSEL 12 */ | |
106 | 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ | |
107 | 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ | |
108 | 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ | |
109 | 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ | |
110 | >; | |
111 | }; | |
112 | ||
4672cddf LW |
113 | fpga { |
114 | /* | |
115 | * The Integator/AP predates the idea to have magic numbers | |
116 | * identifying the PrimeCell in hardware, thus we have to | |
117 | * supply these from the device tree. | |
118 | */ | |
119 | rtc: rtc@15000000 { | |
120 | compatible = "arm,pl030", "arm,primecell"; | |
121 | arm,primecell-periphid = <0x00041030>; | |
b7929852 LW |
122 | clocks = <&pclk>; |
123 | clock-names = "apb_pclk"; | |
4672cddf LW |
124 | }; |
125 | ||
126 | uart0: uart@16000000 { | |
127 | compatible = "arm,pl010", "arm,primecell"; | |
128 | arm,primecell-periphid = <0x00041010>; | |
b7929852 LW |
129 | clocks = <&uartclk>, <&pclk>; |
130 | clock-names = "uartclk", "apb_pclk"; | |
4672cddf LW |
131 | }; |
132 | ||
133 | uart1: uart@17000000 { | |
134 | compatible = "arm,pl010", "arm,primecell"; | |
135 | arm,primecell-periphid = <0x00041010>; | |
b7929852 LW |
136 | clocks = <&uartclk>, <&pclk>; |
137 | clock-names = "uartclk", "apb_pclk"; | |
4672cddf LW |
138 | }; |
139 | ||
140 | kmi0: kmi@18000000 { | |
141 | compatible = "arm,pl050", "arm,primecell"; | |
142 | arm,primecell-periphid = <0x00041050>; | |
b7929852 LW |
143 | clocks = <&xtal24mhz>, <&pclk>; |
144 | clock-names = "KMIREFCLK", "apb_pclk"; | |
4672cddf LW |
145 | }; |
146 | ||
147 | kmi1: kmi@19000000 { | |
148 | compatible = "arm,pl050", "arm,primecell"; | |
149 | arm,primecell-periphid = <0x00041050>; | |
b7929852 LW |
150 | clocks = <&xtal24mhz>, <&pclk>; |
151 | clock-names = "KMIREFCLK", "apb_pclk"; | |
4672cddf LW |
152 | }; |
153 | }; | |
4980f9bc | 154 | }; |