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Commit | Line | Data |
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4980f9bc LW |
1 | /* |
2 | * Device Tree for the ARM Integrator/CP platform | |
3 | */ | |
4 | ||
5 | /dts-v1/; | |
6 | /include/ "integrator.dtsi" | |
7 | ||
8 | / { | |
9 | model = "ARM Integrator/CP"; | |
10 | compatible = "arm,integrator-cp"; | |
11 | ||
4980f9bc LW |
12 | chosen { |
13 | bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; | |
14 | }; | |
15 | ||
b7929852 LW |
16 | /* |
17 | * The Integrator/CP overall clocking architecture can be found in | |
18 | * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which | |
19 | * appear to illustrate the layout used in most configurations. | |
20 | */ | |
21 | ||
22 | /* The codec chrystal operates at 24.576 MHz */ | |
23 | xtal_codec: xtal24.576@24.576M { | |
24 | #clock-cells = <0>; | |
25 | compatible = "fixed-clock"; | |
26 | clock-frequency = <24576000>; | |
27 | }; | |
28 | ||
29 | /* The chrystal is divided by 2 by the codec for the AACI bit clock */ | |
30 | aaci_bitclk: aaci_bitclk@12.288M { | |
31 | #clock-cells = <0>; | |
32 | compatible = "fixed-factor-clock"; | |
33 | clock-div = <2>; | |
34 | clock-mult = <1>; | |
35 | clocks = <&xtal_codec>; | |
36 | }; | |
37 | ||
38 | /* This is a 25MHz chrystal on the base board */ | |
39 | xtal25mhz: xtal25mhz@25M { | |
40 | #clock-cells = <0>; | |
41 | compatible = "fixed-clock"; | |
42 | clock-frequency = <25000000>; | |
43 | }; | |
44 | ||
45 | /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ | |
46 | uartclk: uartclk@14.74M { | |
47 | #clock-cells = <0>; | |
48 | compatible = "fixed-clock"; | |
49 | clock-frequency = <14745600>; | |
50 | }; | |
51 | ||
52 | /* Actually sysclk I think */ | |
53 | pclk: pclk@0 { | |
54 | #clock-cells = <0>; | |
55 | compatible = "fixed-clock"; | |
56 | clock-frequency = <0>; | |
57 | }; | |
58 | ||
59 | core-module@10000000 { | |
60 | /* 24 MHz chrystal on the core module */ | |
61 | xtal24mhz: xtal24mhz@24M { | |
62 | #clock-cells = <0>; | |
63 | compatible = "fixed-clock"; | |
64 | clock-frequency = <24000000>; | |
65 | }; | |
66 | ||
67 | /* | |
68 | * External oscillator on the core module, usually used | |
69 | * to drive video circuitry. Driven from the 24MHz clock. | |
70 | */ | |
71 | auxosc: cm_aux_osc@25M { | |
72 | #clock-cells = <0>; | |
73 | compatible = "arm,integrator-cm-auxosc"; | |
74 | clocks = <&xtal24mhz>; | |
75 | }; | |
76 | ||
77 | /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ | |
78 | kmiclk: kmiclk@1M { | |
79 | #clock-cells = <0>; | |
80 | compatible = "fixed-factor-clock"; | |
81 | clock-div = <3>; | |
82 | clock-mult = <1>; | |
83 | clocks = <&xtal24mhz>; | |
84 | }; | |
85 | ||
86 | /* The timer clock is the 24 MHz oscillator divided to 1MHz */ | |
87 | timclk: timclk@1M { | |
88 | #clock-cells = <0>; | |
89 | compatible = "fixed-factor-clock"; | |
90 | clock-div = <24>; | |
91 | clock-mult = <1>; | |
92 | clocks = <&xtal24mhz>; | |
93 | }; | |
94 | }; | |
95 | ||
df36680f LW |
96 | syscon { |
97 | compatible = "arm,integrator-cp-syscon"; | |
64100a03 LW |
98 | reg = <0xcb000000 0x100>; |
99 | }; | |
100 | ||
4980f9bc | 101 | timer0: timer@13000000 { |
b7929852 | 102 | /* TIMER0 runs directly on the 25MHz chrystal */ |
870e2928 | 103 | compatible = "arm,integrator-cp-timer"; |
b7929852 | 104 | clocks = <&xtal25mhz>; |
4980f9bc LW |
105 | }; |
106 | ||
107 | timer1: timer@13000100 { | |
29114fd7 | 108 | /* TIMER1 runs @ 1MHz */ |
870e2928 | 109 | compatible = "arm,integrator-cp-timer"; |
b7929852 | 110 | clocks = <&timclk>; |
4980f9bc LW |
111 | }; |
112 | ||
113 | timer2: timer@13000200 { | |
29114fd7 | 114 | /* TIMER2 runs @ 1MHz */ |
870e2928 | 115 | compatible = "arm,integrator-cp-timer"; |
b7929852 | 116 | clocks = <&timclk>; |
4980f9bc LW |
117 | }; |
118 | ||
119 | pic: pic@14000000 { | |
120 | valid-mask = <0x1fc003ff>; | |
121 | }; | |
122 | ||
123 | cic: cic@10000040 { | |
124 | compatible = "arm,versatile-fpga-irq"; | |
125 | #interrupt-cells = <1>; | |
126 | interrupt-controller; | |
127 | reg = <0x10000040 0x100>; | |
128 | clear-mask = <0xffffffff>; | |
129 | valid-mask = <0x00000007>; | |
130 | }; | |
131 | ||
8f6344fa | 132 | /* The SIC is cascaded off IRQ 26 on the PIC */ |
4980f9bc LW |
133 | sic: sic@ca000000 { |
134 | compatible = "arm,versatile-fpga-irq"; | |
8f6344fa LW |
135 | interrupt-parent = <&pic>; |
136 | interrupts = <26>; | |
4980f9bc LW |
137 | #interrupt-cells = <1>; |
138 | interrupt-controller; | |
139 | reg = <0xca000000 0x100>; | |
140 | clear-mask = <0x00000fff>; | |
141 | valid-mask = <0x00000fff>; | |
142 | }; | |
4672cddf | 143 | |
73efd530 LW |
144 | ethernet@c8000000 { |
145 | compatible = "smsc,lan91c111"; | |
146 | reg = <0xc8000000 0x10>; | |
147 | interrupt-parent = <&pic>; | |
148 | interrupts = <27>; | |
149 | }; | |
150 | ||
4672cddf LW |
151 | fpga { |
152 | /* | |
153 | * These PrimeCells are at the same location and using | |
154 | * the same interrupts in all Integrators, but in the CP | |
155 | * slightly newer versions are deployed. | |
156 | */ | |
157 | rtc@15000000 { | |
158 | compatible = "arm,pl031", "arm,primecell"; | |
b7929852 LW |
159 | clocks = <&pclk>; |
160 | clock-names = "apb_pclk"; | |
4672cddf LW |
161 | }; |
162 | ||
163 | uart@16000000 { | |
164 | compatible = "arm,pl011", "arm,primecell"; | |
b7929852 LW |
165 | clocks = <&uartclk>, <&pclk>; |
166 | clock-names = "uartclk", "apb_pclk"; | |
4672cddf LW |
167 | }; |
168 | ||
169 | uart@17000000 { | |
170 | compatible = "arm,pl011", "arm,primecell"; | |
b7929852 LW |
171 | clocks = <&uartclk>, <&pclk>; |
172 | clock-names = "uartclk", "apb_pclk"; | |
4672cddf LW |
173 | }; |
174 | ||
175 | kmi@18000000 { | |
176 | compatible = "arm,pl050", "arm,primecell"; | |
b7929852 LW |
177 | clocks = <&kmiclk>, <&pclk>; |
178 | clock-names = "KMIREFCLK", "apb_pclk"; | |
4672cddf LW |
179 | }; |
180 | ||
181 | kmi@19000000 { | |
182 | compatible = "arm,pl050", "arm,primecell"; | |
b7929852 LW |
183 | clocks = <&kmiclk>, <&pclk>; |
184 | clock-names = "KMIREFCLK", "apb_pclk"; | |
4672cddf LW |
185 | }; |
186 | ||
187 | /* | |
188 | * These PrimeCells are only available on the Integrator/CP | |
189 | */ | |
190 | mmc@1c000000 { | |
191 | compatible = "arm,pl180", "arm,primecell"; | |
192 | reg = <0x1c000000 0x1000>; | |
193 | interrupts = <23 24>; | |
194 | max-frequency = <515633>; | |
b7929852 LW |
195 | clocks = <&uartclk>, <&pclk>; |
196 | clock-names = "mclk", "apb_pclk"; | |
4672cddf LW |
197 | }; |
198 | ||
199 | aaci@1d000000 { | |
200 | compatible = "arm,pl041", "arm,primecell"; | |
201 | reg = <0x1d000000 0x1000>; | |
202 | interrupts = <25>; | |
b7929852 LW |
203 | clocks = <&pclk>; |
204 | clock-names = "apb_pclk"; | |
4672cddf LW |
205 | }; |
206 | ||
207 | clcd@c0000000 { | |
208 | compatible = "arm,pl110", "arm,primecell"; | |
209 | reg = <0xC0000000 0x1000>; | |
210 | interrupts = <22>; | |
b7929852 LW |
211 | clocks = <&auxosc>, <&pclk>; |
212 | clock-names = "clcd", "apb_pclk"; | |
4672cddf LW |
213 | }; |
214 | }; | |
4980f9bc | 215 | }; |