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Commit | Line | Data |
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209636b6 MK |
1 | /* |
2 | * Copyright 2014 Texas Instruments, Inc. | |
3 | * | |
4 | * Keystone 2 Edison SoC specific device tree | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | clocks { | |
12 | mainpllclk: mainpllclk@2310110 { | |
13 | #clock-cells = <0>; | |
14 | compatible = "ti,keystone,main-pll-clock"; | |
15 | clocks = <&refclksys>; | |
16 | reg = <0x02620350 4>, <0x02310110 4>; | |
17 | reg-names = "control", "multiplier"; | |
18 | fixed-postdiv = <2>; | |
19 | }; | |
20 | ||
21 | papllclk: papllclk@2620358 { | |
22 | #clock-cells = <0>; | |
23 | compatible = "ti,keystone,pll-clock"; | |
24 | clocks = <&refclkpass>; | |
25 | clock-output-names = "pa-pll-clk"; | |
26 | reg = <0x02620358 4>; | |
27 | reg-names = "control"; | |
28 | }; | |
29 | ||
30 | ddr3apllclk: ddr3apllclk@2620360 { | |
31 | #clock-cells = <0>; | |
32 | compatible = "ti,keystone,pll-clock"; | |
33 | clocks = <&refclkddr3a>; | |
34 | clock-output-names = "ddr-3a-pll-clk"; | |
35 | reg = <0x02620360 4>; | |
36 | reg-names = "control"; | |
37 | }; | |
38 | ||
39 | clkusb1: clkusb1 { | |
40 | #clock-cells = <0>; | |
41 | compatible = "ti,keystone,psc-clock"; | |
42 | clocks = <&chipclk16>; | |
43 | clock-output-names = "usb"; | |
44 | reg = <0x02350004 0xb00>, <0x02350000 0x400>; | |
45 | reg-names = "control", "domain"; | |
46 | domain-id = <0>; | |
47 | }; | |
48 | ||
49 | clkhyperlink0: clkhyperlink0 { | |
50 | #clock-cells = <0>; | |
51 | compatible = "ti,keystone,psc-clock"; | |
52 | clocks = <&chipclk12>; | |
53 | clock-output-names = "hyperlink-0"; | |
54 | reg = <0x02350030 0xb00>, <0x02350014 0x400>; | |
55 | reg-names = "control", "domain"; | |
56 | domain-id = <5>; | |
57 | }; | |
58 | ||
59 | clkpcie1: clkpcie1 { | |
60 | #clock-cells = <0>; | |
61 | compatible = "ti,keystone,psc-clock"; | |
62 | clocks = <&chipclk12>; | |
63 | clock-output-names = "pcie"; | |
64 | reg = <0x0235006c 0xb00>, <0x02350000 0x400>; | |
65 | reg-names = "control", "domain"; | |
66 | domain-id = <18>; | |
67 | }; | |
68 | ||
69 | clkxge: clkxge { | |
70 | #clock-cells = <0>; | |
71 | compatible = "ti,keystone,psc-clock"; | |
72 | clocks = <&chipclk13>; | |
73 | clock-output-names = "xge"; | |
74 | reg = <0x023500c8 0xb00>, <0x02350074 0x400>; | |
75 | reg-names = "control", "domain"; | |
76 | domain-id = <29>; | |
77 | }; | |
78 | }; |