[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / k2l-clocks.dtsi

/*
 * Copyright 2013-2014 Texas Instruments, Inc.
 *
 * Keystone 2 lamarr SoC clock nodes
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

clocks {
	armpllclk: armpllclk@2620370 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-clock";
		clocks = <&refclksys>;
		clock-output-names = "arm-pll-clk";
		reg = <0x02620370 4>;
		reg-names = "control";
	};

	mainpllclk: mainpllclk@2310110 {
		#clock-cells = <0>;
		compatible = "ti,keystone,main-pll-clock";
		clocks = <&refclksys>;
		reg = <0x02620350 4>, <0x02310110 4>;
		reg-names = "control", "multiplier";
		fixed-postdiv = <2>;
	};

	papllclk: papllclk@2620358 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-clock";
		clocks = <&refclksys>;
		clock-output-names = "papllclk";
		reg = <0x02620358 4>;
		reg-names = "control";
	};

	ddr3apllclk: ddr3apllclk@2620360 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-clock";
		clocks = <&refclksys>;
		clock-output-names = "ddr-3a-pll-clk";
		reg = <0x02620360 4>;
		reg-names = "control";
	};

	clkdfeiqnsys: clkdfeiqnsys {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk12>;
		clock-output-names = "dfe";
		reg-names = "control", "domain";
		reg = <0x02350004 0xb00>, <0x02350000 0x400>;
		domain-id = <0>;
	};

	clkpcie1: clkpcie1 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk12>;
		clock-output-names = "pcie";
		reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <4>;
	};

	clkgem1: clkgem1 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1>;
		clock-output-names = "gem1";
		reg = <0x02350040 0xb00>, <0x02350024 0x400>;
		reg-names = "control", "domain";
		domain-id = <9>;
	};

	clkgem2: clkgem2 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1>;
		clock-output-names = "gem2";
		reg = <0x02350044 0xb00>, <0x02350028 0x400>;
		reg-names = "control", "domain";
		domain-id = <10>;
	};

	clkgem3: clkgem3 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1>;
		clock-output-names = "gem3";
		reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
		reg-names = "control", "domain";
		domain-id = <11>;
	};

	clktac: clktac {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "tac";
		reg = <0x02350064 0xb00>, <0x02350044 0x400>;
		reg-names = "control", "domain";
		domain-id = <17>;
	};

	clkrac: clkrac {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "rac";
		reg = <0x02350068 0xb00>, <0x02350044 0x400>;
		reg-names = "control", "domain";
		domain-id = <17>;
	};

	clkdfepd0: clkdfepd0 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "dfe-pd0";
		reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
		reg-names = "control", "domain";
		domain-id = <18>;
	};

	clkfftc0: clkfftc0 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "fftc-0";
		reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
		reg-names = "control", "domain";
		domain-id = <19>;
	};

	clkosr: clkosr {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "osr";
		reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
		reg-names = "control", "domain";
		domain-id = <21>;
	};

	clktcp3d0: clktcp3d0 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "tcp3d-0";
		reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
		reg-names = "control", "domain";
		domain-id = <22>;
	};

	clktcp3d1: clktcp3d1 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "tcp3d-1";
		reg = <0x02350094 0xb00>, <0x02350058 0x400>;
		reg-names = "control", "domain";
		domain-id = <23>;
	};

	clkvcp0: clkvcp0 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-0";
		reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
		reg-names = "control", "domain";
		domain-id = <24>;
	};

	clkvcp1: clkvcp1 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-1";
		reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
		reg-names = "control", "domain";
		domain-id = <24>;
	};

	clkvcp2: clkvcp2 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-2";
		reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
		reg-names = "control", "domain";
		domain-id = <24>;
	};

	clkvcp3: clkvcp3 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-3";
		reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
		reg-names = "control", "domain";
		domain-id = <24>;
	};

	clkbcp: clkbcp {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "bcp";
		reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
		reg-names = "control", "domain";
		domain-id = <26>;
	};

	clkdfepd1: clkdfepd1 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "dfe-pd1";
		reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
		reg-names = "control", "domain";
		domain-id = <27>;
	};

	clkfftc1: clkfftc1 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "fftc-1";
		reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
		reg-names = "control", "domain";
		domain-id = <28>;
	};

	clkiqnail: clkiqnail {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "iqn-ail";
		reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
		reg-names = "control", "domain";
		domain-id = <29>;
	};

	clkuart2: clkuart2 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "uart2";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkuart3: clkuart3 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "uart3";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};
};
Commit	Line	Data
fc1c72eb MK	1	/*
	2	* Copyright 2013-2014 Texas Instruments, Inc.
	3	*
	4	* Keystone 2 lamarr SoC clock nodes
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	clocks {
	12	armpllclk: armpllclk@2620370 {
	13	#clock-cells = <0>;
	14	compatible = "ti,keystone,pll-clock";
	15	clocks = <&refclksys>;
	16	clock-output-names = "arm-pll-clk";
	17	reg = <0x02620370 4>;
	18	reg-names = "control";
	19	};
	20
	21	mainpllclk: mainpllclk@2310110 {
	22	#clock-cells = <0>;
	23	compatible = "ti,keystone,main-pll-clock";
	24	clocks = <&refclksys>;
	25	reg = <0x02620350 4>, <0x02310110 4>;
	26	reg-names = "control", "multiplier";
	27	fixed-postdiv = <2>;
	28	};
	29
	30	papllclk: papllclk@2620358 {
	31	#clock-cells = <0>;
	32	compatible = "ti,keystone,pll-clock";
	33	clocks = <&refclksys>;
2b7ef094	34	clock-output-names = "papllclk";
fc1c72eb MK	35	reg = <0x02620358 4>;
	36	reg-names = "control";
	37	};
	38
	39	ddr3apllclk: ddr3apllclk@2620360 {
	40	#clock-cells = <0>;
	41	compatible = "ti,keystone,pll-clock";
	42	clocks = <&refclksys>;
	43	clock-output-names = "ddr-3a-pll-clk";
	44	reg = <0x02620360 4>;
	45	reg-names = "control";
	46	};
	47
	48	clkdfeiqnsys: clkdfeiqnsys {
	49	#clock-cells = <0>;
	50	compatible = "ti,keystone,psc-clock";
	51	clocks = <&chipclk12>;
	52	clock-output-names = "dfe";
	53	reg-names = "control", "domain";
	54	reg = <0x02350004 0xb00>, <0x02350000 0x400>;
	55	domain-id = <0>;
	56	};
	57
	58	clkpcie1: clkpcie1 {
	59	#clock-cells = <0>;
	60	compatible = "ti,keystone,psc-clock";
	61	clocks = <&chipclk12>;
	62	clock-output-names = "pcie";
	63	reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
	64	reg-names = "control", "domain";
	65	domain-id = <4>;
	66	};
	67
	68	clkgem1: clkgem1 {
	69	#clock-cells = <0>;
	70	compatible = "ti,keystone,psc-clock";
	71	clocks = <&chipclk1>;
	72	clock-output-names = "gem1";
	73	reg = <0x02350040 0xb00>, <0x02350024 0x400>;
	74	reg-names = "control", "domain";
	75	domain-id = <9>;
	76	};
	77
	78	clkgem2: clkgem2 {
	79	#clock-cells = <0>;
	80	compatible = "ti,keystone,psc-clock";
	81	clocks = <&chipclk1>;
	82	clock-output-names = "gem2";
	83	reg = <0x02350044 0xb00>, <0x02350028 0x400>;
	84	reg-names = "control", "domain";
	85	domain-id = <10>;
	86	};
	87
	88	clkgem3: clkgem3 {
	89	#clock-cells = <0>;
	90	compatible = "ti,keystone,psc-clock";
	91	clocks = <&chipclk1>;
	92	clock-output-names = "gem3";
	93	reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
	94	reg-names = "control", "domain";
	95	domain-id = <11>;
	96	};
	97
	98	clktac: clktac {
99	#clock-cells = <0>;
100	compatible = "ti,keystone,psc-clock";
101	clocks = <&chipclk13>;
102	clock-output-names = "tac";
103	reg = <0x02350064 0xb00>, <0x02350044 0x400>;
104	reg-names = "control", "domain";
105	domain-id = <17>;
106	};
107
108	clkrac: clkrac {
109	#clock-cells = <0>;
110	compatible = "ti,keystone,psc-clock";
111	clocks = <&chipclk13>;
112	clock-output-names = "rac";
113	reg = <0x02350068 0xb00>, <0x02350044 0x400>;
114	reg-names = "control", "domain";
115	domain-id = <17>;
116	};
117
118	clkdfepd0: clkdfepd0 {
119	#clock-cells = <0>;
120	compatible = "ti,keystone,psc-clock";
121	clocks = <&chipclk13>;
122	clock-output-names = "dfe-pd0";
123	reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
124	reg-names = "control", "domain";
125	domain-id = <18>;
126	};
127
128	clkfftc0: clkfftc0 {
129	#clock-cells = <0>;
130	compatible = "ti,keystone,psc-clock";
131	clocks = <&chipclk13>;
132	clock-output-names = "fftc-0";
133	reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
134	reg-names = "control", "domain";
135	domain-id = <19>;
136	};
137
138	clkosr: clkosr {
139	#clock-cells = <0>;
140	compatible = "ti,keystone,psc-clock";
141	clocks = <&chipclk13>;
142	clock-output-names = "osr";
143	reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
144	reg-names = "control", "domain";
145	domain-id = <21>;
146	};
147
148	clktcp3d0: clktcp3d0 {
149	#clock-cells = <0>;
150	compatible = "ti,keystone,psc-clock";
151	clocks = <&chipclk13>;
152	clock-output-names = "tcp3d-0";
153	reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
154	reg-names = "control", "domain";
155	domain-id = <22>;
156	};
157
158	clktcp3d1: clktcp3d1 {
159	#clock-cells = <0>;
160	compatible = "ti,keystone,psc-clock";
161	clocks = <&chipclk13>;
162	clock-output-names = "tcp3d-1";
163	reg = <0x02350094 0xb00>, <0x02350058 0x400>;
164	reg-names = "control", "domain";
165	domain-id = <23>;
166	};
167
168	clkvcp0: clkvcp0 {
169	#clock-cells = <0>;
170	compatible = "ti,keystone,psc-clock";
171	clocks = <&chipclk13>;
172	clock-output-names = "vcp-0";
173	reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
174	reg-names = "control", "domain";
175	domain-id = <24>;
176	};
177
178	clkvcp1: clkvcp1 {
179	#clock-cells = <0>;
180	compatible = "ti,keystone,psc-clock";
181	clocks = <&chipclk13>;
182	clock-output-names = "vcp-1";
183	reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
184	reg-names = "control", "domain";
185	domain-id = <24>;
186	};
187
188	clkvcp2: clkvcp2 {
189	#clock-cells = <0>;
190	compatible = "ti,keystone,psc-clock";
191	clocks = <&chipclk13>;
192	clock-output-names = "vcp-2";
193	reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
194	reg-names = "control", "domain";
195	domain-id = <24>;
196	};
197
198	clkvcp3: clkvcp3 {
199	#clock-cells = <0>;
200	compatible = "ti,keystone,psc-clock";
201	clocks = <&chipclk13>;
202	clock-output-names = "vcp-3";
203	reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
204	reg-names = "control", "domain";
205	domain-id = <24>;
206	};
207
208	clkbcp: clkbcp {
209	#clock-cells = <0>;
210	compatible = "ti,keystone,psc-clock";
211	clocks = <&chipclk13>;
212	clock-output-names = "bcp";
213	reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
214	reg-names = "control", "domain";
215	domain-id = <26>;
216	};
217
218	clkdfepd1: clkdfepd1 {
219	#clock-cells = <0>;
220	compatible = "ti,keystone,psc-clock";
221	clocks = <&chipclk13>;
222	clock-output-names = "dfe-pd1";
223	reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
224	reg-names = "control", "domain";
225	domain-id = <27>;
226	};
227
228	clkfftc1: clkfftc1 {
229	#clock-cells = <0>;
230	compatible = "ti,keystone,psc-clock";
231	clocks = <&chipclk13>;
232	clock-output-names = "fftc-1";
233	reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
234	reg-names = "control", "domain";
235	domain-id = <28>;
236	};
237
238	clkiqnail: clkiqnail {
239	#clock-cells = <0>;
240	compatible = "ti,keystone,psc-clock";
241	clocks = <&chipclk13>;
242	clock-output-names = "iqn-ail";
243	reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
244	reg-names = "control", "domain";
245	domain-id = <29>;
246	};
247
248	clkuart2: clkuart2 {
249	#clock-cells = <0>;
250	compatible = "ti,keystone,psc-clock";
251	clocks = <&clkmodrst0>;
252	clock-output-names = "uart2";
253	reg = <0x02350000 0xb00>, <0x02350000 0x400>;
254	reg-names = "control", "domain";
255	domain-id = <0>;
256	};
257
258	clkuart3: clkuart3 {
259	#clock-cells = <0>;
260	compatible = "ti,keystone,psc-clock";
261	clocks = <&clkmodrst0>;
262	clock-output-names = "uart3";
263	reg = <0x02350000 0xb00>, <0x02350000 0x400>;
264	reg-names = "control", "domain";
265	domain-id = <0>;
266	};
267	};