[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / keystone.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "ti,keystone";
	model = "Texas Instruments Keystone 2 SoC";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	aliases {
		serial0	= &uart0;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
	};

	chosen { };

	memory: memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
	};

	gic: interrupt-controller {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x02561000 0x0 0x1000>,
		      <0x0 0x02562000 0x0 0x2000>,
		      <0x0 0x02564000 0x0 0x2000>,
		      <0x0 0x02566000 0x0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
				IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts =
			<GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
	};

	psci {
		compatible	= "arm,psci";
		method		= "smc";
		cpu_suspend	= <0x84000001>;
		cpu_off		= <0x84000002>;
		cpu_on		= <0x84000003>;
	};

	soc0: soc@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "ti,keystone","simple-bus";
		interrupt-parent = <&gic>;
		ranges = <0x0 0x0 0x0 0xc0000000>;
		dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;

		pllctrl: pll-controller@2310000 {
			compatible = "ti,keystone-pllctrl", "syscon";
			reg = <0x02310000 0x200>;
		};

		psc: power-sleep-controller@2350000 {
			compatible = "syscon", "simple-mfd";
			reg = <0x02350000 0x1000>;
		};

		devctrl: device-state-control@2620000 {
			compatible = "ti,keystone-devctrl", "syscon";
			reg = <0x02620000 0x1000>;
		};

		rstctrl: reset-controller {
			compatible = "ti,keystone-reset";
			ti,syscon-pll = <&pllctrl 0xe4>;
			ti,syscon-dev = <&devctrl 0x328>;
			ti,wdt-list = <0>;
		};

		/include/ "keystone-clocks.dtsi"

		uart0: serial@2530c00 {
			compatible = "ti,da830-uart", "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02530c00 0x100>;
			clocks	= <&clkuart0>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
		};

		uart1:	serial@2531000 {
			compatible = "ti,da830-uart", "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02531000 0x100>;
			clocks	= <&clkuart1>;
			interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
		};

		i2c0: i2c@2530000 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530000 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@2530400 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530400 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@2530800 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530800 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi0: spi@21000400 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000400 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@21000600 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000600 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi2: spi@21000800 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000800 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		usb_phy: usb_phy@2620738 {
			compatible = "ti,keystone-usbphy";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2620738 24>;
			status = "disabled";
		};

		keystone_usb0: usb@2680000 {
			compatible = "ti,keystone-dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2680000 0x10000>;
			clocks = <&clkusb>;
			clock-names = "usb";
			interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
			ranges;
			dma-coherent;
			dma-ranges;
			status = "disabled";

			usb0: dwc3@2690000 {
				compatible = "synopsys,dwc3";
				reg = <0x2690000 0x70000>;
				interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
				usb-phy = <&usb_phy>, <&usb_phy>;
			};
		};

		wdt: wdt@22f0080 {
			compatible = "ti,keystone-wdt","ti,davinci-wdt";
			reg = <0x022f0080 0x80>;
			clocks = <&clkwdtimer0>;
		};

		clock_event: timer@22f0000 {
			compatible = "ti,keystone-timer";
			reg = <0x022f0000 0x80>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clktimer15>;
		};

		gpio0: gpio@260bf00 {
			compatible = "ti,keystone-gpio";
			reg = <0x0260bf00 0x100>;
			gpio-controller;
			#gpio-cells = <2>;
			/* HW Interrupts mapped to GPIO pins */
			interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkgpio>;
			clock-names = "gpio";
			ti,ngpio = <32>;
			ti,davinci-gpio-unbanked = <32>;
		};

		aemif: aemif@21000A00 {
			compatible = "ti,keystone-aemif", "ti,davinci-aemif";
			#address-cells = <2>;
			#size-cells = <1>;
			clocks = <&clkaemif>;
			clock-names = "aemif";
			clock-ranges;

			reg = <0x21000A00 0x00000100>;
			ranges = <0 0 0x30000000 0x10000000
				  1 0 0x21000A00 0x00000100>;
		};

		kirq0: keystone_irq@26202a0 {
			compatible = "ti,keystone-irq";
			interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,syscon-dev = <&devctrl 0x2a0>;
		};

		pcie0: pcie@21800000 {
			compatible = "ti,keystone-pcie", "snps,dw-pcie";
			clocks = <&clkpcie>;
			clock-names = "pcie";
			#address-cells = <3>;
			#size-cells = <2>;
			reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
			ranges = <0x82000000 0 0x50000000 0x50000000
				  0 0x10000000>;

			status = "disabled";
			device_type = "pci";
			num-lanes = <2>;
			bus-range = <0x00 0xff>;

			/* error interrupt */
			interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
					<0 0 0 2 &pcie_intc0 1>, /* INT B */
					<0 0 0 3 &pcie_intc0 2>, /* INT C */
					<0 0 0 4 &pcie_intc0 3>; /* INT D */

			pcie_msi_intc0: msi-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
			};

			pcie_intc0: legacy-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
			};
		};
	};
};
Commit	Line	Data
d6392ae3	1	// SPDX-License-Identifier: GPL-2.0
d5e9fe84	2	/*
d6392ae3	3	* Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
d5e9fe84 SS	4	*/
d5e9fe84 SS	5
eb788f43	6	#include <dt-bindings/interrupt-controller/arm-gic.h>
970c2256	7	#include <dt-bindings/gpio/gpio.h>
eb788f43	8
d5e9fe84	9	/ {
91dca0f0	10	compatible = "ti,keystone";
d5e9fe84	11	model = "Texas Instruments Keystone 2 SoC";
d5e9fe84 SS	12	#address-cells = <2>;
	13	#size-cells = <2>;
	14	interrupt-parent = <&gic>;
	15
	16	aliases {
	17	serial0 = &uart0;
72f7e959 V	18	spi0 = &spi0;
	19	spi1 = &spi1;
	20	spi2 = &spi2;
d5e9fe84 SS	21	};
d5e9fe84 SS	22
d2a3ec71 NM	23	chosen { };
	24
	25	memory: memory@80000000 {
	26	device_type = "memory";
d5e9fe84 SS	27	reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
	28	};
	29
d5e9fe84	30	gic: interrupt-controller {
387720c9	31	compatible = "arm,gic-400", "arm,cortex-a15-gic";
d5e9fe84	32	#interrupt-cells = <3>;
d5e9fe84 SS	33	interrupt-controller;
d5e9fe84 SS	34	reg = <0x0 0x02561000 0x0 0x1000>,
a18b4aa2	35	<0x0 0x02562000 0x0 0x2000>,
387720c9	36	<0x0 0x02564000 0x0 0x2000>,
a18b4aa2	37	<0x0 0x02566000 0x0 0x2000>;
0ee15444 SS	38	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \|
0ee15444 SS	39	IRQ_TYPE_LEVEL_HIGH)>;
d5e9fe84 SS	40	};
	41
	42	timer {
	43	compatible = "arm,armv7-timer";
eb788f43 SS	44	interrupts =
	45	<GIC_PPI 13
	46	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	47	<GIC_PPI 14
	48	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	49	<GIC_PPI 11
	50	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	51	<GIC_PPI 10
	52	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
d5e9fe84 SS	53	};
	54
	55	pmu {
	56	compatible = "arm,cortex-a15-pmu";
eb788f43 SS	57	interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
	58	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	59	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
	60	<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	61	};
d5e9fe84 SS	62
14de48a4 VA	63	psci {
	64	compatible = "arm,psci";
	65	method = "smc";
	66	cpu_suspend = <0x84000001>;
	67	cpu_off = <0x84000002>;
	68	cpu_on = <0x84000003>;
	69	};
	70
eb08c33f	71	soc0: soc@0 {
d5e9fe84 SS	72	#address-cells = <1>;
	73	#size-cells = <1>;
	74	compatible = "ti,keystone","simple-bus";
	75	interrupt-parent = <&gic>;
	76	ranges = <0x0 0x0 0x0 0xc0000000>;
4d46596d	77	dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
d5e9fe84	78
8dccafaa	79	pllctrl: pll-controller@2310000 {
ded79beb IK	80	compatible = "ti,keystone-pllctrl", "syscon";
	81	reg = <0x02310000 0x200>;
	82	};
	83
8dccafaa	84	psc: power-sleep-controller@2350000 {
e2dd60f9 SA	85	compatible = "syscon", "simple-mfd";
	86	reg = <0x02350000 0x1000>;
	87	};
	88
8dccafaa	89	devctrl: device-state-control@2620000 {
ded79beb IK	90	compatible = "ti,keystone-devctrl", "syscon";
	91	reg = <0x02620000 0x1000>;
	92	};
	93
d5e9fe84 SS	94	rstctrl: reset-controller {
d5e9fe84 SS	95	compatible = "ti,keystone-reset";
ded79beb IK	96	ti,syscon-pll = <&pllctrl 0xe4>;
	97	ti,syscon-dev = <&devctrl 0x328>;
	98	ti,wdt-list = <0>;
d5e9fe84 SS	99	};
d5e9fe84 SS	100
feeea8f3 SS	101	/include/ "keystone-clocks.dtsi"
feeea8f3 SS	102
8dccafaa	103	uart0: serial@2530c00 {
1dd55813	104	compatible = "ti,da830-uart", "ns16550a";
d5e9fe84 SS	105	current-speed = <115200>;
	106	reg-shift = <2>;
	107	reg-io-width = <4>;
	108	reg = <0x02530c00 0x100>;
f023bd10	109	clocks = <&clkuart0>;
eb788f43	110	interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	111	};
d5e9fe84 SS	112
8dccafaa	113	uart1: serial@2531000 {
1dd55813	114	compatible = "ti,da830-uart", "ns16550a";
d5e9fe84 SS	115	current-speed = <115200>;
	116	reg-shift = <2>;
	117	reg-io-width = <4>;
	118	reg = <0x02531000 0x100>;
f023bd10	119	clocks = <&clkuart1>;
eb788f43	120	interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	121	};
d5e9fe84 SS	122
6120ac23 SS	123	i2c0: i2c@2530000 {
	124	compatible = "ti,davinci-i2c";
	125	reg = <0x02530000 0x400>;
	126	clock-frequency = <100000>;
	127	clocks = <&clki2c>;
	128	interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
	129	#address-cells = <1>;
	130	#size-cells = <0>;
6120ac23 SS	131	};
	132
	133	i2c1: i2c@2530400 {
	134	compatible = "ti,davinci-i2c";
	135	reg = <0x02530400 0x400>;
	136	clock-frequency = <100000>;
	137	clocks = <&clki2c>;
	138	interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
3953505a GS	139	#address-cells = <1>;
3953505a GS	140	#size-cells = <0>;
6120ac23 SS	141	};
	142
	143	i2c2: i2c@2530800 {
	144	compatible = "ti,davinci-i2c";
	145	reg = <0x02530800 0x400>;
	146	clock-frequency = <100000>;
	147	clocks = <&clki2c>;
	148	interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
3953505a GS	149	#address-cells = <1>;
3953505a GS	150	#size-cells = <0>;
6120ac23	151	};
b3bd6c59 SS	152
b3bd6c59 SS	153	spi0: spi@21000400 {
1a344e9b	154	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	155	reg = <0x21000400 0x200>;
	156	num-cs = <4>;
	157	ti,davinci-spi-intr-line = <0>;
	158	interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
	159	clocks = <&clkspi>;
509046a7 GS	160	#address-cells = <1>;
509046a7 GS	161	#size-cells = <0>;
b3bd6c59 SS	162	};
	163
	164	spi1: spi@21000600 {
1a344e9b	165	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	166	reg = <0x21000600 0x200>;
	167	num-cs = <4>;
	168	ti,davinci-spi-intr-line = <0>;
	169	interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
	170	clocks = <&clkspi>;
509046a7 GS	171	#address-cells = <1>;
509046a7 GS	172	#size-cells = <0>;
b3bd6c59 SS	173	};
	174
	175	spi2: spi@21000800 {
1a344e9b	176	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	177	reg = <0x21000800 0x200>;
	178	num-cs = <4>;
	179	ti,davinci-spi-intr-line = <0>;
	180	interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
	181	clocks = <&clkspi>;
509046a7 GS	182	#address-cells = <1>;
509046a7 GS	183	#size-cells = <0>;
b3bd6c59	184	};
08c36762 WK	185
	186	usb_phy: usb_phy@2620738 {
	187	compatible = "ti,keystone-usbphy";
	188	#address-cells = <1>;
	189	#size-cells = <1>;
cfb198ce	190	reg = <0x2620738 24>;
08c36762 WK	191	status = "disabled";
08c36762 WK	192	};
73207956	193
64497844	194	keystone_usb0: usb@2680000 {
73207956 WK	195	compatible = "ti,keystone-dwc3";
	196	#address-cells = <1>;
	197	#size-cells = <1>;
	198	reg = <0x2680000 0x10000>;
	199	clocks = <&clkusb>;
	200	clock-names = "usb";
	201	interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
	202	ranges;
86156978 SS	203	dma-coherent;
86156978 SS	204	dma-ranges;
73207956 WK	205	status = "disabled";
73207956 WK	206
64497844	207	usb0: dwc3@2690000 {
73207956 WK	208	compatible = "synopsys,dwc3";
	209	reg = <0x2690000 0x70000>;
	210	interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
	211	usb-phy = <&usb_phy>, <&usb_phy>;
	212	};
	213	};
20d89313	214
8dccafaa	215	wdt: wdt@22f0080 {
20d89313 IK	216	compatible = "ti,keystone-wdt","ti,davinci-wdt";
	217	reg = <0x022f0080 0x80>;
	218	clocks = <&clkwdtimer0>;
	219	};
2b4f76b6 IK	220
	221	clock_event: timer@22f0000 {
	222	compatible = "ti,keystone-timer";
	223	reg = <0x022f0000 0x80>;
	224	interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
	225	clocks = <&clktimer15>;
	226	};
970c2256 GS	227
	228	gpio0: gpio@260bf00 {
	229	compatible = "ti,keystone-gpio";
	230	reg = <0x0260bf00 0x100>;
	231	gpio-controller;
	232	#gpio-cells = <2>;
	233	/* HW Interrupts mapped to GPIO pins */
	234	interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
	235	<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
	236	<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
	237	<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
	238	<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
	239	<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
	240	<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
	241	<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
	242	<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
	243	<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
	244	<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
	245	<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
	246	<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
	247	<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
	248	<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
	249	<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
	250	<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
	251	<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
	252	<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
	253	<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
	254	<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
	255	<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
	256	<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
	257	<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
	258	<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
	259	<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
	260	<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
	261	<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
	262	<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
	263	<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
	264	<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
	265	<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
	266	clocks = <&clkgpio>;
	267	clock-names = "gpio";
	268	ti,ngpio = <32>;
	269	ti,davinci-gpio-unbanked = <32>;
	270	};
82c04f71 IK	271
	272	aemif: aemif@21000A00 {
	273	compatible = "ti,keystone-aemif", "ti,davinci-aemif";
	274	#address-cells = <2>;
	275	#size-cells = <1>;
	276	clocks = <&clkaemif>;
	277	clock-names = "aemif";
	278	clock-ranges;
	279
	280	reg = <0x21000A00 0x00000100>;
	281	ranges = <0 0 0x30000000 0x10000000
	282	1 0 0x21000A00 0x00000100>;
	283	};
979c36c8	284
a392d42d GS	285	kirq0: keystone_irq@26202a0 {
	286	compatible = "ti,keystone-irq";
	287	interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
	288	interrupt-controller;
	289	#interrupt-cells = <1>;
	290	ti,syscon-dev = <&devctrl 0x2a0>;
	291	};
bed80507	292
8b4769cc	293	pcie0: pcie@21800000 {
bed80507 MK	294	compatible = "ti,keystone-pcie", "snps,dw-pcie";
	295	clocks = <&clkpcie>;
	296	clock-names = "pcie";
	297	#address-cells = <3>;
	298	#size-cells = <2>;
	299	reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
59e13aac MK	300	ranges = <0x82000000 0 0x50000000 0x50000000
59e13aac MK	301	0 0x10000000>;
bed80507	302
9dd4f28f	303	status = "disabled";
bed80507 MK	304	device_type = "pci";
bed80507 MK	305	num-lanes = <2>;
59e13aac	306	bus-range = <0x00 0xff>;
bed80507	307
a9e5b20d MK	308	/* error interrupt */
a9e5b20d MK	309	interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
bed80507 MK	310	#interrupt-cells = <1>;
	311	interrupt-map-mask = <0 0 0 7>;
	312	interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
	313	<0 0 0 2 &pcie_intc0 1>, /* INT B */
	314	<0 0 0 3 &pcie_intc0 2>, /* INT C */
	315	<0 0 0 4 &pcie_intc0 3>; /* INT D */
	316
	317	pcie_msi_intc0: msi-interrupt-controller {
	318	interrupt-controller;
	319	#interrupt-cells = <1>;
	320	interrupt-parent = <&gic>;
	321	interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
	322	<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
	323	<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
	324	<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
	325	<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
	326	<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
	327	<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
	328	<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
	329	};
	330
	331	pcie_intc0: legacy-interrupt-controller {
	332	interrupt-controller;
	333	#interrupt-cells = <1>;
	334	interrupt-parent = <&gic>;
	335	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
	336	<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
	337	<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
	338	<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
	339	};
	340	};
d5e9fe84 SS	341	};
d5e9fe84 SS	342	};