[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / keystone.dtsi

/*
 * Copyright 2013 Texas Instruments, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,keystone";
	model = "Texas Instruments Keystone 2 SoC";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	aliases {
		serial0	= &uart0;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
	};

	memory {
		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
	};

	gic: interrupt-controller {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x02561000 0x0 0x1000>,
		      <0x0 0x02562000 0x0 0x2000>,
		      <0x0 0x02564000 0x0 0x2000>,
		      <0x0 0x02566000 0x0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
				IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts =
			<GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
	};

	psci {
		compatible	= "arm,psci";
		method		= "smc";
		cpu_suspend	= <0x84000001>;
		cpu_off		= <0x84000002>;
		cpu_on		= <0x84000003>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "ti,keystone","simple-bus";
		interrupt-parent = <&gic>;
		ranges = <0x0 0x0 0x0 0xc0000000>;
		dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;

		pllctrl: pll-controller@02310000 {
			compatible = "ti,keystone-pllctrl", "syscon";
			reg = <0x02310000 0x200>;
		};

		psc: power-sleep-controller@02350000 {
			compatible = "syscon", "simple-mfd";
			reg = <0x02350000 0x1000>;
		};

		devctrl: device-state-control@02620000 {
			compatible = "ti,keystone-devctrl", "syscon";
			reg = <0x02620000 0x1000>;
		};

		rstctrl: reset-controller {
			compatible = "ti,keystone-reset";
			ti,syscon-pll = <&pllctrl 0xe4>;
			ti,syscon-dev = <&devctrl 0x328>;
			ti,wdt-list = <0>;
		};

		/include/ "keystone-clocks.dtsi"

		uart0: serial@02530c00 {
			compatible = "ti,da830-uart", "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02530c00 0x100>;
			clocks	= <&clkuart0>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
		};

		uart1:	serial@02531000 {
			compatible = "ti,da830-uart", "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02531000 0x100>;
			clocks	= <&clkuart1>;
			interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
		};

		i2c0: i2c@2530000 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530000 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@2530400 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530400 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@2530800 {
			compatible = "ti,davinci-i2c";
			reg = <0x02530800 0x400>;
			clock-frequency = <100000>;
			clocks = <&clki2c>;
			interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi0: spi@21000400 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000400 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@21000600 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000600 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi2: spi@21000800 {
			compatible = "ti,keystone-spi", "ti,dm6441-spi";
			reg = <0x21000800 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkspi>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		usb_phy: usb_phy@2620738 {
			compatible = "ti,keystone-usbphy";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2620738 24>;
			status = "disabled";
		};

		keystone_usb0: usb@2680000 {
			compatible = "ti,keystone-dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2680000 0x10000>;
			clocks = <&clkusb>;
			clock-names = "usb";
			interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
			ranges;
			dma-coherent;
			dma-ranges;
			status = "disabled";

			usb0: dwc3@2690000 {
				compatible = "synopsys,dwc3";
				reg = <0x2690000 0x70000>;
				interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
				usb-phy = <&usb_phy>, <&usb_phy>;
			};
		};

		wdt: wdt@022f0080 {
			compatible = "ti,keystone-wdt","ti,davinci-wdt";
			reg = <0x022f0080 0x80>;
			clocks = <&clkwdtimer0>;
		};

		clock_event: timer@22f0000 {
			compatible = "ti,keystone-timer";
			reg = <0x022f0000 0x80>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clktimer15>;
		};

		gpio0: gpio@260bf00 {
			compatible = "ti,keystone-gpio";
			reg = <0x0260bf00 0x100>;
			gpio-controller;
			#gpio-cells = <2>;
			/* HW Interrupts mapped to GPIO pins */
			interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
			clocks = <&clkgpio>;
			clock-names = "gpio";
			ti,ngpio = <32>;
			ti,davinci-gpio-unbanked = <32>;
		};

		aemif: aemif@21000A00 {
			compatible = "ti,keystone-aemif", "ti,davinci-aemif";
			#address-cells = <2>;
			#size-cells = <1>;
			clocks = <&clkaemif>;
			clock-names = "aemif";
			clock-ranges;

			reg = <0x21000A00 0x00000100>;
			ranges = <0 0 0x30000000 0x10000000
				  1 0 0x21000A00 0x00000100>;
		};

		kirq0: keystone_irq@26202a0 {
			compatible = "ti,keystone-irq";
			interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,syscon-dev = <&devctrl 0x2a0>;
		};

		pcie0: pcie@21800000 {
			compatible = "ti,keystone-pcie", "snps,dw-pcie";
			clocks = <&clkpcie>;
			clock-names = "pcie";
			#address-cells = <3>;
			#size-cells = <2>;
			reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
			ranges = <0x82000000 0 0x50000000 0x50000000
				  0 0x10000000>;

			status = "disabled";
			device_type = "pci";
			num-lanes = <2>;
			bus-range = <0x00 0xff>;

			/* error interrupt */
			interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
					<0 0 0 2 &pcie_intc0 1>, /* INT B */
					<0 0 0 3 &pcie_intc0 2>, /* INT C */
					<0 0 0 4 &pcie_intc0 3>; /* INT D */

			pcie_msi_intc0: msi-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
			};

			pcie_intc0: legacy-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
			};
		};
	};
};
Commit	Line	Data
d5e9fe84 SS	1	/*
	2	* Copyright 2013 Texas Instruments, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
eb788f43	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
970c2256	10	#include <dt-bindings/gpio/gpio.h>
eb788f43	11
226d1c5b	12	#include "skeleton.dtsi"
d5e9fe84 SS	13
d5e9fe84 SS	14	/ {
91dca0f0	15	compatible = "ti,keystone";
d5e9fe84	16	model = "Texas Instruments Keystone 2 SoC";
d5e9fe84 SS	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19	interrupt-parent = <&gic>;
	20
	21	aliases {
	22	serial0 = &uart0;
72f7e959 V	23	spi0 = &spi0;
	24	spi1 = &spi1;
	25	spi2 = &spi2;
d5e9fe84 SS	26	};
	27
	28	memory {
	29	reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
	30	};
	31
d5e9fe84	32	gic: interrupt-controller {
387720c9	33	compatible = "arm,gic-400", "arm,cortex-a15-gic";
d5e9fe84	34	#interrupt-cells = <3>;
d5e9fe84 SS	35	interrupt-controller;
d5e9fe84 SS	36	reg = <0x0 0x02561000 0x0 0x1000>,
a18b4aa2	37	<0x0 0x02562000 0x0 0x2000>,
387720c9	38	<0x0 0x02564000 0x0 0x2000>,
a18b4aa2	39	<0x0 0x02566000 0x0 0x2000>;
0ee15444 SS	40	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \|
0ee15444 SS	41	IRQ_TYPE_LEVEL_HIGH)>;
d5e9fe84 SS	42	};
	43
	44	timer {
	45	compatible = "arm,armv7-timer";
eb788f43 SS	46	interrupts =
	47	<GIC_PPI 13
	48	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	49	<GIC_PPI 14
	50	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	51	<GIC_PPI 11
	52	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	53	<GIC_PPI 10
	54	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
d5e9fe84 SS	55	};
	56
	57	pmu {
	58	compatible = "arm,cortex-a15-pmu";
eb788f43 SS	59	interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
	60	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	61	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
	62	<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	63	};
d5e9fe84 SS	64
14de48a4 VA	65	psci {
	66	compatible = "arm,psci";
	67	method = "smc";
	68	cpu_suspend = <0x84000001>;
	69	cpu_off = <0x84000002>;
	70	cpu_on = <0x84000003>;
	71	};
	72
d5e9fe84 SS	73	soc {
	74	#address-cells = <1>;
	75	#size-cells = <1>;
	76	compatible = "ti,keystone","simple-bus";
	77	interrupt-parent = <&gic>;
	78	ranges = <0x0 0x0 0x0 0xc0000000>;
4d46596d	79	dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
d5e9fe84	80
ded79beb IK	81	pllctrl: pll-controller@02310000 {
	82	compatible = "ti,keystone-pllctrl", "syscon";
	83	reg = <0x02310000 0x200>;
	84	};
	85
e2dd60f9 SA	86	psc: power-sleep-controller@02350000 {
	87	compatible = "syscon", "simple-mfd";
	88	reg = <0x02350000 0x1000>;
	89	};
	90
ded79beb IK	91	devctrl: device-state-control@02620000 {
	92	compatible = "ti,keystone-devctrl", "syscon";
	93	reg = <0x02620000 0x1000>;
	94	};
	95
d5e9fe84 SS	96	rstctrl: reset-controller {
d5e9fe84 SS	97	compatible = "ti,keystone-reset";
ded79beb IK	98	ti,syscon-pll = <&pllctrl 0xe4>;
	99	ti,syscon-dev = <&devctrl 0x328>;
	100	ti,wdt-list = <0>;
d5e9fe84 SS	101	};
d5e9fe84 SS	102
feeea8f3 SS	103	/include/ "keystone-clocks.dtsi"
feeea8f3 SS	104
d5e9fe84	105	uart0: serial@02530c00 {
1dd55813	106	compatible = "ti,da830-uart", "ns16550a";
d5e9fe84 SS	107	current-speed = <115200>;
	108	reg-shift = <2>;
	109	reg-io-width = <4>;
	110	reg = <0x02530c00 0x100>;
f023bd10	111	clocks = <&clkuart0>;
eb788f43	112	interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	113	};
	114
	115	uart1: serial@02531000 {
1dd55813	116	compatible = "ti,da830-uart", "ns16550a";
d5e9fe84 SS	117	current-speed = <115200>;
	118	reg-shift = <2>;
	119	reg-io-width = <4>;
	120	reg = <0x02531000 0x100>;
f023bd10	121	clocks = <&clkuart1>;
eb788f43	122	interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
d5e9fe84 SS	123	};
d5e9fe84 SS	124
6120ac23 SS	125	i2c0: i2c@2530000 {
	126	compatible = "ti,davinci-i2c";
	127	reg = <0x02530000 0x400>;
	128	clock-frequency = <100000>;
	129	clocks = <&clki2c>;
	130	interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
	131	#address-cells = <1>;
	132	#size-cells = <0>;
6120ac23 SS	133	};
	134
	135	i2c1: i2c@2530400 {
	136	compatible = "ti,davinci-i2c";
	137	reg = <0x02530400 0x400>;
	138	clock-frequency = <100000>;
	139	clocks = <&clki2c>;
	140	interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
3953505a GS	141	#address-cells = <1>;
3953505a GS	142	#size-cells = <0>;
6120ac23 SS	143	};
	144
	145	i2c2: i2c@2530800 {
	146	compatible = "ti,davinci-i2c";
	147	reg = <0x02530800 0x400>;
	148	clock-frequency = <100000>;
	149	clocks = <&clki2c>;
	150	interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
3953505a GS	151	#address-cells = <1>;
3953505a GS	152	#size-cells = <0>;
6120ac23	153	};
b3bd6c59 SS	154
b3bd6c59 SS	155	spi0: spi@21000400 {
1a344e9b	156	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	157	reg = <0x21000400 0x200>;
	158	num-cs = <4>;
	159	ti,davinci-spi-intr-line = <0>;
	160	interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
	161	clocks = <&clkspi>;
509046a7 GS	162	#address-cells = <1>;
509046a7 GS	163	#size-cells = <0>;
b3bd6c59 SS	164	};
	165
	166	spi1: spi@21000600 {
1a344e9b	167	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	168	reg = <0x21000600 0x200>;
	169	num-cs = <4>;
	170	ti,davinci-spi-intr-line = <0>;
	171	interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
	172	clocks = <&clkspi>;
509046a7 GS	173	#address-cells = <1>;
509046a7 GS	174	#size-cells = <0>;
b3bd6c59 SS	175	};
	176
	177	spi2: spi@21000800 {
1a344e9b	178	compatible = "ti,keystone-spi", "ti,dm6441-spi";
b3bd6c59 SS	179	reg = <0x21000800 0x200>;
	180	num-cs = <4>;
	181	ti,davinci-spi-intr-line = <0>;
	182	interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
	183	clocks = <&clkspi>;
509046a7 GS	184	#address-cells = <1>;
509046a7 GS	185	#size-cells = <0>;
b3bd6c59	186	};
08c36762 WK	187
	188	usb_phy: usb_phy@2620738 {
	189	compatible = "ti,keystone-usbphy";
	190	#address-cells = <1>;
	191	#size-cells = <1>;
cfb198ce	192	reg = <0x2620738 24>;
08c36762 WK	193	status = "disabled";
08c36762 WK	194	};
73207956	195
64497844	196	keystone_usb0: usb@2680000 {
73207956 WK	197	compatible = "ti,keystone-dwc3";
	198	#address-cells = <1>;
	199	#size-cells = <1>;
	200	reg = <0x2680000 0x10000>;
	201	clocks = <&clkusb>;
	202	clock-names = "usb";
	203	interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
	204	ranges;
86156978 SS	205	dma-coherent;
86156978 SS	206	dma-ranges;
73207956 WK	207	status = "disabled";
73207956 WK	208
64497844	209	usb0: dwc3@2690000 {
73207956 WK	210	compatible = "synopsys,dwc3";
	211	reg = <0x2690000 0x70000>;
	212	interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
	213	usb-phy = <&usb_phy>, <&usb_phy>;
	214	};
	215	};
20d89313 IK	216
	217	wdt: wdt@022f0080 {
	218	compatible = "ti,keystone-wdt","ti,davinci-wdt";
	219	reg = <0x022f0080 0x80>;
	220	clocks = <&clkwdtimer0>;
	221	};
2b4f76b6 IK	222
	223	clock_event: timer@22f0000 {
	224	compatible = "ti,keystone-timer";
	225	reg = <0x022f0000 0x80>;
	226	interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
	227	clocks = <&clktimer15>;
	228	};
970c2256 GS	229
	230	gpio0: gpio@260bf00 {
	231	compatible = "ti,keystone-gpio";
	232	reg = <0x0260bf00 0x100>;
	233	gpio-controller;
	234	#gpio-cells = <2>;
	235	/* HW Interrupts mapped to GPIO pins */
	236	interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
	237	<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
	238	<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
	239	<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
	240	<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
	241	<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
	242	<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
	243	<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
	244	<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
	245	<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
	246	<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
	247	<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
	248	<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
	249	<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
	250	<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
	251	<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
	252	<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
	253	<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
	254	<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
	255	<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
	256	<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
	257	<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
	258	<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
	259	<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
	260	<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
	261	<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
	262	<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
	263	<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
	264	<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
	265	<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
	266	<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
	267	<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
	268	clocks = <&clkgpio>;
	269	clock-names = "gpio";
	270	ti,ngpio = <32>;
	271	ti,davinci-gpio-unbanked = <32>;
	272	};
82c04f71 IK	273
	274	aemif: aemif@21000A00 {
	275	compatible = "ti,keystone-aemif", "ti,davinci-aemif";
	276	#address-cells = <2>;
	277	#size-cells = <1>;
	278	clocks = <&clkaemif>;
	279	clock-names = "aemif";
	280	clock-ranges;
	281
	282	reg = <0x21000A00 0x00000100>;
	283	ranges = <0 0 0x30000000 0x10000000
	284	1 0 0x21000A00 0x00000100>;
	285	};
979c36c8	286
a392d42d GS	287	kirq0: keystone_irq@26202a0 {
	288	compatible = "ti,keystone-irq";
	289	interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
	290	interrupt-controller;
	291	#interrupt-cells = <1>;
	292	ti,syscon-dev = <&devctrl 0x2a0>;
	293	};
bed80507	294
8b4769cc	295	pcie0: pcie@21800000 {
bed80507 MK	296	compatible = "ti,keystone-pcie", "snps,dw-pcie";
	297	clocks = <&clkpcie>;
	298	clock-names = "pcie";
	299	#address-cells = <3>;
	300	#size-cells = <2>;
	301	reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
59e13aac MK	302	ranges = <0x82000000 0 0x50000000 0x50000000
59e13aac MK	303	0 0x10000000>;
bed80507	304
9dd4f28f	305	status = "disabled";
bed80507 MK	306	device_type = "pci";
bed80507 MK	307	num-lanes = <2>;
59e13aac	308	bus-range = <0x00 0xff>;
bed80507	309
a9e5b20d MK	310	/* error interrupt */
a9e5b20d MK	311	interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
bed80507 MK	312	#interrupt-cells = <1>;
	313	interrupt-map-mask = <0 0 0 7>;
	314	interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
	315	<0 0 0 2 &pcie_intc0 1>, /* INT B */
	316	<0 0 0 3 &pcie_intc0 2>, /* INT C */
	317	<0 0 0 4 &pcie_intc0 3>; /* INT D */
	318
	319	pcie_msi_intc0: msi-interrupt-controller {
	320	interrupt-controller;
	321	#interrupt-cells = <1>;
	322	interrupt-parent = <&gic>;
	323	interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
	324	<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
	325	<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
	326	<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
	327	<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
	328	<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
	329	<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
	330	<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
	331	};
	332
	333	pcie_intc0: legacy-interrupt-controller {
	334	interrupt-controller;
	335	#interrupt-cells = <1>;
	336	interrupt-parent = <&gic>;
	337	interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
	338	<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
	339	<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
	340	<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
	341	};
	342	};
d5e9fe84 SS	343	};
d5e9fe84 SS	344	};