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e7822263 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c134043e BV |
2 | /* |
3 | * kirkwood-viper.dts - Device Tree file for Linksys viper (E4200v2 / EA4500) | |
4 | * | |
5 | * (c) 2013 Jonas Gorski <jogo@openwrt.org> | |
6 | * (c) 2013 Deutsche Telekom Innovation Laboratories | |
7 | * (c) 2014 Luka Perkov <luka@openwrt.org> | |
8 | * (c) 2014 Randy C. Will <randall.will@gmail.com> | |
9 | * | |
c134043e BV |
10 | */ |
11 | ||
12 | /dts-v1/; | |
13 | ||
14 | #include "kirkwood.dtsi" | |
15 | #include "kirkwood-6282.dtsi" | |
16 | ||
17 | / { | |
18 | model = "Linksys Viper (E4200v2 / EA4500)"; | |
19 | compatible = "linksys,viper", "marvell,kirkwood-88f6282", "marvell,kirkwood"; | |
20 | ||
21 | memory { | |
22 | device_type = "memory"; | |
23 | reg = <0x00000000 0x8000000>; | |
24 | }; | |
25 | ||
26 | aliases { | |
27 | serial0 = &uart0; | |
28 | }; | |
29 | ||
30 | chosen { | |
31 | stdout-path = "serial0:115200n8"; | |
32 | }; | |
33 | ||
34 | gpio_keys { | |
35 | compatible = "gpio-keys"; | |
36 | #address-cells = <1>; | |
37 | #size-cells = <0>; | |
38 | pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; | |
39 | pinctrl-names = "default"; | |
40 | ||
41 | wps { | |
42 | label = "WPS Button"; | |
43 | linux,code = <KEY_WPS_BUTTON>; | |
44 | gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; | |
45 | }; | |
46 | ||
47 | reset { | |
48 | label = "Reset Button"; | |
49 | linux,code = <KEY_RESTART>; | |
50 | gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; | |
51 | }; | |
52 | }; | |
53 | ||
54 | gpio-leds { | |
55 | compatible = "gpio-leds"; | |
56 | pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; | |
57 | pinctrl-names = "default"; | |
58 | ||
59 | white-health { | |
60 | label = "viper:white:health"; | |
61 | gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; | |
62 | }; | |
63 | ||
64 | white-pulse { | |
65 | label = "viper:white:pulse"; | |
66 | gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; | |
67 | }; | |
68 | }; | |
69 | ||
70 | dsa { | |
69e8e6ae FF |
71 | status = "disabled"; |
72 | ||
c134043e BV |
73 | compatible = "marvell,dsa"; |
74 | #address-cells = <2>; | |
75 | #size-cells = <0>; | |
76 | ||
77 | dsa,ethernet = <ð0port>; | |
78 | dsa,mii-bus = <&mdio>; | |
79 | ||
80 | switch@16,0 { | |
81 | #address-cells = <1>; | |
82 | #size-cells = <0>; | |
83 | reg = <16 0>; /* MDIO address 16, switch 0 in tree */ | |
84 | ||
85 | port@0 { | |
86 | reg = <0>; | |
87 | label = "ethernet1"; | |
88 | }; | |
89 | ||
90 | port@1 { | |
91 | reg = <1>; | |
92 | label = "ethernet2"; | |
93 | }; | |
94 | ||
95 | port@2 { | |
96 | reg = <2>; | |
97 | label = "ethernet3"; | |
98 | }; | |
99 | ||
100 | port@3 { | |
101 | reg = <3>; | |
102 | label = "ethernet4"; | |
103 | }; | |
104 | ||
105 | port@4 { | |
106 | reg = <4>; | |
107 | label = "internet"; | |
108 | }; | |
109 | ||
110 | port@5 { | |
111 | reg = <5>; | |
112 | label = "cpu"; | |
113 | }; | |
114 | }; | |
115 | }; | |
116 | }; | |
117 | ||
118 | &pinctrl { | |
119 | pmx_led_white_health: pmx-led-white-health { | |
120 | marvell,pins = "mpp7"; | |
121 | marvell,function = "gpo"; | |
122 | }; | |
123 | pmx_led_white_pulse: pmx-led-white-pulse { | |
124 | marvell,pins = "mpp14"; | |
125 | marvell,function = "gpio"; | |
126 | }; | |
127 | pmx_btn_wps: pmx-btn-wps { | |
128 | marvell,pins = "mpp47"; | |
129 | marvell,function = "gpio"; | |
130 | }; | |
131 | pmx_btn_reset: pmx-btn-reset { | |
132 | marvell,pins = "mpp48"; | |
133 | marvell,function = "gpio"; | |
134 | }; | |
135 | }; | |
136 | ||
137 | &nand { | |
138 | status = "okay"; | |
139 | pinctrl-0 = <&pmx_nand>; | |
140 | pinctrl-names = "default"; | |
141 | ||
142 | partitions { | |
143 | compatible = "fixed-partitions"; | |
144 | #address-cells = <1>; | |
145 | #size-cells = <1>; | |
146 | ||
147 | partition@0 { | |
148 | label = "u-boot"; | |
149 | reg = <0x0 0x80000>; | |
150 | read-only; | |
151 | }; | |
152 | ||
153 | partition@80000 { | |
154 | label = "u_env"; | |
155 | reg = <0x80000 0x20000>; | |
156 | }; | |
157 | ||
cea96bf1 | 158 | partition@a0000 { |
c134043e BV |
159 | label = "s_env"; |
160 | reg = <0xA0000 0x20000>; | |
161 | }; | |
162 | ||
163 | partition@200000 { | |
164 | label = "kernel"; | |
165 | reg = <0x200000 0x2A0000>; | |
166 | }; | |
167 | ||
cea96bf1 | 168 | partition@4a0000 { |
c134043e BV |
169 | label = "rootfs"; |
170 | reg = <0x4A0000 0x1760000>; | |
171 | }; | |
172 | ||
cea96bf1 | 173 | partition@1c00000 { |
c134043e BV |
174 | label = "alt_kernel"; |
175 | reg = <0x1C00000 0x2A0000>; | |
176 | }; | |
177 | ||
cea96bf1 | 178 | partition@1ea0000 { |
c134043e BV |
179 | label = "alt_rootfs"; |
180 | reg = <0x1EA0000 0x1760000>; | |
181 | }; | |
182 | ||
183 | partition@3600000 { | |
184 | label = "syscfg"; | |
185 | reg = <0x3600000 0x4A00000>; | |
186 | }; | |
187 | ||
cea96bf1 | 188 | partition@c0000 { |
c134043e BV |
189 | label = "unused"; |
190 | reg = <0xC0000 0x140000>; | |
191 | }; | |
192 | ||
193 | }; | |
194 | }; | |
195 | ||
196 | &pciec { | |
197 | status = "okay"; | |
198 | }; | |
199 | ||
200 | &pcie0 { | |
201 | status = "okay"; | |
202 | }; | |
203 | ||
204 | &pcie1 { | |
205 | status = "okay"; | |
206 | }; | |
207 | ||
208 | &mdio { | |
209 | status = "okay"; | |
69e8e6ae FF |
210 | |
211 | switch@10 { | |
212 | compatible = "marvell,mv88e6085"; | |
213 | #address-cells = <1>; | |
214 | #size-cells = <0>; | |
215 | reg = <16>; | |
216 | ||
217 | ports { | |
218 | #address-cells = <1>; | |
219 | #size-cells = <0>; | |
220 | ||
221 | port@0 { | |
222 | reg = <0>; | |
223 | label = "ethernet1"; | |
224 | }; | |
225 | ||
226 | port@1 { | |
227 | reg = <1>; | |
228 | label = "ethernet2"; | |
229 | }; | |
230 | ||
231 | port@2 { | |
232 | reg = <2>; | |
233 | label = "ethernet3"; | |
234 | }; | |
235 | ||
236 | port@3 { | |
237 | reg = <3>; | |
238 | label = "ethernet4"; | |
239 | }; | |
240 | ||
241 | port@4 { | |
242 | reg = <4>; | |
243 | label = "internet"; | |
244 | }; | |
245 | ||
246 | port@5 { | |
247 | reg = <5>; | |
248 | label = "cpu"; | |
249 | ethernet = <ð0port>; | |
250 | fixed-link { | |
251 | speed = <1000>; | |
252 | full-duplex; | |
253 | }; | |
254 | }; | |
255 | }; | |
256 | }; | |
c134043e BV |
257 | }; |
258 | ||
259 | &uart0 { | |
260 | status = "okay"; | |
261 | }; | |
262 | ||
263 | /* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set | |
264 | * fixed speed and duplex. | |
265 | */ | |
266 | ð0 { | |
267 | status = "okay"; | |
268 | ethernet0-port@0 { | |
269 | speed = <1000>; | |
270 | duplex = <1>; | |
271 | }; | |
272 | }; | |
273 | ||
274 | /* eth1 is connected to the switch at port 6. However DSA only supports a | |
275 | * single CPU port. So leave this port disabled to avoid confusion. | |
276 | */ | |
277 | ð1 { | |
278 | status = "disabled"; | |
279 | }; | |
280 | ||
281 | /* There is no battery on the board, so the RTC does not keep | |
282 | * time when there is no power, making it useless. | |
283 | */ | |
284 | &rtc { | |
285 | status = "disabled"; | |
286 | }; | |
287 |