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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
b6e30a47 LW |
2 | /* |
3 | * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4 | |
4 | * inspired by the board files made by Kevin Mihelich for ArchLinux, | |
5 | * and their DTS file. | |
6 | * | |
7 | * Copyright (C) 2015 Linus Walleij <linus.walleij@linaro.org> | |
8 | */ | |
9 | ||
10 | /dts-v1/; | |
11 | ||
12 | #include "kirkwood.dtsi" | |
13 | #include "kirkwood-6192.dtsi" | |
14 | #include <dt-bindings/input/linux-event-codes.h> | |
15 | ||
16 | / { | |
17 | model = "Cloud Engines PogoPlug Series 4"; | |
18 | compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", | |
19 | "marvell,kirkwood"; | |
20 | ||
21 | memory { | |
22 | device_type = "memory"; | |
23 | reg = <0x00000000 0x08000000>; | |
24 | }; | |
25 | ||
26 | chosen { | |
27 | stdout-path = "uart0:115200n8"; | |
28 | }; | |
29 | ||
30 | gpio_keys { | |
31 | compatible = "gpio-keys"; | |
32 | #address-cells = <1>; | |
33 | #size-cells = <0>; | |
34 | pinctrl-0 = <&pmx_button_eject>; | |
35 | pinctrl-names = "default"; | |
36 | ||
395c755f | 37 | eject { |
5beaf4d7 | 38 | debounce-interval = <50>; |
b6e30a47 LW |
39 | wakeup-source; |
40 | linux,code = <KEY_EJECTCD>; | |
41 | label = "Eject Button"; | |
42 | gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; | |
43 | }; | |
44 | }; | |
45 | ||
46 | gpio-leds { | |
47 | compatible = "gpio-leds"; | |
48 | pinctrl-0 = <&pmx_led_green &pmx_led_red>; | |
49 | pinctrl-names = "default"; | |
50 | ||
51 | health { | |
52 | label = "pogoplugv4:green:health"; | |
53 | gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; | |
54 | default-state = "on"; | |
55 | }; | |
56 | fault { | |
57 | label = "pogoplugv4:red:fault"; | |
58 | gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; | |
59 | }; | |
60 | }; | |
61 | }; | |
62 | ||
63 | &pinctrl { | |
64 | pmx_sata0: pmx-sata0 { | |
65 | marvell,pins = "mpp21"; | |
66 | marvell,function = "sata0"; | |
67 | }; | |
68 | ||
69 | pmx_sata1: pmx-sata1 { | |
70 | marvell,pins = "mpp20"; | |
71 | marvell,function = "sata1"; | |
72 | }; | |
73 | ||
74 | pmx_sdio_cd: pmx-sdio-cd { | |
75 | marvell,pins = "mpp27"; | |
76 | marvell,function = "gpio"; | |
77 | }; | |
78 | ||
79 | pmx_sdio_wp: pmx-sdio-wp { | |
80 | marvell,pins = "mpp28"; | |
81 | marvell,function = "gpio"; | |
82 | }; | |
83 | ||
84 | pmx_button_eject: pmx-button-eject { | |
85 | marvell,pins = "mpp29"; | |
86 | marvell,function = "gpio"; | |
87 | }; | |
88 | ||
89 | pmx_led_green: pmx-led-green { | |
90 | marvell,pins = "mpp22"; | |
91 | marvell,function = "gpio"; | |
92 | }; | |
93 | ||
94 | pmx_led_red: pmx-led-red { | |
95 | marvell,pins = "mpp24"; | |
96 | marvell,function = "gpio"; | |
97 | }; | |
98 | }; | |
99 | ||
100 | &uart0 { | |
101 | status = "okay"; | |
102 | }; | |
103 | ||
104 | /* | |
105 | * This PCIE controller has a USB 3.0 XHCI controller at 1,0 | |
106 | */ | |
107 | &pciec { | |
108 | status = "okay"; | |
109 | }; | |
110 | ||
111 | &pcie0 { | |
112 | status = "okay"; | |
113 | }; | |
114 | ||
115 | &sata { | |
116 | status = "okay"; | |
117 | pinctrl-0 = <&pmx_sata0 &pmx_sata1>; | |
118 | pinctrl-names = "default"; | |
119 | nr-ports = <1>; | |
120 | }; | |
121 | ||
122 | &sdio { | |
123 | status = "okay"; | |
124 | pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; | |
125 | pinctrl-names = "default"; | |
126 | cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; | |
127 | wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; | |
128 | }; | |
129 | ||
130 | &nand { | |
131 | /* 128 MiB of NAND flash */ | |
132 | chip-delay = <40>; | |
133 | status = "okay"; | |
134 | partitions { | |
84d92dd3 | 135 | compatible = "fixed-partitions"; |
b6e30a47 LW |
136 | #address-cells = <1>; |
137 | #size-cells = <1>; | |
138 | ||
139 | partition@0 { | |
140 | label = "u-boot"; | |
141 | reg = <0x00000000 0x200000>; | |
142 | read-only; | |
143 | }; | |
144 | ||
145 | partition@200000 { | |
146 | label = "uImage"; | |
147 | reg = <0x00200000 0x300000>; | |
148 | }; | |
149 | ||
150 | partition@500000 { | |
151 | label = "uImage2"; | |
152 | reg = <0x00500000 0x300000>; | |
153 | }; | |
154 | ||
155 | partition@800000 { | |
156 | label = "failsafe"; | |
157 | reg = <0x00800000 0x800000>; | |
158 | }; | |
159 | ||
160 | partition@1000000 { | |
161 | label = "root"; | |
162 | reg = <0x01000000 0x7000000>; | |
163 | }; | |
164 | }; | |
165 | }; | |
166 | ||
167 | &mdio { | |
168 | status = "okay"; | |
169 | ||
170 | ethphy0: ethernet-phy@0 { | |
171 | reg = <0>; | |
172 | }; | |
173 | }; | |
174 | ||
175 | ð0 { | |
176 | status = "okay"; | |
177 | ethernet0-port@0 { | |
178 | phy-handle = <ðphy0>; | |
179 | }; | |
180 | }; |