[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / kirkwood.dtsi

// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "marvell,kirkwood";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,feroceon";
			reg = <0>;
			clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
			clock-names = "cpu_clk", "ddrclk", "powersave";
		};
	};

	aliases {
	       gpio0 = &gpio0;
	       gpio1 = &gpio1;
	       i2c0 = &i2c0;
	};

	mbus@f1000000 {
		compatible = "marvell,kirkwood-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		/* If a board file needs to change this ranges it must replace it completely */
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000	/* internal-regs */
			  MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000	/* nand flash */
			  MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000	/* crypto sram */
			  >;
		controller = <&mbusc>;
		pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
		pcie-io-aperture  = <0xf2000000 0x100000>;   /*   1 MiB    I/O space */

		nand: nand@12f {
			#address-cells = <1>;
			#size-cells = <1>;
			cle = <0>;
			ale = <1>;
			bank-width = <1>;
			compatible = "marvell,orion-nand";
			reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
			chip-delay = <25>;
			/* set partition map and/or chip-delay in board dts */
			clocks = <&gate_clk 7>;
			pinctrl-0 = <&pmx_nand>;
			pinctrl-names = "default";
			status = "disabled";
		};

		crypto_sram: sa-sram@301 {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>;
			clocks = <&gate_clk 17>;
			#address-cells = <1>;
			#size-cells = <1>;
		};
	};

	ocp@f1000000 {
		compatible = "simple-bus";
		ranges = <0x00000000 0xf1000000 0x0100000>;
		#address-cells = <1>;
		#size-cells = <1>;

		pinctrl: pin-controller@10000 {
			/* set compatible property in SoC file */
			reg = <0x10000 0x20>;

			pmx_ge1: pmx-ge1 {
				marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23",
					       "mpp24", "mpp25", "mpp26", "mpp27",
					       "mpp30", "mpp31", "mpp32", "mpp33";
				marvell,function = "ge1";
			};

			pmx_nand: pmx-nand {
				marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
					       "mpp4", "mpp5", "mpp18", "mpp19";
				marvell,function = "nand";
			};

			/*
			 * Default SPI0 pinctrl setting with CSn on mpp0,
			 * overwrite marvell,pins on board level if required.
			 */
			pmx_spi: pmx-spi {
				marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
				marvell,function = "spi";
			};

			pmx_twsi0: pmx-twsi0 {
				marvell,pins = "mpp8", "mpp9";
				marvell,function = "twsi0";
			};

			/*
			 * Default UART pinctrl setting without RTS/CTS,
			 * overwrite marvell,pins on board level if required.
			 */
			pmx_uart0: pmx-uart0 {
				marvell,pins = "mpp10", "mpp11";
				marvell,function = "uart0";
			};

			pmx_uart1: pmx-uart1 {
				marvell,pins = "mpp13", "mpp14";
				marvell,function = "uart1";
			};
		};

		core_clk: core-clocks@10030 {
			compatible = "marvell,kirkwood-core-clock";
			reg = <0x10030 0x4>;
			#clock-cells = <1>;
		};

		spi0: spi@10600 {
			compatible = "marvell,orion-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			interrupts = <23>;
			reg = <0x10600 0x28>;
			clocks = <&gate_clk 7>;
			pinctrl-0 = <&pmx_spi>;
			pinctrl-names = "default";
			status = "disabled";
		};

		gpio0: gpio@10100 {
			compatible = "marvell,orion-gpio";
			#gpio-cells = <2>;
			gpio-controller;
			reg = <0x10100 0x40>;
			ngpios = <32>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <35>, <36>, <37>, <38>;
			clocks = <&gate_clk 7>;
		};

		gpio1: gpio@10140 {
			compatible = "marvell,orion-gpio";
			#gpio-cells = <2>;
			gpio-controller;
			reg = <0x10140 0x40>;
			ngpios = <18>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <39>, <40>, <41>;
			clocks = <&gate_clk 7>;
		};

		i2c0: i2c@11000 {
			compatible = "marvell,mv64xxx-i2c";
			reg = <0x11000 0x20>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <29>;
			clock-frequency = <100000>;
			clocks = <&gate_clk 7>;
			pinctrl-0 = <&pmx_twsi0>;
			pinctrl-names = "default";
			status = "disabled";
		};

		uart0: serial@12000 {
			compatible = "ns16550a";
			reg = <0x12000 0x100>;
			reg-shift = <2>;
			interrupts = <33>;
			clocks = <&gate_clk 7>;
			pinctrl-0 = <&pmx_uart0>;
			pinctrl-names = "default";
			status = "disabled";
		};

		uart1: serial@12100 {
			compatible = "ns16550a";
			reg = <0x12100 0x100>;
			reg-shift = <2>;
			interrupts = <34>;
			clocks = <&gate_clk 7>;
			pinctrl-0 = <&pmx_uart1>;
			pinctrl-names = "default";
			status = "disabled";
		};

		mbusc: mbus-controller@20000 {
			compatible = "marvell,mbus-controller";
			reg = <0x20000 0x80>, <0x1500 0x20>;
		};

		sysc: system-controller@20000 {
			compatible = "marvell,orion-system-controller";
			reg = <0x20000 0x120>;
		};

		bridge_intc: bridge-interrupt-ctrl@20110 {
			compatible = "marvell,orion-bridge-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x20110 0x8>;
			interrupts = <1>;
			marvell,#interrupts = <6>;
		};

		gate_clk: clock-gating-control@2011c {
			compatible = "marvell,kirkwood-gating-clock";
			reg = <0x2011c 0x4>;
			clocks = <&core_clk 0>;
			#clock-cells = <1>;
		};

		l2: l2-cache@20128 {
			compatible = "marvell,kirkwood-cache";
			reg = <0x20128 0x4>;
		};

		intc: main-interrupt-ctrl@20200 {
			compatible = "marvell,orion-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x20200 0x10>, <0x20210 0x10>;
		};

		timer: timer@20300 {
			compatible = "marvell,orion-timer";
			reg = <0x20300 0x20>;
			interrupt-parent = <&bridge_intc>;
			interrupts = <1>, <2>;
			clocks = <&core_clk 0>;
		};

		wdt: watchdog-timer@20300 {
			compatible = "marvell,orion-wdt";
			reg = <0x20300 0x28>, <0x20108 0x4>;
			interrupt-parent = <&bridge_intc>;
			interrupts = <3>;
			clocks = <&gate_clk 7>;
			status = "okay";
		};

		cesa: crypto@30000 {
			compatible = "marvell,kirkwood-crypto";
			reg = <0x30000 0x10000>;
			reg-names = "regs";
			interrupts = <22>;
			clocks = <&gate_clk 17>;
			marvell,crypto-srams = <&crypto_sram>;
			marvell,crypto-sram-size = <0x800>;
			status = "okay";
		};

		usb0: ehci@50000 {
			compatible = "marvell,orion-ehci";
			reg = <0x50000 0x1000>;
			interrupts = <19>;
			clocks = <&gate_clk 3>;
			status = "okay";
		};

		dma0: xor@60800 {
			compatible = "marvell,orion-xor";
			reg = <0x60800 0x100
			       0x60A00 0x100>;
			status = "okay";
			clocks = <&gate_clk 8>;

			xor00 {
			      interrupts = <5>;
			      dmacap,memcpy;
			      dmacap,xor;
			};
			xor01 {
			      interrupts = <6>;
			      dmacap,memcpy;
			      dmacap,xor;
			      dmacap,memset;
			};
		};

		dma1: xor@60900 {
			compatible = "marvell,orion-xor";
			reg = <0x60900 0x100
			       0x60B00 0x100>;
			status = "okay";
			clocks = <&gate_clk 16>;

			xor00 {
			      interrupts = <7>;
			      dmacap,memcpy;
			      dmacap,xor;
			};
			xor01 {
			      interrupts = <8>;
			      dmacap,memcpy;
			      dmacap,xor;
			      dmacap,memset;
			};
		};

		eth0: ethernet-controller@72000 {
			compatible = "marvell,kirkwood-eth";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x72000 0x4000>;
			clocks = <&gate_clk 0>;
			marvell,tx-checksum-limit = <1600>;
			status = "disabled";

			eth0port: ethernet0-port@0 {
				compatible = "marvell,kirkwood-eth-port";
				reg = <0>;
				interrupts = <11>;
				/* overwrite MAC address in bootloader */
				local-mac-address = [00 00 00 00 00 00];
				/* set phy-handle property in board file */
			};
		};

		mdio: mdio-bus@72004 {
			compatible = "marvell,orion-mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x72004 0x84>;
			interrupts = <46>;
			clocks = <&gate_clk 0>;
			status = "disabled";

			/* add phy nodes in board file */
		};

		eth1: ethernet-controller@76000 {
			compatible = "marvell,kirkwood-eth";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x76000 0x4000>;
			clocks = <&gate_clk 19>;
			marvell,tx-checksum-limit = <1600>;
			pinctrl-0 = <&pmx_ge1>;
			pinctrl-names = "default";
			status = "disabled";

			eth1port: ethernet1-port@0 {
				compatible = "marvell,kirkwood-eth-port";
				reg = <0>;
				interrupts = <15>;
				/* overwrite MAC address in bootloader */
				local-mac-address = [00 00 00 00 00 00];
				/* set phy-handle property in board file */
			};
		};

		sata_phy0: sata-phy@82000 {
			compatible = "marvell,mvebu-sata-phy";
			reg = <0x82000 0x0334>;
			clocks = <&gate_clk 14>;
			clock-names = "sata";
			#phy-cells = <0>;
			status = "ok";
		};

		sata_phy1: sata-phy@84000 {
			compatible = "marvell,mvebu-sata-phy";
			reg = <0x84000 0x0334>;
			clocks = <&gate_clk 15>;
			clock-names = "sata";
			#phy-cells = <0>;
			status = "ok";
		};

		audio0: audio-controller@a0000 {
			compatible = "marvell,kirkwood-audio";
			#sound-dai-cells = <0>;
			reg = <0xa0000 0x2210>;
			interrupts = <24>;
			clocks = <&gate_clk 9>;
			clock-names = "internal";
			status = "disabled";
		};
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
23301190	2	#include <dt-bindings/input/input.h>
3a31f2d7	3	#include <dt-bindings/gpio/gpio.h>
3d468b6d	4
3ec81e7e EG	5	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
3ec81e7e EG	6
3d468b6d	7	/ {
abe60a3a RH	8	#address-cells = <1>;
abe60a3a RH	9	#size-cells = <1>;
77843504	10	compatible = "marvell,kirkwood";
278b45b0 AL	11	interrupt-parent = <&intc>;
278b45b0 AL	12
33a66754 AB	13	cpus {
	14	#address-cells = <1>;
	15	#size-cells = <0>;
	16
	17	cpu@0 {
	18	device_type = "cpu";
	19	compatible = "marvell,feroceon";
2290414b	20	reg = <0>;
33a66754 AB	21	clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
	22	clock-names = "cpu_clk", "ddrclk", "powersave";
	23	};
	24	};
	25
f9e75922 AL	26	aliases {
	27	gpio0 = &gpio0;
	28	gpio1 = &gpio1;
cb932e12	29	i2c0 = &i2c0;
f9e75922	30	};
3d468b6d	31
5d7fd656	32	mbus@f1000000 {
455f81a3	33	compatible = "marvell,kirkwood-mbus", "simple-bus";
54397d85 EG	34	#address-cells = <2>;
54397d85 EG	35	#size-cells = <1>;
7f69f8a4 JG	36	/* If a board file needs to change this ranges it must replace it completely */
	37	ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
	38	MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
	39	MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
	40	>;
455f81a3	41	controller = <&mbusc>;
54397d85 EG	42	pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
54397d85 EG	43	pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
34a30090	44
8dccafaa	45	nand: nand@12f {
7045ff5a JG	46	#address-cells = <1>;
	47	#size-cells = <1>;
	48	cle = <0>;
	49	ale = <1>;
	50	bank-width = <1>;
	51	compatible = "marvell,orion-nand";
	52	reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
	53	chip-delay = <25>;
	54	/* set partition map and/or chip-delay in board dts */
	55	clocks = <&gate_clk 7>;
cbfaea96 SH	56	pinctrl-0 = <&pmx_nand>;
cbfaea96 SH	57	pinctrl-names = "default";
7045ff5a JG	58	status = "disabled";
7045ff5a JG	59	};
eb69e001	60
8dccafaa	61	crypto_sram: sa-sram@301 {
eb69e001 BB	62	compatible = "mmio-sram";
	63	reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>;
	64	clocks = <&gate_clk 17>;
	65	#address-cells = <1>;
	66	#size-cells = <1>;
	67	};
455f81a3 EG	68	};
455f81a3 EG	69
163f2cea JC	70	ocp@f1000000 {
163f2cea JC	71	compatible = "simple-bus";
7045ff5a	72	ranges = <0x00000000 0xf1000000 0x0100000>;
163f2cea JC	73	#address-cells = <1>;
	74	#size-cells = <1>;
	75
2ab516ad SH	76	pinctrl: pin-controller@10000 {
	77	/* set compatible property in SoC file */
	78	reg = <0x10000 0x20>;
327e1542 SH	79
	80	pmx_ge1: pmx-ge1 {
	81	marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23",
	82	"mpp24", "mpp25", "mpp26", "mpp27",
	83	"mpp30", "mpp31", "mpp32", "mpp33";
	84	marvell,function = "ge1";
	85	};
	86
	87	pmx_nand: pmx-nand {
	88	marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
	89	"mpp4", "mpp5", "mpp18", "mpp19";
	90	marvell,function = "nand";
	91	};
	92
92901201 SH	93	/*
	94	* Default SPI0 pinctrl setting with CSn on mpp0,
	95	* overwrite marvell,pins on board level if required.
	96	*/
327e1542 SH	97	pmx_spi: pmx-spi {
	98	marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
	99	marvell,function = "spi";
	100	};
	101
	102	pmx_twsi0: pmx-twsi0 {
	103	marvell,pins = "mpp8", "mpp9";
	104	marvell,function = "twsi0";
	105	};
	106
9f2339a6 SH	107	/*
	108	* Default UART pinctrl setting without RTS/CTS,
	109	* overwrite marvell,pins on board level if required.
	110	*/
327e1542 SH	111	pmx_uart0: pmx-uart0 {
	112	marvell,pins = "mpp10", "mpp11";
	113	marvell,function = "uart0";
	114	};
	115
	116	pmx_uart1: pmx-uart1 {
	117	marvell,pins = "mpp13", "mpp14";
	118	marvell,function = "uart1";
	119	};
2ab516ad SH	120	};
2ab516ad SH	121
1611f872 AL	122	core_clk: core-clocks@10030 {
	123	compatible = "marvell,kirkwood-core-clock";
	124	reg = <0x10030 0x4>;
20bba588 JC	125	#clock-cells = <1>;
	126	};
	127
7b36efd0	128	spi0: spi@10600 {
20bba588 JC	129	compatible = "marvell,orion-spi";
	130	#address-cells = <1>;
	131	#size-cells = <0>;
	132	cell-index = <0>;
	133	interrupts = <23>;
	134	reg = <0x10600 0x28>;
	135	clocks = <&gate_clk 7>;
92901201 SH	136	pinctrl-0 = <&pmx_spi>;
92901201 SH	137	pinctrl-names = "default";
20bba588	138	status = "disabled";
1611f872 AL	139	};
1611f872 AL	140
278b45b0 AL	141	gpio0: gpio@10100 {
	142	compatible = "marvell,orion-gpio";
	143	#gpio-cells = <2>;
	144	gpio-controller;
	145	reg = <0x10100 0x40>;
f9e75922 AL	146	ngpios = <32>;
f9e75922 AL	147	interrupt-controller;
09d75bc7	148	#interrupt-cells = <2>;
278b45b0	149	interrupts = <35>, <36>, <37>, <38>;
de88747f	150	clocks = <&gate_clk 7>;
278b45b0 AL	151	};
	152
	153	gpio1: gpio@10140 {
	154	compatible = "marvell,orion-gpio";
	155	#gpio-cells = <2>;
	156	gpio-controller;
	157	reg = <0x10140 0x40>;
f9e75922 AL	158	ngpios = <18>;
f9e75922 AL	159	interrupt-controller;
09d75bc7	160	#interrupt-cells = <2>;
278b45b0	161	interrupts = <39>, <40>, <41>;
de88747f	162	clocks = <&gate_clk 7>;
278b45b0 AL	163	};
278b45b0 AL	164
cb932e12	165	i2c0: i2c@11000 {
20bba588 JC	166	compatible = "marvell,mv64xxx-i2c";
	167	reg = <0x11000 0x20>;
	168	#address-cells = <1>;
	169	#size-cells = <0>;
	170	interrupts = <29>;
	171	clock-frequency = <100000>;
	172	clocks = <&gate_clk 7>;
ce55b1f4 SH	173	pinctrl-0 = <&pmx_twsi0>;
ce55b1f4 SH	174	pinctrl-names = "default";
20bba588 JC	175	status = "disabled";
	176	};
	177
7b36efd0	178	uart0: serial@12000 {
163f2cea JC	179	compatible = "ns16550a";
	180	reg = <0x12000 0x100>;
	181	reg-shift = <2>;
	182	interrupts = <33>;
1611f872	183	clocks = <&gate_clk 7>;
9f2339a6 SH	184	pinctrl-0 = <&pmx_uart0>;
9f2339a6 SH	185	pinctrl-names = "default";
163f2cea JC	186	status = "disabled";
	187	};
	188
7b36efd0	189	uart1: serial@12100 {
163f2cea JC	190	compatible = "ns16550a";
	191	reg = <0x12100 0x100>;
	192	reg-shift = <2>;
	193	interrupts = <34>;
1611f872	194	clocks = <&gate_clk 7>;
9f2339a6 SH	195	pinctrl-0 = <&pmx_uart1>;
9f2339a6 SH	196	pinctrl-names = "default";
163f2cea JC	197	status = "disabled";
163f2cea JC	198	};
e871b87a	199
20bba588 JC	200	mbusc: mbus-controller@20000 {
	201	compatible = "marvell,mbus-controller";
	202	reg = <0x20000 0x80>, <0x1500 0x20>;
	203	};
	204
7b36efd0	205	sysc: system-controller@20000 {
77026937 AL	206	compatible = "marvell,orion-system-controller";
	207	reg = <0x20000 0x120>;
	208	};
	209
20bba588 JC	210	bridge_intc: bridge-interrupt-ctrl@20110 {
	211	compatible = "marvell,orion-bridge-intc";
	212	interrupt-controller;
	213	#interrupt-cells = <1>;
	214	reg = <0x20110 0x8>;
	215	interrupts = <1>;
	216	marvell,#interrupts = <6>;
76372120 MW	217	};
76372120 MW	218
1611f872 AL	219	gate_clk: clock-gating-control@2011c {
	220	compatible = "marvell,kirkwood-gating-clock";
	221	reg = <0x2011c 0x4>;
	222	clocks = <&core_clk 0>;
	223	#clock-cells = <1>;
	224	};
	225
e65d9c61 AL	226	l2: l2-cache@20128 {
	227	compatible = "marvell,kirkwood-cache";
	228	reg = <0x20128 0x4>;
	229	};
	230
20bba588 JC	231	intc: main-interrupt-ctrl@20200 {
	232	compatible = "marvell,orion-intc";
	233	interrupt-controller;
	234	#interrupt-cells = <1>;
	235	reg = <0x20200 0x10>, <0x20210 0x10>;
	236	};
	237
	238	timer: timer@20300 {
	239	compatible = "marvell,orion-timer";
	240	reg = <0x20300 0x20>;
	241	interrupt-parent = <&bridge_intc>;
	242	interrupts = <1>, <2>;
	243	clocks = <&core_clk 0>;
	244	};
	245
15f18591	246	wdt: watchdog-timer@20300 {
1e7bad0f	247	compatible = "marvell,orion-wdt";
7224cbc1	248	reg = <0x20300 0x28>, <0x20108 0x4>;
15f18591 SH	249	interrupt-parent = <&bridge_intc>;
15f18591 SH	250	interrupts = <3>;
1611f872	251	clocks = <&gate_clk 7>;
1e7bad0f AL	252	status = "okay";
	253	};
	254
eb69e001	255	cesa: crypto@30000 {
9b24a35c	256	compatible = "marvell,kirkwood-crypto";
eb69e001 BB	257	reg = <0x30000 0x10000>;
	258	reg-names = "regs";
	259	interrupts = <22>;
	260	clocks = <&gate_clk 17>;
	261	marvell,crypto-srams = <&crypto_sram>;
	262	marvell,crypto-sram-size = <0x800>;
	263	status = "okay";
	264	};
	265
7b36efd0	266	usb0: ehci@50000 {
20bba588 JC	267	compatible = "marvell,orion-ehci";
	268	reg = <0x50000 0x1000>;
	269	interrupts = <19>;
	270	clocks = <&gate_clk 3>;
	271	status = "okay";
	272	};
	273
7b36efd0	274	dma0: xor@60800 {
c896ed0f AL	275	compatible = "marvell,orion-xor";
	276	reg = <0x60800 0x100
	277	0x60A00 0x100>;
	278	status = "okay";
	279	clocks = <&gate_clk 8>;
	280
	281	xor00 {
	282	interrupts = <5>;
	283	dmacap,memcpy;
	284	dmacap,xor;
	285	};
	286	xor01 {
	287	interrupts = <6>;
	288	dmacap,memcpy;
	289	dmacap,xor;
	290	dmacap,memset;
	291	};
	292	};
	293
7b36efd0	294	dma1: xor@60900 {
c896ed0f AL	295	compatible = "marvell,orion-xor";
c896ed0f AL	296	reg = <0x60900 0x100
ddf7e399	297	0x60B00 0x100>;
1e7bad0f	298	status = "okay";
c896ed0f AL	299	clocks = <&gate_clk 16>;
	300
	301	xor00 {
	302	interrupts = <7>;
	303	dmacap,memcpy;
	304	dmacap,xor;
	305	};
	306	xor01 {
	307	interrupts = <8>;
	308	dmacap,memcpy;
	309	dmacap,xor;
	310	dmacap,memset;
	311	};
1e7bad0f AL	312	};
1e7bad0f AL	313
876e2333 SH	314	eth0: ethernet-controller@72000 {
	315	compatible = "marvell,kirkwood-eth";
	316	#address-cells = <1>;
	317	#size-cells = <0>;
	318	reg = <0x72000 0x4000>;
	319	clocks = <&gate_clk 0>;
	320	marvell,tx-checksum-limit = <1600>;
	321	status = "disabled";
	322
4f5e01e9	323	eth0port: ethernet0-port@0 {
876e2333 SH	324	compatible = "marvell,kirkwood-eth-port";
	325	reg = <0>;
	326	interrupts = <11>;
	327	/* overwrite MAC address in bootloader */
	328	local-mac-address = [00 00 00 00 00 00];
	329	/* set phy-handle property in board file */
	330	};
	331	};
	332
20bba588 JC	333	mdio: mdio-bus@72004 {
	334	compatible = "marvell,orion-mdio";
	335	#address-cells = <1>;
	336	#size-cells = <0>;
	337	reg = <0x72004 0x84>;
	338	interrupts = <46>;
	339	clocks = <&gate_clk 0>;
	340	status = "disabled";
	341
	342	/* add phy nodes in board file */
	343	};
	344
876e2333 SH	345	eth1: ethernet-controller@76000 {
	346	compatible = "marvell,kirkwood-eth";
	347	#address-cells = <1>;
	348	#size-cells = <0>;
	349	reg = <0x76000 0x4000>;
	350	clocks = <&gate_clk 19>;
	351	marvell,tx-checksum-limit = <1600>;
9dd85ad2 SH	352	pinctrl-0 = <&pmx_ge1>;
9dd85ad2 SH	353	pinctrl-names = "default";
876e2333 SH	354	status = "disabled";
876e2333 SH	355
4f5e01e9	356	eth1port: ethernet1-port@0 {
876e2333 SH	357	compatible = "marvell,kirkwood-eth-port";
	358	reg = <0>;
	359	interrupts = <15>;
	360	/* overwrite MAC address in bootloader */
	361	local-mac-address = [00 00 00 00 00 00];
	362	/* set phy-handle property in board file */
	363	};
	364	};
0ad82cd8 AL	365
	366	sata_phy0: sata-phy@82000 {
	367	compatible = "marvell,mvebu-sata-phy";
	368	reg = <0x82000 0x0334>;
	369	clocks = <&gate_clk 14>;
	370	clock-names = "sata";
	371	#phy-cells = <0>;
	372	status = "ok";
	373	};
	374
	375	sata_phy1: sata-phy@84000 {
	376	compatible = "marvell,mvebu-sata-phy";
	377	reg = <0x84000 0x0334>;
	378	clocks = <&gate_clk 15>;
	379	clock-names = "sata";
	380	#phy-cells = <0>;
	381	status = "ok";
	382	};
b3f742cc AL	383
	384	audio0: audio-controller@a0000 {
	385	compatible = "marvell,kirkwood-audio";
e662e70f	386	#sound-dai-cells = <0>;
b3f742cc AL	387	reg = <0xa0000 0x2210>;
	388	interrupts = <24>;
	389	clocks = <&gate_clk 9>;
	390	clock-names = "internal";
	391	status = "disabled";
	392	};
163f2cea JC	393	};
163f2cea JC	394	};