[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / logicpd-torpedo-som.dtsi

// SPDX-License-Identifier: GPL-2.0-only

#include <dt-bindings/input/input.h>

/ {
	chosen {
		stdout-path = &uart1;
	};

	cpus {
		cpu@0 {
			cpu0-supply = <&vcc>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0>;
	};

	leds {
		compatible = "gpio-leds";
		user0 {
			label = "user0";
			gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;	/* LEDA */
			linux,default-trigger = "none";
		};
	};

	/* fixed 26MHz oscillator */
	hfclk_26m: oscillator {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
	};
};

&gpmc {
	ranges = <0 0 0x30000000 0x1000000>;	/* CS0: 16MB for NAND */

	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		linux,mtd-name = "micron,mt29f4g16abbda3w";
		nand-bus-width = <16>;
		ti,nand-ecc-opt = "bch8";
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <44>;
		gpmc,cs-wr-off-ns = <44>;
		gpmc,adv-on-ns = <6>;
		gpmc,adv-rd-off-ns = <34>;
		gpmc,adv-wr-off-ns = <44>;
		gpmc,we-off-ns = <40>;
		gpmc,oe-off-ns = <54>;
		gpmc,access-ns = <64>;
		gpmc,rd-cycle-ns = <82>;
		gpmc,wr-cycle-ns = <82>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;
		gpmc,device-width = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	clock-frequency = <2600000>;

	twl: twl@48 {
		reg = <0x48>;
		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
		interrupt-parent = <&intc>;
		clocks = <&hfclk_26m>;
		clock-names = "fck";

		twl_audio: audio {
			compatible = "ti,twl4030-audio";
			codec {
			};
		};
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	clock-frequency = <400000>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;
	clock-frequency = <400000>;
	at24@50 {
		compatible = "atmel,24c64";
		readonly;
		reg = <0x50>;
	};
};

&omap3_pmx_core {
	mcbsp2_pins: pinmux_mcbsp2_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx */
			OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx */
			OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr */
			OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx */
		>;
	};
	uart2_pins: pinmux_uart2_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)	/* uart2_cts.uart2_cts */
			OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)	/* uart2_rts .uart2_rts*/
			OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)	/* uart2_tx.uart2_tx */
			OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)	/* uart2_rx.uart2_rx */
			OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)	/* GPIO_162,BT_EN */
		>;
	};
	mcspi1_pins: pinmux_mcspi1_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
			OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_simo.mcspi1_simo */
			OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
			OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
		>;
	};
	hsusb_otg_pins: pinmux_hsusb_otg_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)	/* hsusb0_clk.hsusb0_clk */
			OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)	/* hsusb0_stp.hsusb0_stp */
			OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)	/* hsusb0_dir.hsusb0_dir */
			OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)	/* hsusb0_nxt.hsusb0_nxt */

			OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)	/* hsusb0_data0.hsusb0_data0 */
			OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)	/* hsusb0_data1.hsusb0_data1 */
			OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)	/* hsusb0_data2.hsusb0_data2 */
			OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)	/* hsusb0_data3.hsusb0_data3 */
			OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)	/* hsusb0_data4.hsusb0_data4 */
			OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)	/* hsusb0_data5.hsusb0_data5 */
			OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)	/* hsusb0_data6.hsusb0_data6 */
			OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)	/* hsusb0_data7.hsusb0_data7 */
		>;
	};
	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)        /* i2c1_scl.i2c1_scl */
			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)        /* i2c1_sda.i2c1_sda */
		>;
	};
	i2c2_pins: pinmux_i2c2_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)	/* i2c2_scl */
			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)	/* i2c2_sda */
		>;
	};
	i2c3_pins: pinmux_i2c3_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl */
			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda */
		>;
	};
};

&uart2 {
	interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
};

&mcspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi1_pins>;
};

#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"

&twl {
	twl_power: power {
		compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
		ti,use_poweroff;
	};
};

&twl_gpio {
	ti,use-leds;
};
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
687c2767 TL	2
	3	#include <dt-bindings/input/input.h>
	4
	5	/ {
cb11a8ba TL	6	chosen {
	7	stdout-path = &uart1;
	8	};
	9
687c2767 TL	10	cpus {
	11	cpu@0 {
	12	cpu0-supply = <&vcc>;
	13	};
	14	};
	15
271a3024	16	memory@80000000 {
766a1fe7	17	device_type = "memory";
271a3024	18	reg = <0x80000000 0>;
766a1fe7 JMC	19	};
766a1fe7 JMC	20
687c2767 TL	21	leds {
	22	compatible = "gpio-leds";
	23	user0 {
	24	label = "user0";
	25	gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
	26	linux,default-trigger = "none";
	27	};
	28	};
d0174fa4 AF	29
	30	/* fixed 26MHz oscillator */
	31	hfclk_26m: oscillator {
	32	#clock-cells = <0>;
	33	compatible = "fixed-clock";
	34	clock-frequency = <26000000>;
	35	};
687c2767 TL	36	};
	37
	38	&gpmc {
44e47164	39	ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
687c2767 TL	40
687c2767 TL	41	nand@0,0 {
44e47164	42	compatible = "ti,omap2-nand";
687c2767	43	reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
44e47164 RQ	44	interrupt-parent = <&gpmc>;
	45	interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
	46	<1 IRQ_TYPE_NONE>; /* termcount */
	47	linux,mtd-name = "micron,mt29f4g16abbda3w";
687c2767 TL	48	nand-bus-width = <16>;
687c2767 TL	49	ti,nand-ecc-opt = "bch8";
a8771a6a	50	rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
687c2767 TL	51	gpmc,sync-clk-ps = <0>;
	52	gpmc,cs-on-ns = <0>;
	53	gpmc,cs-rd-off-ns = <44>;
	54	gpmc,cs-wr-off-ns = <44>;
	55	gpmc,adv-on-ns = <6>;
	56	gpmc,adv-rd-off-ns = <34>;
	57	gpmc,adv-wr-off-ns = <44>;
	58	gpmc,we-off-ns = <40>;
	59	gpmc,oe-off-ns = <54>;
	60	gpmc,access-ns = <64>;
	61	gpmc,rd-cycle-ns = <82>;
	62	gpmc,wr-cycle-ns = <82>;
	63	gpmc,wr-access-ns = <40>;
	64	gpmc,wr-data-mux-bus-ns = <0>;
	65	gpmc,device-width = <2>;
	66	#address-cells = <1>;
	67	#size-cells = <1>;
687c2767 TL	68	};
	69	};
	70
	71	&i2c1 {
74402055 AF	72	pinctrl-names = "default";
74402055 AF	73	pinctrl-0 = <&i2c1_pins>;
687c2767 TL	74	clock-frequency = <2600000>;
	75
	76	twl: twl@48 {
	77	reg = <0x48>;
	78	interrupts = <7>; /* SYS_NIRQ cascaded to intc */
	79	interrupt-parent = <&intc>;
d0174fa4 AF	80	clocks = <&hfclk_26m>;
	81	clock-names = "fck";
	82
f81902e4 AF	83	twl_audio: audio {
	84	compatible = "ti,twl4030-audio";
	85	codec {
	86	};
	87	};
687c2767 TL	88	};
	89	};
	90
6b3d42c6	91	&i2c2 {
a135a392 AF	92	pinctrl-names = "default";
a135a392 AF	93	pinctrl-0 = <&i2c2_pins>;
6b3d42c6 AF	94	clock-frequency = <400000>;
	95	};
	96
	97	&i2c3 {
a135a392 AF	98	pinctrl-names = "default";
a135a392 AF	99	pinctrl-0 = <&i2c3_pins>;
6b3d42c6	100	clock-frequency = <400000>;
5e3447a2	101	at24@50 {
06e1a5cc	102	compatible = "atmel,24c64";
5e3447a2 AF	103	readonly;
	104	reg = <0x50>;
	105	};
6b3d42c6 AF	106	};
6b3d42c6 AF	107
687c2767	108	&omap3_pmx_core {
f81902e4 AF	109	mcbsp2_pins: pinmux_mcbsp2_pins {
	110	pinctrl-single,pins = <
	111	OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT \| MUX_MODE0) /* mcbsp2_fsx */
	112	OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT \| MUX_MODE0) /* mcbsp2_clkx */
	113	OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT \| MUX_MODE0) /* mcbsp2_dr */
	114	OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT \| MUX_MODE0) /* mcbsp2_dx */
	115	>;
	116	};
9ff502f5 AF	117	uart2_pins: pinmux_uart2_pins {
	118	pinctrl-single,pins = <
	119	OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT \| MUX_MODE0) /* uart2_cts.uart2_cts */
	120	OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT \| MUX_MODE0) /* uart2_rts .uart2_rts*/
	121	OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT \| MUX_MODE0) /* uart2_tx.uart2_tx */
	122	OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT \| MUX_MODE0) /* uart2_rx.uart2_rx */
	123	OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT \| MUX_MODE4) /* GPIO_162,BT_EN */
	124	>;
	125	};
40d5cb20 AF	126	mcspi1_pins: pinmux_mcspi1_pins {
	127	pinctrl-single,pins = <
	128	OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT \| MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
	129	OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT \| MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
	130	OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP \| MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
	131	OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT \| MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
	132	>;
	133	};
b4cc2b75 AF	134	hsusb_otg_pins: pinmux_hsusb_otg_pins {
	135	pinctrl-single,pins = <
	136	OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT \| MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
	137	OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT \| MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
	138	OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT \| MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
	139	OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT \| MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
	140
	141	OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT \| MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
	142	OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT \| MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
	143	OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT \| MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
	144	OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT \| MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
	145	OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT \| MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
	146	OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT \| MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
	147	OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT \| MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
	148	OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT \| MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
	149	>;
	150	};
74402055 AF	151	i2c1_pins: pinmux_i2c1_pins {
	152	pinctrl-single,pins = <
	153	OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT \| MUX_MODE0) /* i2c1_scl.i2c1_scl */
	154	OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT \| MUX_MODE0) /* i2c1_sda.i2c1_sda */
	155	>;
	156	};
a135a392 AF	157	i2c2_pins: pinmux_i2c2_pins {
	158	pinctrl-single,pins = <
	159	OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT \| MUX_MODE0) /* i2c2_scl */
	160	OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT \| MUX_MODE0) /* i2c2_sda */
	161	>;
	162	};
	163	i2c3_pins: pinmux_i2c3_pins {
	164	pinctrl-single,pins = <
	165	OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT \| MUX_MODE0) /* i2c3_scl */
	166	OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT \| MUX_MODE0) /* i2c3_sda */
	167	>;
	168	};
9ff502f5 AF	169	};
	170
	171	&uart2 {
	172	interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
	173	pinctrl-names = "default";
	174	pinctrl-0 = <&uart2_pins>;
687c2767 TL	175	};
687c2767 TL	176
40d5cb20 AF	177	&mcspi1 {
	178	pinctrl-names = "default";
	179	pinctrl-0 = <&mcspi1_pins>;
	180	};
	181
687c2767 TL	182	#include "twl4030.dtsi"
	183	#include "twl4030_omap3.dtsi"
	184
	185	&twl {
	186	twl_power: power {
	187	compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
	188	ti,use_poweroff;
	189	};
	190	};
	191
	192	&twl_gpio {
	193	ti,use-leds;
	194	};