]>
Commit | Line | Data |
---|---|---|
e04920d9 RS |
1 | /* |
2 | * NXP LPC32xx SoC | |
3 | * | |
4 | * Copyright 2012 Roland Stigge <stigge@antcom.de> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
1a24edd2 | 14 | #include "skeleton.dtsi" |
e04920d9 | 15 | |
93898eb7 | 16 | #include <dt-bindings/clock/lpc32xx-clock.h> |
b715802f | 17 | #include <dt-bindings/interrupt-controller/irq.h> |
93898eb7 | 18 | |
e04920d9 RS |
19 | / { |
20 | compatible = "nxp,lpc3220"; | |
21 | interrupt-parent = <&mic>; | |
22 | ||
23 | cpus { | |
246d8fc3 | 24 | #address-cells = <1>; |
73158b77 LP |
25 | #size-cells = <0>; |
26 | ||
246d8fc3 | 27 | cpu@0 { |
73158b77 LP |
28 | compatible = "arm,arm926ej-s"; |
29 | device_type = "cpu"; | |
246d8fc3 | 30 | reg = <0x0>; |
e04920d9 RS |
31 | }; |
32 | }; | |
33 | ||
ef5f885e VZ |
34 | clocks { |
35 | xtal_32k: xtal_32k { | |
36 | compatible = "fixed-clock"; | |
37 | #clock-cells = <0>; | |
38 | clock-frequency = <32768>; | |
39 | clock-output-names = "xtal_32k"; | |
40 | }; | |
41 | ||
42 | xtal: xtal { | |
43 | compatible = "fixed-clock"; | |
44 | #clock-cells = <0>; | |
45 | clock-frequency = <13000000>; | |
46 | clock-output-names = "xtal"; | |
47 | }; | |
48 | }; | |
49 | ||
e04920d9 RS |
50 | ahb { |
51 | #address-cells = <1>; | |
52 | #size-cells = <1>; | |
53 | compatible = "simple-bus"; | |
8185041f VZ |
54 | ranges = <0x00000000 0x00000000 0x10000000>, |
55 | <0x20000000 0x20000000 0x30000000>, | |
f83ee67f | 56 | <0xe0000000 0xe0000000 0x04000000>; |
e04920d9 | 57 | |
8dccafaa | 58 | iram: sram@8000000 { |
8185041f VZ |
59 | compatible = "mmio-sram"; |
60 | reg = <0x08000000 0x20000>; | |
61 | ||
62 | #address-cells = <1>; | |
63 | #size-cells = <1>; | |
64 | ranges = <0x00000000 0x08000000 0x20000>; | |
65 | }; | |
66 | ||
e04920d9 RS |
67 | /* |
68 | * Enable either SLC or MLC | |
69 | */ | |
70 | slc: flash@20020000 { | |
71 | compatible = "nxp,lpc3220-slc"; | |
72 | reg = <0x20020000 0x1000>; | |
93898eb7 | 73 | clocks = <&clk LPC32XX_CLK_SLC>; |
cb85a9e5 | 74 | status = "disabled"; |
e04920d9 RS |
75 | }; |
76 | ||
6d1c3e93 | 77 | mlc: flash@200a8000 { |
e04920d9 | 78 | compatible = "nxp,lpc3220-mlc"; |
6d1c3e93 | 79 | reg = <0x200a8000 0x11000>; |
b715802f | 80 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 | 81 | clocks = <&clk LPC32XX_CLK_MLC>; |
cb85a9e5 | 82 | status = "disabled"; |
e04920d9 RS |
83 | }; |
84 | ||
25de7c96 | 85 | dma: dma@31000000 { |
e04920d9 RS |
86 | compatible = "arm,pl080", "arm,primecell"; |
87 | reg = <0x31000000 0x1000>; | |
b715802f | 88 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 VZ |
89 | clocks = <&clk LPC32XX_CLK_DMA>; |
90 | clock-names = "apb_pclk"; | |
e04920d9 RS |
91 | }; |
92 | ||
aa29efb4 VZ |
93 | usb { |
94 | #address-cells = <1>; | |
95 | #size-cells = <1>; | |
96 | compatible = "simple-bus"; | |
97 | ranges = <0x0 0x31020000 0x00001000>; | |
e04920d9 | 98 | |
aa29efb4 VZ |
99 | /* |
100 | * Enable either ohci or usbd (gadget)! | |
101 | */ | |
102 | ohci: ohci@0 { | |
103 | compatible = "nxp,ohci-nxp", "usb-ohci"; | |
104 | reg = <0x0 0x300>; | |
9b8ad3fb VZ |
105 | interrupt-parent = <&sic1>; |
106 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; | |
865e9009 | 107 | clocks = <&usbclk LPC32XX_USB_CLK_HOST>; |
aa29efb4 VZ |
108 | status = "disabled"; |
109 | }; | |
110 | ||
111 | usbd: usbd@0 { | |
112 | compatible = "nxp,lpc3220-udc"; | |
113 | reg = <0x0 0x300>; | |
9b8ad3fb VZ |
114 | interrupt-parent = <&sic1>; |
115 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, | |
116 | <30 IRQ_TYPE_LEVEL_HIGH>, | |
117 | <28 IRQ_TYPE_LEVEL_HIGH>, | |
118 | <26 IRQ_TYPE_LEVEL_LOW>; | |
865e9009 | 119 | clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; |
aa29efb4 VZ |
120 | status = "disabled"; |
121 | }; | |
122 | ||
123 | i2cusb: i2c@300 { | |
124 | compatible = "nxp,pnx-i2c"; | |
125 | reg = <0x300 0x100>; | |
9b8ad3fb VZ |
126 | interrupt-parent = <&sic1>; |
127 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; | |
865e9009 | 128 | clocks = <&usbclk LPC32XX_USB_CLK_I2C>; |
aa29efb4 VZ |
129 | #address-cells = <1>; |
130 | #size-cells = <0>; | |
131 | pnx,timeout = <0x64>; | |
132 | }; | |
865e9009 VZ |
133 | |
134 | usbclk: clock-controller@f00 { | |
135 | compatible = "nxp,lpc3220-usb-clk"; | |
136 | reg = <0xf00 0x100>; | |
137 | #clock-cells = <1>; | |
138 | }; | |
e04920d9 RS |
139 | }; |
140 | ||
25de7c96 | 141 | clcd: clcd@31040000 { |
5427c2e1 | 142 | compatible = "arm,pl111", "arm,primecell"; |
e04920d9 | 143 | reg = <0x31040000 0x1000>; |
b715802f | 144 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; |
eaae1b18 VZ |
145 | clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>; |
146 | clock-names = "clcdclk", "apb_pclk"; | |
cb85a9e5 | 147 | status = "disabled"; |
e04920d9 RS |
148 | }; |
149 | ||
150 | mac: ethernet@31060000 { | |
151 | compatible = "nxp,lpc-eth"; | |
152 | reg = <0x31060000 0x1000>; | |
b715802f | 153 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 | 154 | clocks = <&clk LPC32XX_CLK_MAC>; |
e04920d9 RS |
155 | }; |
156 | ||
f83ee67f VZ |
157 | emc: memory-controller@31080000 { |
158 | compatible = "arm,pl175", "arm,primecell"; | |
159 | reg = <0x31080000 0x1000>; | |
93898eb7 VZ |
160 | clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>; |
161 | clock-names = "mpmcclk", "apb_pclk"; | |
f83ee67f VZ |
162 | #address-cells = <1>; |
163 | #size-cells = <1>; | |
164 | ||
165 | ranges = <0 0xe0000000 0x01000000>, | |
166 | <1 0xe1000000 0x01000000>, | |
167 | <2 0xe2000000 0x01000000>, | |
168 | <3 0xe3000000 0x01000000>; | |
169 | status = "disabled"; | |
170 | }; | |
171 | ||
e04920d9 RS |
172 | apb { |
173 | #address-cells = <1>; | |
174 | #size-cells = <1>; | |
175 | compatible = "simple-bus"; | |
176 | ranges = <0x20000000 0x20000000 0x30000000>; | |
177 | ||
961212e3 SL |
178 | /* |
179 | * ssp0 and spi1 are shared pins; | |
180 | * enable one in your board dts, as needed. | |
181 | */ | |
4799f372 | 182 | ssp0: spi@20084000 { |
e04920d9 RS |
183 | compatible = "arm,pl022", "arm,primecell"; |
184 | reg = <0x20084000 0x1000>; | |
b715802f | 185 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 VZ |
186 | clocks = <&clk LPC32XX_CLK_SSP0>; |
187 | clock-names = "apb_pclk"; | |
961212e3 | 188 | status = "disabled"; |
e04920d9 RS |
189 | }; |
190 | ||
191 | spi1: spi@20088000 { | |
192 | compatible = "nxp,lpc3220-spi"; | |
193 | reg = <0x20088000 0x1000>; | |
73fdaa0f | 194 | clocks = <&clk LPC32XX_CLK_SPI1>; |
961212e3 | 195 | status = "disabled"; |
e04920d9 RS |
196 | }; |
197 | ||
961212e3 SL |
198 | /* |
199 | * ssp1 and spi2 are shared pins; | |
200 | * enable one in your board dts, as needed. | |
201 | */ | |
4799f372 | 202 | ssp1: spi@2008c000 { |
e04920d9 RS |
203 | compatible = "arm,pl022", "arm,primecell"; |
204 | reg = <0x2008c000 0x1000>; | |
b715802f | 205 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; |
93898eb7 VZ |
206 | clocks = <&clk LPC32XX_CLK_SSP1>; |
207 | clock-names = "apb_pclk"; | |
961212e3 | 208 | status = "disabled"; |
e04920d9 RS |
209 | }; |
210 | ||
211 | spi2: spi@20090000 { | |
212 | compatible = "nxp,lpc3220-spi"; | |
213 | reg = <0x20090000 0x1000>; | |
73fdaa0f | 214 | clocks = <&clk LPC32XX_CLK_SPI2>; |
961212e3 | 215 | status = "disabled"; |
e04920d9 RS |
216 | }; |
217 | ||
218 | i2s0: i2s@20094000 { | |
219 | compatible = "nxp,lpc3220-i2s"; | |
220 | reg = <0x20094000 0x1000>; | |
221 | }; | |
222 | ||
25de7c96 | 223 | sd: sd@20098000 { |
2c7fa286 | 224 | compatible = "arm,pl18x", "arm,primecell"; |
e04920d9 | 225 | reg = <0x20098000 0x1000>; |
b715802f VZ |
226 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, |
227 | <13 IRQ_TYPE_LEVEL_HIGH>; | |
93898eb7 VZ |
228 | clocks = <&clk LPC32XX_CLK_SD>; |
229 | clock-names = "apb_pclk"; | |
2c7fa286 | 230 | status = "disabled"; |
e04920d9 RS |
231 | }; |
232 | ||
1c8e6dc5 | 233 | i2s1: i2s@2009c000 { |
e04920d9 RS |
234 | compatible = "nxp,lpc3220-i2s"; |
235 | reg = <0x2009C000 0x1000>; | |
236 | }; | |
237 | ||
c70426f1 RS |
238 | /* UART5 first since it is the default console, ttyS0 */ |
239 | uart5: serial@40090000 { | |
240 | /* actually, ns16550a w/ 64 byte fifos! */ | |
241 | compatible = "nxp,lpc3220-uart"; | |
242 | reg = <0x40090000 0x1000>; | |
b715802f | 243 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; |
c70426f1 | 244 | reg-shift = <2>; |
93898eb7 | 245 | clocks = <&clk LPC32XX_CLK_UART5>; |
c70426f1 RS |
246 | status = "disabled"; |
247 | }; | |
248 | ||
e04920d9 | 249 | uart3: serial@40080000 { |
c70426f1 | 250 | compatible = "nxp,lpc3220-uart"; |
e04920d9 | 251 | reg = <0x40080000 0x1000>; |
b715802f | 252 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; |
c70426f1 | 253 | reg-shift = <2>; |
93898eb7 | 254 | clocks = <&clk LPC32XX_CLK_UART3>; |
c70426f1 | 255 | status = "disabled"; |
e04920d9 RS |
256 | }; |
257 | ||
258 | uart4: serial@40088000 { | |
c70426f1 | 259 | compatible = "nxp,lpc3220-uart"; |
e04920d9 | 260 | reg = <0x40088000 0x1000>; |
b715802f | 261 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; |
c70426f1 | 262 | reg-shift = <2>; |
93898eb7 | 263 | clocks = <&clk LPC32XX_CLK_UART4>; |
c70426f1 | 264 | status = "disabled"; |
e04920d9 RS |
265 | }; |
266 | ||
267 | uart6: serial@40098000 { | |
c70426f1 | 268 | compatible = "nxp,lpc3220-uart"; |
e04920d9 | 269 | reg = <0x40098000 0x1000>; |
b715802f | 270 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; |
c70426f1 | 271 | reg-shift = <2>; |
93898eb7 | 272 | clocks = <&clk LPC32XX_CLK_UART6>; |
c70426f1 | 273 | status = "disabled"; |
e04920d9 RS |
274 | }; |
275 | ||
1c8e6dc5 | 276 | i2c1: i2c@400a0000 { |
e04920d9 RS |
277 | compatible = "nxp,pnx-i2c"; |
278 | reg = <0x400A0000 0x100>; | |
9b8ad3fb VZ |
279 | interrupt-parent = <&sic1>; |
280 | interrupts = <19 IRQ_TYPE_LEVEL_LOW>; | |
e04920d9 RS |
281 | #address-cells = <1>; |
282 | #size-cells = <0>; | |
283 | pnx,timeout = <0x64>; | |
93898eb7 | 284 | clocks = <&clk LPC32XX_CLK_I2C1>; |
e04920d9 RS |
285 | }; |
286 | ||
1c8e6dc5 | 287 | i2c2: i2c@400a8000 { |
e04920d9 RS |
288 | compatible = "nxp,pnx-i2c"; |
289 | reg = <0x400A8000 0x100>; | |
9b8ad3fb VZ |
290 | interrupt-parent = <&sic1>; |
291 | interrupts = <18 IRQ_TYPE_LEVEL_LOW>; | |
e04920d9 RS |
292 | #address-cells = <1>; |
293 | #size-cells = <0>; | |
294 | pnx,timeout = <0x64>; | |
93898eb7 | 295 | clocks = <&clk LPC32XX_CLK_I2C2>; |
e04920d9 RS |
296 | }; |
297 | ||
1c8e6dc5 | 298 | mpwm: mpwm@400e8000 { |
b7d41c93 AB |
299 | compatible = "nxp,lpc3220-motor-pwm"; |
300 | reg = <0x400E8000 0x78>; | |
301 | status = "disabled"; | |
302 | #pwm-cells = <2>; | |
303 | }; | |
e04920d9 RS |
304 | }; |
305 | ||
306 | fab { | |
307 | #address-cells = <1>; | |
308 | #size-cells = <1>; | |
309 | compatible = "simple-bus"; | |
310 | ranges = <0x20000000 0x20000000 0x30000000>; | |
311 | ||
fe86131f VZ |
312 | /* System Control Block */ |
313 | scb { | |
314 | compatible = "simple-bus"; | |
315 | ranges = <0x0 0x040004000 0x00001000>; | |
316 | #address-cells = <1>; | |
317 | #size-cells = <1>; | |
318 | ||
319 | clk: clock-controller@0 { | |
320 | compatible = "nxp,lpc3220-clk"; | |
321 | reg = <0x00 0x114>; | |
322 | #clock-cells = <1>; | |
323 | ||
324 | clocks = <&xtal_32k>, <&xtal>; | |
325 | clock-names = "xtal_32k", "xtal"; | |
c17e9377 VZ |
326 | |
327 | assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>; | |
328 | assigned-clock-rates = <208000000>; | |
fe86131f VZ |
329 | }; |
330 | }; | |
331 | ||
e04920d9 RS |
332 | mic: interrupt-controller@40008000 { |
333 | compatible = "nxp,lpc3220-mic"; | |
9b8ad3fb | 334 | reg = <0x40008000 0x4000>; |
e04920d9 | 335 | interrupt-controller; |
e04920d9 RS |
336 | #interrupt-cells = <2>; |
337 | }; | |
338 | ||
9b8ad3fb VZ |
339 | sic1: interrupt-controller@4000c000 { |
340 | compatible = "nxp,lpc3220-sic"; | |
341 | reg = <0x4000c000 0x4000>; | |
342 | interrupt-controller; | |
343 | #interrupt-cells = <2>; | |
344 | ||
345 | interrupt-parent = <&mic>; | |
346 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>, | |
347 | <30 IRQ_TYPE_LEVEL_LOW>; | |
348 | }; | |
349 | ||
350 | sic2: interrupt-controller@40010000 { | |
351 | compatible = "nxp,lpc3220-sic"; | |
352 | reg = <0x40010000 0x4000>; | |
353 | interrupt-controller; | |
354 | #interrupt-cells = <2>; | |
355 | ||
356 | interrupt-parent = <&mic>; | |
357 | interrupts = <1 IRQ_TYPE_LEVEL_LOW>, | |
358 | <31 IRQ_TYPE_LEVEL_LOW>; | |
359 | }; | |
360 | ||
e04920d9 | 361 | uart1: serial@40014000 { |
ac5ced91 | 362 | compatible = "nxp,lpc3220-hsuart"; |
e04920d9 | 363 | reg = <0x40014000 0x1000>; |
b715802f | 364 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; |
ac5ced91 | 365 | status = "disabled"; |
e04920d9 RS |
366 | }; |
367 | ||
368 | uart2: serial@40018000 { | |
ac5ced91 | 369 | compatible = "nxp,lpc3220-hsuart"; |
e04920d9 | 370 | reg = <0x40018000 0x1000>; |
b715802f | 371 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; |
ac5ced91 | 372 | status = "disabled"; |
e04920d9 RS |
373 | }; |
374 | ||
ac5ced91 RS |
375 | uart7: serial@4001c000 { |
376 | compatible = "nxp,lpc3220-hsuart"; | |
377 | reg = <0x4001c000 0x1000>; | |
b715802f | 378 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; |
ac5ced91 | 379 | status = "disabled"; |
e04920d9 RS |
380 | }; |
381 | ||
25de7c96 | 382 | rtc: rtc@40024000 { |
e04920d9 RS |
383 | compatible = "nxp,lpc3220-rtc"; |
384 | reg = <0x40024000 0x1000>; | |
9b8ad3fb VZ |
385 | interrupt-parent = <&sic1>; |
386 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; | |
93898eb7 | 387 | clocks = <&clk LPC32XX_CLK_RTC>; |
e04920d9 RS |
388 | }; |
389 | ||
390 | gpio: gpio@40028000 { | |
391 | compatible = "nxp,lpc3220-gpio"; | |
392 | reg = <0x40028000 0x1000>; | |
a035254a RS |
393 | gpio-controller; |
394 | #gpio-cells = <3>; /* bank, pin, flags */ | |
e04920d9 RS |
395 | }; |
396 | ||
1c8e6dc5 | 397 | timer4: timer@4002c000 { |
c1aa7007 VZ |
398 | compatible = "nxp,lpc3220-timer"; |
399 | reg = <0x4002C000 0x1000>; | |
b715802f | 400 | interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
93898eb7 VZ |
401 | clocks = <&clk LPC32XX_CLK_TIMER4>; |
402 | clock-names = "timerclk"; | |
c1aa7007 VZ |
403 | status = "disabled"; |
404 | }; | |
405 | ||
406 | timer5: timer@40030000 { | |
407 | compatible = "nxp,lpc3220-timer"; | |
408 | reg = <0x40030000 0x1000>; | |
b715802f | 409 | interrupts = <4 IRQ_TYPE_LEVEL_LOW>; |
93898eb7 VZ |
410 | clocks = <&clk LPC32XX_CLK_TIMER5>; |
411 | clock-names = "timerclk"; | |
c1aa7007 VZ |
412 | status = "disabled"; |
413 | }; | |
414 | ||
1c8e6dc5 | 415 | watchdog: watchdog@4003c000 { |
e04920d9 RS |
416 | compatible = "nxp,pnx4008-wdt"; |
417 | reg = <0x4003C000 0x1000>; | |
93898eb7 | 418 | clocks = <&clk LPC32XX_CLK_WDOG>; |
e04920d9 RS |
419 | }; |
420 | ||
c1aa7007 VZ |
421 | timer0: timer@40044000 { |
422 | compatible = "nxp,lpc3220-timer"; | |
423 | reg = <0x40044000 0x1000>; | |
93898eb7 VZ |
424 | clocks = <&clk LPC32XX_CLK_TIMER0>; |
425 | clock-names = "timerclk"; | |
b715802f | 426 | interrupts = <16 IRQ_TYPE_LEVEL_LOW>; |
c1aa7007 VZ |
427 | }; |
428 | ||
e04920d9 RS |
429 | /* |
430 | * TSC vs. ADC: Since those two share the same | |
431 | * hardware, you need to choose from one of the | |
432 | * following two and do 'status = "okay";' for one of | |
433 | * them | |
434 | */ | |
435 | ||
25de7c96 | 436 | adc: adc@40048000 { |
e04920d9 RS |
437 | compatible = "nxp,lpc3220-adc"; |
438 | reg = <0x40048000 0x1000>; | |
9b8ad3fb VZ |
439 | interrupt-parent = <&sic1>; |
440 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; | |
93898eb7 | 441 | clocks = <&clk LPC32XX_CLK_ADC>; |
cb85a9e5 | 442 | status = "disabled"; |
e04920d9 RS |
443 | }; |
444 | ||
25de7c96 | 445 | tsc: tsc@40048000 { |
e04920d9 RS |
446 | compatible = "nxp,lpc3220-tsc"; |
447 | reg = <0x40048000 0x1000>; | |
9b8ad3fb VZ |
448 | interrupt-parent = <&sic1>; |
449 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; | |
93898eb7 | 450 | clocks = <&clk LPC32XX_CLK_ADC>; |
cb85a9e5 | 451 | status = "disabled"; |
e04920d9 RS |
452 | }; |
453 | ||
1c8e6dc5 | 454 | timer1: timer@4004c000 { |
c1aa7007 VZ |
455 | compatible = "nxp,lpc3220-timer"; |
456 | reg = <0x4004C000 0x1000>; | |
b715802f | 457 | interrupts = <17 IRQ_TYPE_LEVEL_LOW>; |
93898eb7 VZ |
458 | clocks = <&clk LPC32XX_CLK_TIMER1>; |
459 | clock-names = "timerclk"; | |
c1aa7007 VZ |
460 | }; |
461 | ||
25de7c96 | 462 | key: key@40050000 { |
e04920d9 RS |
463 | compatible = "nxp,lpc3220-key"; |
464 | reg = <0x40050000 0x1000>; | |
ca7536d1 | 465 | clocks = <&clk LPC32XX_CLK_KEY>; |
3f6fa94d VZ |
466 | interrupt-parent = <&sic1>; |
467 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; | |
a6d1be0e | 468 | status = "disabled"; |
e04920d9 RS |
469 | }; |
470 | ||
c1aa7007 VZ |
471 | timer2: timer@40058000 { |
472 | compatible = "nxp,lpc3220-timer"; | |
473 | reg = <0x40058000 0x1000>; | |
b715802f | 474 | interrupts = <18 IRQ_TYPE_LEVEL_LOW>; |
93898eb7 VZ |
475 | clocks = <&clk LPC32XX_CLK_TIMER2>; |
476 | clock-names = "timerclk"; | |
c1aa7007 VZ |
477 | status = "disabled"; |
478 | }; | |
479 | ||
1c8e6dc5 | 480 | pwm1: pwm@4005c000 { |
de639854 | 481 | compatible = "nxp,lpc3220-pwm"; |
2a6c6563 | 482 | reg = <0x4005C000 0x4>; |
93898eb7 | 483 | clocks = <&clk LPC32XX_CLK_PWM1>; |
1754906f SL |
484 | assigned-clocks = <&clk LPC32XX_CLK_PWM1>; |
485 | assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; | |
2a6c6563 VZ |
486 | status = "disabled"; |
487 | }; | |
488 | ||
1c8e6dc5 | 489 | pwm2: pwm@4005c004 { |
2a6c6563 VZ |
490 | compatible = "nxp,lpc3220-pwm"; |
491 | reg = <0x4005C004 0x4>; | |
93898eb7 | 492 | clocks = <&clk LPC32XX_CLK_PWM2>; |
1754906f SL |
493 | assigned-clocks = <&clk LPC32XX_CLK_PWM2>; |
494 | assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; | |
de639854 APS |
495 | status = "disabled"; |
496 | }; | |
c1aa7007 VZ |
497 | |
498 | timer3: timer@40060000 { | |
499 | compatible = "nxp,lpc3220-timer"; | |
500 | reg = <0x40060000 0x1000>; | |
b715802f | 501 | interrupts = <19 IRQ_TYPE_LEVEL_LOW>; |
93898eb7 VZ |
502 | clocks = <&clk LPC32XX_CLK_TIMER3>; |
503 | clock-names = "timerclk"; | |
c1aa7007 VZ |
504 | status = "disabled"; |
505 | }; | |
e04920d9 RS |
506 | }; |
507 | }; | |
508 | }; |