]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - arch/arm/boot/dts/ls1021a.dtsi
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'mvebu-fixes-4.17-2' of git://git.infradead.org/linux-mvebu into fixes
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / ls1021a.dtsi
CommitLineData
7239280c
JL		 1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "skeleton64.dtsi"
49#include <dt-bindings/interrupt-controller/arm-gic.h>
4d9e9cbb 50#include <dt-bindings/thermal/thermal.h>
7239280c
JL		 51
52/ {
53 compatible = "fsl,ls1021a";
54 interrupt-parent = <&gic>;
55
56 aliases {
816aa61c 57 crypto = &crypto;
d69cb5d7
CM		 58 ethernet0 = &enet0;
59 ethernet1 = &enet1;
60 ethernet2 = &enet2;
7239280c
JL		 61 serial0 = &lpuart0;
62 serial1 = &lpuart1;
63 serial2 = &lpuart2;
64 serial3 = &lpuart3;
65 serial4 = &lpuart4;
66 serial5 = &lpuart5;
67 sysclk = &sysclk;
68 };
69
70 cpus {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
4d9e9cbb 74 cpu0: cpu@f00 {
7239280c
JL		 75 compatible = "arm,cortex-a7";
76 device_type = "cpu";
77 reg = <0xf00>;
b6f5e701 78 clocks = <&clockgen 1 0>;
4d9e9cbb 79 #cooling-cells = <2>;
7239280c
JL		 80 };
81
4d9e9cbb 82 cpu1: cpu@f01 {
7239280c
JL		 83 compatible = "arm,cortex-a7";
84 device_type = "cpu";
85 reg = <0xf01>;
b6f5e701 86 clocks = <&clockgen 1 0>;
7239280c
JL		 87 };
88 };
89
b6f5e701
YT		 90 sysclk: sysclk {
91 compatible = "fixed-clock";
92 #clock-cells = <0>;
93 clock-frequency = <100000000>;
94 clock-output-names = "sysclk";
95 };
96
7239280c
JL		 97 timer {
98 compatible = "arm,armv7-timer";
99 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
103 };
104
105 pmu {
106 compatible = "arm,cortex-a7-pmu";
107 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
6742139b 109 interrupt-affinity = <&cpu0>, <&cpu1>;
7239280c
JL		 110 };
111
7eaec553
RV		 112 reboot {
113 compatible = "syscon-reboot";
114 regmap = <&dcfg>;
115 offset = <0xb0>;
116 mask = <0x02>;
7239280c
JL		 117 };
118
119 soc {
120 compatible = "simple-bus";
121 #address-cells = <2>;
122 #size-cells = <2>;
123 device_type = "soc";
124 interrupt-parent = <&gic>;
125 ranges;
126
127 gic: interrupt-controller@1400000 {
387720c9 128 compatible = "arm,gic-400", "arm,cortex-a7-gic";
7239280c
JL		 129 #interrupt-cells = <3>;
130 interrupt-controller;
131 reg = <0x0 0x1401000 0x0 0x1000>,
387720c9 132 <0x0 0x1402000 0x0 0x2000>,
7239280c
JL		 133 <0x0 0x1404000 0x0 0x2000>,
134 <0x0 0x1406000 0x0 0x2000>;
135 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
136
137 };
138
f4a458fd 139 msi1: msi-controller@1570e00 {
c9041ea3 140 compatible = "fsl,ls1021a-msi";
f4a458fd
ML		 141 reg = <0x0 0x1570e00 0x0 0x8>;
142 msi-controller;
143 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
144 };
145
146 msi2: msi-controller@1570e08 {
c9041ea3 147 compatible = "fsl,ls1021a-msi";
f4a458fd
ML		 148 reg = <0x0 0x1570e08 0x0 0x8>;
149 msi-controller;
150 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
151 };
152
7239280c
JL		 153 ifc: ifc@1530000 {
154 compatible = "fsl,ifc", "simple-bus";
155 reg = <0x0 0x1530000 0x0 0x10000>;
156 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
157 };
158
159 dcfg: dcfg@1ee0000 {
160 compatible = "fsl,ls1021a-dcfg", "syscon";
161 reg = <0x0 0x1ee0000 0x0 0x10000>;
162 big-endian;
163 };
164
85f8ee78
SL		 165 qspi: quadspi@1550000 {
166 compatible = "fsl,ls1021a-qspi";
167 #address-cells = <1>;
168 #size-cells = <0>;
169 reg = <0x0 0x1550000 0x0 0x10000>,
170 <0x0 0x40000000 0x0 0x40000000>;
171 reg-names = "QuadSPI", "QuadSPI-memory";
172 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
173 clock-names = "qspi_en", "qspi";
174 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
175 big-endian;
176 status = "disabled";
177 };
178
7239280c 179 esdhc: esdhc@1560000 {
d5c7b4d5 180 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
7239280c
JL		 181 reg = <0x0 0x1560000 0x0 0x10000>;
182 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
183 clock-frequency = <0>;
184 voltage-ranges = <1800 1800 3300 3300>;
185 sdhci,auto-cmd12;
186 big-endian;
187 bus-width = <4>;
188 status = "disabled";
189 };
190
318f05e5
TY		 191 sata: sata@3200000 {
192 compatible = "fsl,ls1021a-ahci";
193 reg = <0x0 0x3200000 0x0 0x10000>,
194 <0x0 0x20220520 0x0 0x4>;
195 reg-names = "ahci", "sata-ecc";
196 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 197 clocks = <&clockgen 4 1>;
318f05e5
TY		 198 dma-coherent;
199 status = "disabled";
200 };
201
7239280c
JL		 202 scfg: scfg@1570000 {
203 compatible = "fsl,ls1021a-scfg", "syscon";
204 reg = <0x0 0x1570000 0x0 0x10000>;
4fe6be0f 205 big-endian;
7239280c
JL		 206 };
207
816aa61c
HG		 208 crypto: crypto@1700000 {
209 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
210 fsl,sec-era = <7>;
211 #address-cells = <1>;
212 #size-cells = <1>;
213 reg = <0x0 0x1700000 0x0 0x100000>;
214 ranges = <0x0 0x0 0x1700000 0x100000>;
215 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
216
217 sec_jr0: jr@10000 {
218 compatible = "fsl,sec-v5.0-job-ring",
219 "fsl,sec-v4.0-job-ring";
220 reg = <0x10000 0x10000>;
221 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
222 };
223
224 sec_jr1: jr@20000 {
225 compatible = "fsl,sec-v5.0-job-ring",
226 "fsl,sec-v4.0-job-ring";
227 reg = <0x20000 0x10000>;
228 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
229 };
230
231 sec_jr2: jr@30000 {
232 compatible = "fsl,sec-v5.0-job-ring",
233 "fsl,sec-v4.0-job-ring";
234 reg = <0x30000 0x10000>;
235 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
236 };
237
238 sec_jr3: jr@40000 {
239 compatible = "fsl,sec-v5.0-job-ring",
240 "fsl,sec-v4.0-job-ring";
241 reg = <0x40000 0x10000>;
242 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
243 };
244
245 };
246
7239280c 247 clockgen: clocking@1ee1000 {
b6f5e701
YT		 248 compatible = "fsl,ls1021a-clockgen";
249 reg = <0x0 0x1ee1000 0x0 0x1000>;
250 #clock-cells = <2>;
251 clocks = <&sysclk>;
7239280c
JL		 252 };
253
4d9e9cbb
HJ		 254 tmu: tmu@1f00000 {
255 compatible = "fsl,qoriq-tmu";
256 reg = <0x0 0x1f00000 0x0 0x10000>;
257 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
258 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
259 fsl,tmu-calibration = <0x00000000 0x0000000f
260 0x00000001 0x00000017
261 0x00000002 0x0000001e
262 0x00000003 0x00000026
263 0x00000004 0x0000002e
264 0x00000005 0x00000035
265 0x00000006 0x0000003d
266 0x00000007 0x00000044
267 0x00000008 0x0000004c
268 0x00000009 0x00000053
269 0x0000000a 0x0000005b
270 0x0000000b 0x00000064
271
272 0x00010000 0x00000011
273 0x00010001 0x0000001c
274 0x00010002 0x00000024
275 0x00010003 0x0000002b
276 0x00010004 0x00000034
277 0x00010005 0x00000039
278 0x00010006 0x00000042
279 0x00010007 0x0000004c
280 0x00010008 0x00000051
281 0x00010009 0x0000005a
282 0x0001000a 0x00000063
283
284 0x00020000 0x00000013
285 0x00020001 0x00000019
286 0x00020002 0x00000024
287 0x00020003 0x0000002c
288 0x00020004 0x00000035
289 0x00020005 0x0000003d
290 0x00020006 0x00000046
291 0x00020007 0x00000050
292 0x00020008 0x00000059
293
294 0x00030000 0x00000002
295 0x00030001 0x0000000d
296 0x00030002 0x00000019
297 0x00030003 0x00000024>;
298 #thermal-sensor-cells = <1>;
299 };
300
301 thermal-zones {
302 cpu_thermal: cpu-thermal {
303 polling-delay-passive = <1000>;
304 polling-delay = <5000>;
305
306 thermal-sensors = <&tmu 0>;
307
308 trips {
309 cpu_alert: cpu-alert {
310 temperature = <85000>;
311 hysteresis = <2000>;
312 type = "passive";
313 };
314 cpu_crit: cpu-crit {
315 temperature = <95000>;
316 hysteresis = <2000>;
317 type = "critical";
318 };
319 };
320
321 cooling-maps {
322 map0 {
323 trip = <&cpu_alert>;
324 cooling-device =
325 <&cpu0 THERMAL_NO_LIMIT
326 THERMAL_NO_LIMIT>;
327 };
328 };
329 };
330 };
331
7239280c 332 dspi0: dspi@2100000 {
c47d6e38 333 compatible = "fsl,ls1021a-v1.0-dspi";
7239280c
JL		 334 #address-cells = <1>;
335 #size-cells = <0>;
336 reg = <0x0 0x2100000 0x0 0x10000>;
337 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
338 clock-names = "dspi";
b6f5e701 339 clocks = <&clockgen 4 1>;
5b9f967c 340 spi-num-chipselects = <6>;
7239280c
JL		 341 big-endian;
342 status = "disabled";
343 };
344
345 dspi1: dspi@2110000 {
c47d6e38 346 compatible = "fsl,ls1021a-v1.0-dspi";
7239280c
JL		 347 #address-cells = <1>;
348 #size-cells = <0>;
349 reg = <0x0 0x2110000 0x0 0x10000>;
350 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
351 clock-names = "dspi";
b6f5e701 352 clocks = <&clockgen 4 1>;
5b9f967c 353 spi-num-chipselects = <6>;
7239280c
JL		 354 big-endian;
355 status = "disabled";
356 };
357
358 i2c0: i2c@2180000 {
359 compatible = "fsl,vf610-i2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 reg = <0x0 0x2180000 0x0 0x10000>;
363 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
364 clock-names = "i2c";
b6f5e701 365 clocks = <&clockgen 4 1>;
7239280c
JL		 366 status = "disabled";
367 };
368
369 i2c1: i2c@2190000 {
370 compatible = "fsl,vf610-i2c";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 reg = <0x0 0x2190000 0x0 0x10000>;
374 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
375 clock-names = "i2c";
b6f5e701 376 clocks = <&clockgen 4 1>;
7239280c
JL		 377 status = "disabled";
378 };
379
380 i2c2: i2c@21a0000 {
381 compatible = "fsl,vf610-i2c";
382 #address-cells = <1>;
383 #size-cells = <0>;
384 reg = <0x0 0x21a0000 0x0 0x10000>;
385 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
386 clock-names = "i2c";
b6f5e701 387 clocks = <&clockgen 4 1>;
7239280c
JL		 388 status = "disabled";
389 };
390
391 uart0: serial@21c0500 {
392 compatible = "fsl,16550-FIFO64", "ns16550a";
393 reg = <0x0 0x21c0500 0x0 0x100>;
394 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
395 clock-frequency = <0>;
396 fifo-size = <15>;
397 status = "disabled";
398 };
399
400 uart1: serial@21c0600 {
401 compatible = "fsl,16550-FIFO64", "ns16550a";
402 reg = <0x0 0x21c0600 0x0 0x100>;
403 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
404 clock-frequency = <0>;
405 fifo-size = <15>;
406 status = "disabled";
407 };
408
409 uart2: serial@21d0500 {
410 compatible = "fsl,16550-FIFO64", "ns16550a";
411 reg = <0x0 0x21d0500 0x0 0x100>;
412 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
413 clock-frequency = <0>;
414 fifo-size = <15>;
415 status = "disabled";
416 };
417
418 uart3: serial@21d0600 {
419 compatible = "fsl,16550-FIFO64", "ns16550a";
420 reg = <0x0 0x21d0600 0x0 0x100>;
421 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
422 clock-frequency = <0>;
423 fifo-size = <15>;
424 status = "disabled";
425 };
426
c54dd442
LG		 427 gpio0: gpio@2300000 {
428 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
429 reg = <0x0 0x2300000 0x0 0x10000>;
430 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
431 gpio-controller;
432 #gpio-cells = <2>;
433 interrupt-controller;
434 #interrupt-cells = <2>;
435 };
436
437 gpio1: gpio@2310000 {
438 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
439 reg = <0x0 0x2310000 0x0 0x10000>;
440 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
441 gpio-controller;
442 #gpio-cells = <2>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
445 };
446
447 gpio2: gpio@2320000 {
448 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
449 reg = <0x0 0x2320000 0x0 0x10000>;
450 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
451 gpio-controller;
452 #gpio-cells = <2>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
455 };
456
457 gpio3: gpio@2330000 {
458 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
459 reg = <0x0 0x2330000 0x0 0x10000>;
460 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
461 gpio-controller;
462 #gpio-cells = <2>;
463 interrupt-controller;
464 #interrupt-cells = <2>;
465 };
466
7239280c
JL		 467 lpuart0: serial@2950000 {
468 compatible = "fsl,ls1021a-lpuart";
469 reg = <0x0 0x2950000 0x0 0x1000>;
470 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&sysclk>;
472 clock-names = "ipg";
473 status = "disabled";
474 };
475
476 lpuart1: serial@2960000 {
477 compatible = "fsl,ls1021a-lpuart";
478 reg = <0x0 0x2960000 0x0 0x1000>;
479 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 480 clocks = <&clockgen 4 1>;
7239280c
JL		 481 clock-names = "ipg";
482 status = "disabled";
483 };
484
485 lpuart2: serial@2970000 {
486 compatible = "fsl,ls1021a-lpuart";
487 reg = <0x0 0x2970000 0x0 0x1000>;
488 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 489 clocks = <&clockgen 4 1>;
7239280c
JL		 490 clock-names = "ipg";
491 status = "disabled";
492 };
493
494 lpuart3: serial@2980000 {
495 compatible = "fsl,ls1021a-lpuart";
496 reg = <0x0 0x2980000 0x0 0x1000>;
497 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 498 clocks = <&clockgen 4 1>;
7239280c
JL		 499 clock-names = "ipg";
500 status = "disabled";
501 };
502
503 lpuart4: serial@2990000 {
504 compatible = "fsl,ls1021a-lpuart";
505 reg = <0x0 0x2990000 0x0 0x1000>;
506 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 507 clocks = <&clockgen 4 1>;
7239280c
JL		 508 clock-names = "ipg";
509 status = "disabled";
510 };
511
512 lpuart5: serial@29a0000 {
513 compatible = "fsl,ls1021a-lpuart";
514 reg = <0x0 0x29a0000 0x0 0x1000>;
515 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 516 clocks = <&clockgen 4 1>;
7239280c
JL		 517 clock-names = "ipg";
518 status = "disabled";
519 };
520
521 wdog0: watchdog@2ad0000 {
522 compatible = "fsl,imx21-wdt";
523 reg = <0x0 0x2ad0000 0x0 0x10000>;
524 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 525 clocks = <&clockgen 4 1>;
7239280c
JL		 526 clock-names = "wdog-en";
527 big-endian;
528 };
529
530 sai1: sai@2b50000 {
50897cb6 531 #sound-dai-cells = <0>;
7239280c
JL		 532 compatible = "fsl,vf610-sai";
533 reg = <0x0 0x2b50000 0x0 0x10000>;
534 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701
YT		 535 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
536 <&clockgen 4 1>, <&clockgen 4 1>;
50897cb6 537 clock-names = "bus", "mclk1", "mclk2", "mclk3";
7239280c
JL		 538 dma-names = "tx", "rx";
539 dmas = <&edma0 1 47>,
540 <&edma0 1 46>;
7239280c
JL		 541 status = "disabled";
542 };
543
544 sai2: sai@2b60000 {
50897cb6 545 #sound-dai-cells = <0>;
7239280c
JL		 546 compatible = "fsl,vf610-sai";
547 reg = <0x0 0x2b60000 0x0 0x10000>;
548 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701
YT		 549 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
550 <&clockgen 4 1>, <&clockgen 4 1>;
50897cb6 551 clock-names = "bus", "mclk1", "mclk2", "mclk3";
7239280c
JL		 552 dma-names = "tx", "rx";
553 dmas = <&edma0 1 45>,
554 <&edma0 1 44>;
7239280c
JL		 555 status = "disabled";
556 };
557
558 edma0: edma@2c00000 {
559 #dma-cells = <2>;
560 compatible = "fsl,vf610-edma";
561 reg = <0x0 0x2c00000 0x0 0x10000>,
562 <0x0 0x2c10000 0x0 0x10000>,
563 <0x0 0x2c20000 0x0 0x10000>;
564 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
566 interrupt-names = "edma-tx", "edma-err";
567 dma-channels = <32>;
568 big-endian;
569 clock-names = "dmamux0", "dmamux1";
b6f5e701
YT		 570 clocks = <&clockgen 4 1>,
571 <&clockgen 4 1>;
7239280c
JL		 572 };
573
ab0087df
MY		 574 dcu: dcu@2ce0000 {
575 compatible = "fsl,ls1021a-dcu";
576 reg = <0x0 0x2ce0000 0x0 0x10000>;
577 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701
YT		 578 clocks = <&clockgen 4 0>,
579 <&clockgen 4 0>;
5d01e99e 580 clock-names = "dcu", "pix";
ab0087df
MY		 581 big-endian;
582 status = "disabled";
583 };
584
7239280c
JL		 585 mdio0: mdio@2d24000 {
586 compatible = "gianfar";
587 device_type = "mdio";
588 #address-cells = <1>;
589 #size-cells = <0>;
55711961
EH		 590 reg = <0x0 0x2d24000 0x0 0x4000>,
591 <0x0 0x2d10030 0x0 0x4>;
7239280c
JL		 592 };
593
3db66fdc
YL		 594 ptp_clock@2d10e00 {
595 compatible = "fsl,etsec-ptp";
596 reg = <0x0 0x2d10e00 0x0 0xb0>;
597 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
598 fsl,tclk-period = <5>;
599 fsl,tmr-prsc = <2>;
600 fsl,tmr-add = <0xaaaaaaab>;
bdba5017 601 fsl,tmr-fiper1 = <999999995>;
3db66fdc
YL		 602 fsl,tmr-fiper2 = <99990>;
603 fsl,max-adj = <499999999>;
604 };
605
d69cb5d7
CM		 606 enet0: ethernet@2d10000 {
607 compatible = "fsl,etsec2";
608 device_type = "network";
609 #address-cells = <2>;
610 #size-cells = <2>;
611 interrupt-parent = <&gic>;
612 model = "eTSEC";
613 fsl,magic-packet;
614 ranges;
70b5ea97 615 dma-coherent;
d69cb5d7
CM		 616
617 queue-group@2d10000 {
618 #address-cells = <2>;
619 #size-cells = <2>;
620 reg = <0x0 0x2d10000 0x0 0x1000>;
621 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
624 };
625
626 queue-group@2d14000 {
627 #address-cells = <2>;
628 #size-cells = <2>;
629 reg = <0x0 0x2d14000 0x0 0x1000>;
630 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
633 };
634 };
635
636 enet1: ethernet@2d50000 {
637 compatible = "fsl,etsec2";
638 device_type = "network";
639 #address-cells = <2>;
640 #size-cells = <2>;
641 interrupt-parent = <&gic>;
642 model = "eTSEC";
643 ranges;
70b5ea97 644 dma-coherent;
d69cb5d7
CM		 645
646 queue-group@2d50000 {
647 #address-cells = <2>;
648 #size-cells = <2>;
649 reg = <0x0 0x2d50000 0x0 0x1000>;
650 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
653 };
654
655 queue-group@2d54000 {
656 #address-cells = <2>;
657 #size-cells = <2>;
658 reg = <0x0 0x2d54000 0x0 0x1000>;
659 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
662 };
663 };
664
665 enet2: ethernet@2d90000 {
666 compatible = "fsl,etsec2";
667 device_type = "network";
668 #address-cells = <2>;
669 #size-cells = <2>;
670 interrupt-parent = <&gic>;
671 model = "eTSEC";
672 ranges;
70b5ea97 673 dma-coherent;
d69cb5d7
CM		 674
675 queue-group@2d90000 {
676 #address-cells = <2>;
677 #size-cells = <2>;
678 reg = <0x0 0x2d90000 0x0 0x1000>;
679 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
682 };
683
684 queue-group@2d94000 {
685 #address-cells = <2>;
686 #size-cells = <2>;
687 reg = <0x0 0x2d94000 0x0 0x1000>;
688 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
691 };
692 };
693
31fa7631 694 usb2: usb@8600000 {
7239280c
JL		 695 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
696 reg = <0x0 0x8600000 0x0 0x1000>;
697 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
698 dr_mode = "host";
699 phy_type = "ulpi";
700 };
701
31fa7631 702 usb3: usb3@3100000 {
7239280c
JL		 703 compatible = "snps,dwc3";
704 reg = <0x0 0x3100000 0x0 0x10000>;
705 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
706 dr_mode = "host";
607e266c 707 snps,quirk-frame-length-adjustment = <0x20>;
6f0808c4 708 snps,dis_rxdet_inp3_quirk;
7239280c 709 };
bc7abb47
ML		 710
711 pcie@3400000 {
712 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
713 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
714 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
715 reg-names = "regs", "config";
716 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
717 fsl,pcie-scfg = <&scfg 0>;
718 #address-cells = <3>;
719 #size-cells = <2>;
720 device_type = "pci";
721 num-lanes = <4>;
722 bus-range = <0x0 0xff>;
723 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
724 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
df301588 725 msi-parent = <&msi1>, <&msi2>;
bc7abb47
ML		 726 #interrupt-cells = <1>;
727 interrupt-map-mask = <0 0 0 7>;
728 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
729 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
730 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
731 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
732 };
733
734 pcie@3500000 {
735 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
736 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
737 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
738 reg-names = "regs", "config";
739 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
740 fsl,pcie-scfg = <&scfg 1>;
741 #address-cells = <3>;
742 #size-cells = <2>;
743 device_type = "pci";
744 num-lanes = <4>;
745 bus-range = <0x0 0xff>;
746 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
747 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
df301588 748 msi-parent = <&msi1>, <&msi2>;
bc7abb47
ML		 749 #interrupt-cells = <1>;
750 interrupt-map-mask = <0 0 0 7>;
751 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
752 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
753 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
754 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
755 };
fa2edcfb
PB		 756
757 can0: can@2a70000 {
758 compatible = "fsl,ls1021ar2-flexcan";
759 reg = <0x0 0x2a70000 0x0 0x1000>;
760 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
762 clock-names = "ipg", "per";
763 big-endian;
764 };
765
766 can1: can@2a80000 {
767 compatible = "fsl,ls1021ar2-flexcan";
768 reg = <0x0 0x2a80000 0x0 0x1000>;
769 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
771 clock-names = "ipg", "per";
772 big-endian;
773 };
774
775 can2: can@2a90000 {
776 compatible = "fsl,ls1021ar2-flexcan";
777 reg = <0x0 0x2a90000 0x0 0x1000>;
778 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
780 clock-names = "ipg", "per";
781 big-endian;
782 };
783
784 can3: can@2aa0000 {
785 compatible = "fsl,ls1021ar2-flexcan";
786 reg = <0x0 0x2aa0000 0x0 0x1000>;
787 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
789 clock-names = "ipg", "per";
790 big-endian;
791 };
35090321
RV		 792
793 ocram1: sram@10000000 {
794 compatible = "mmio-sram";
795 reg = <0x0 0x10000000 0x0 0x10000>;
796 #address-cells = <1>;
797 #size-cells = <1>;
798 ranges = <0x0 0x0 0x10000000 0x10000>;
799 };
800
801 ocram2: sram@10010000 {
802 compatible = "mmio-sram";
803 reg = <0x0 0x10010000 0x0 0x10000>;
804 #address-cells = <1>;
805 #size-cells = <1>;
806 ranges = <0x0 0x0 0x10010000 0x10000>;
807 };
7239280c
JL		 808 };
809};
Ubuntu Eoan Linux kernel mirror