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7239280c JL |
1 | /* |
2 | * Copyright 2013-2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This file is dual-licensed: you can use it either under the terms | |
5 | * of the GPL or the X11 license, at your option. Note that this dual | |
6 | * licensing only applies to this file, and not this project as a | |
7 | * whole. | |
8 | * | |
9 | * a) This file is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This file is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public | |
20 | * License along with this file; if not, write to the Free | |
21 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, | |
22 | * MA 02110-1301 USA | |
23 | * | |
24 | * Or, alternatively, | |
25 | * | |
26 | * b) Permission is hereby granted, free of charge, to any person | |
27 | * obtaining a copy of this software and associated documentation | |
28 | * files (the "Software"), to deal in the Software without | |
29 | * restriction, including without limitation the rights to use, | |
30 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
31 | * sell copies of the Software, and to permit persons to whom the | |
32 | * Software is furnished to do so, subject to the following | |
33 | * conditions: | |
34 | * | |
35 | * The above copyright notice and this permission notice shall be | |
36 | * included in all copies or substantial portions of the Software. | |
37 | * | |
38 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
39 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
40 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
41 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
42 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
43 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
44 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
45 | * OTHER DEALINGS IN THE SOFTWARE. | |
46 | */ | |
47 | ||
48 | #include "skeleton64.dtsi" | |
49 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
50 | ||
51 | / { | |
52 | compatible = "fsl,ls1021a"; | |
53 | interrupt-parent = <&gic>; | |
54 | ||
55 | aliases { | |
56 | serial0 = &lpuart0; | |
57 | serial1 = &lpuart1; | |
58 | serial2 = &lpuart2; | |
59 | serial3 = &lpuart3; | |
60 | serial4 = &lpuart4; | |
61 | serial5 = &lpuart5; | |
62 | sysclk = &sysclk; | |
63 | }; | |
64 | ||
65 | cpus { | |
66 | #address-cells = <1>; | |
67 | #size-cells = <0>; | |
68 | ||
69 | cpu@f00 { | |
70 | compatible = "arm,cortex-a7"; | |
71 | device_type = "cpu"; | |
72 | reg = <0xf00>; | |
73 | clocks = <&cluster1_clk>; | |
74 | }; | |
75 | ||
76 | cpu@f01 { | |
77 | compatible = "arm,cortex-a7"; | |
78 | device_type = "cpu"; | |
79 | reg = <0xf01>; | |
80 | clocks = <&cluster1_clk>; | |
81 | }; | |
82 | }; | |
83 | ||
84 | timer { | |
85 | compatible = "arm,armv7-timer"; | |
86 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
87 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
88 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
89 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
90 | }; | |
91 | ||
92 | pmu { | |
93 | compatible = "arm,cortex-a7-pmu"; | |
94 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
95 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; | |
96 | }; | |
97 | ||
98 | soc { | |
99 | compatible = "simple-bus"; | |
100 | #address-cells = <2>; | |
101 | #size-cells = <2>; | |
102 | device_type = "soc"; | |
103 | interrupt-parent = <&gic>; | |
104 | ranges; | |
105 | ||
106 | gic: interrupt-controller@1400000 { | |
107 | compatible = "arm,cortex-a7-gic"; | |
108 | #interrupt-cells = <3>; | |
109 | interrupt-controller; | |
110 | reg = <0x0 0x1401000 0x0 0x1000>, | |
111 | <0x0 0x1402000 0x0 0x1000>, | |
112 | <0x0 0x1404000 0x0 0x2000>, | |
113 | <0x0 0x1406000 0x0 0x2000>; | |
114 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
115 | ||
116 | }; | |
117 | ||
118 | ifc: ifc@1530000 { | |
119 | compatible = "fsl,ifc", "simple-bus"; | |
120 | reg = <0x0 0x1530000 0x0 0x10000>; | |
121 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
122 | }; | |
123 | ||
124 | dcfg: dcfg@1ee0000 { | |
125 | compatible = "fsl,ls1021a-dcfg", "syscon"; | |
126 | reg = <0x0 0x1ee0000 0x0 0x10000>; | |
127 | big-endian; | |
128 | }; | |
129 | ||
130 | esdhc: esdhc@1560000 { | |
131 | compatible = "fsl,esdhc"; | |
132 | reg = <0x0 0x1560000 0x0 0x10000>; | |
133 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
134 | clock-frequency = <0>; | |
135 | voltage-ranges = <1800 1800 3300 3300>; | |
136 | sdhci,auto-cmd12; | |
137 | big-endian; | |
138 | bus-width = <4>; | |
139 | status = "disabled"; | |
140 | }; | |
141 | ||
142 | scfg: scfg@1570000 { | |
143 | compatible = "fsl,ls1021a-scfg", "syscon"; | |
144 | reg = <0x0 0x1570000 0x0 0x10000>; | |
145 | }; | |
146 | ||
147 | clockgen: clocking@1ee1000 { | |
148 | #address-cells = <1>; | |
149 | #size-cells = <1>; | |
150 | ranges = <0x0 0x0 0x1ee1000 0x10000>; | |
151 | ||
152 | sysclk: sysclk { | |
153 | compatible = "fixed-clock"; | |
154 | #clock-cells = <0>; | |
155 | clock-output-names = "sysclk"; | |
156 | }; | |
157 | ||
158 | cga_pll1: pll@800 { | |
159 | compatible = "fsl,qoriq-core-pll-2.0"; | |
160 | #clock-cells = <1>; | |
161 | reg = <0x800 0x10>; | |
162 | clocks = <&sysclk>; | |
163 | clock-output-names = "cga-pll1", "cga-pll1-div2", | |
164 | "cga-pll1-div4"; | |
165 | }; | |
166 | ||
167 | platform_clk: pll@c00 { | |
168 | compatible = "fsl,qoriq-core-pll-2.0"; | |
169 | #clock-cells = <1>; | |
170 | reg = <0xc00 0x10>; | |
171 | clocks = <&sysclk>; | |
172 | clock-output-names = "platform-clk", "platform-clk-div2"; | |
173 | }; | |
174 | ||
175 | cluster1_clk: clk0c0@0 { | |
176 | compatible = "fsl,qoriq-core-mux-2.0"; | |
177 | #clock-cells = <0>; | |
178 | reg = <0x0 0x10>; | |
179 | clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; | |
180 | clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; | |
181 | clock-output-names = "cluster1-clk"; | |
182 | }; | |
183 | }; | |
184 | ||
185 | dspi0: dspi@2100000 { | |
186 | compatible = "fsl,vf610-dspi"; | |
187 | #address-cells = <1>; | |
188 | #size-cells = <0>; | |
189 | reg = <0x0 0x2100000 0x0 0x10000>; | |
190 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
191 | clock-names = "dspi"; | |
192 | clocks = <&platform_clk 1>; | |
193 | spi-num-chipselects = <5>; | |
194 | big-endian; | |
195 | status = "disabled"; | |
196 | }; | |
197 | ||
198 | dspi1: dspi@2110000 { | |
199 | compatible = "fsl,vf610-dspi"; | |
200 | #address-cells = <1>; | |
201 | #size-cells = <0>; | |
202 | reg = <0x0 0x2110000 0x0 0x10000>; | |
203 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
204 | clock-names = "dspi"; | |
205 | clocks = <&platform_clk 1>; | |
206 | spi-num-chipselects = <5>; | |
207 | big-endian; | |
208 | status = "disabled"; | |
209 | }; | |
210 | ||
211 | i2c0: i2c@2180000 { | |
212 | compatible = "fsl,vf610-i2c"; | |
213 | #address-cells = <1>; | |
214 | #size-cells = <0>; | |
215 | reg = <0x0 0x2180000 0x0 0x10000>; | |
216 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
217 | clock-names = "i2c"; | |
218 | clocks = <&platform_clk 1>; | |
219 | status = "disabled"; | |
220 | }; | |
221 | ||
222 | i2c1: i2c@2190000 { | |
223 | compatible = "fsl,vf610-i2c"; | |
224 | #address-cells = <1>; | |
225 | #size-cells = <0>; | |
226 | reg = <0x0 0x2190000 0x0 0x10000>; | |
227 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
228 | clock-names = "i2c"; | |
229 | clocks = <&platform_clk 1>; | |
230 | status = "disabled"; | |
231 | }; | |
232 | ||
233 | i2c2: i2c@21a0000 { | |
234 | compatible = "fsl,vf610-i2c"; | |
235 | #address-cells = <1>; | |
236 | #size-cells = <0>; | |
237 | reg = <0x0 0x21a0000 0x0 0x10000>; | |
238 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
239 | clock-names = "i2c"; | |
240 | clocks = <&platform_clk 1>; | |
241 | status = "disabled"; | |
242 | }; | |
243 | ||
244 | uart0: serial@21c0500 { | |
245 | compatible = "fsl,16550-FIFO64", "ns16550a"; | |
246 | reg = <0x0 0x21c0500 0x0 0x100>; | |
247 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
248 | clock-frequency = <0>; | |
249 | fifo-size = <15>; | |
250 | status = "disabled"; | |
251 | }; | |
252 | ||
253 | uart1: serial@21c0600 { | |
254 | compatible = "fsl,16550-FIFO64", "ns16550a"; | |
255 | reg = <0x0 0x21c0600 0x0 0x100>; | |
256 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
257 | clock-frequency = <0>; | |
258 | fifo-size = <15>; | |
259 | status = "disabled"; | |
260 | }; | |
261 | ||
262 | uart2: serial@21d0500 { | |
263 | compatible = "fsl,16550-FIFO64", "ns16550a"; | |
264 | reg = <0x0 0x21d0500 0x0 0x100>; | |
265 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
266 | clock-frequency = <0>; | |
267 | fifo-size = <15>; | |
268 | status = "disabled"; | |
269 | }; | |
270 | ||
271 | uart3: serial@21d0600 { | |
272 | compatible = "fsl,16550-FIFO64", "ns16550a"; | |
273 | reg = <0x0 0x21d0600 0x0 0x100>; | |
274 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
275 | clock-frequency = <0>; | |
276 | fifo-size = <15>; | |
277 | status = "disabled"; | |
278 | }; | |
279 | ||
280 | lpuart0: serial@2950000 { | |
281 | compatible = "fsl,ls1021a-lpuart"; | |
282 | reg = <0x0 0x2950000 0x0 0x1000>; | |
283 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
284 | clocks = <&sysclk>; | |
285 | clock-names = "ipg"; | |
286 | status = "disabled"; | |
287 | }; | |
288 | ||
289 | lpuart1: serial@2960000 { | |
290 | compatible = "fsl,ls1021a-lpuart"; | |
291 | reg = <0x0 0x2960000 0x0 0x1000>; | |
292 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
293 | clocks = <&platform_clk 1>; | |
294 | clock-names = "ipg"; | |
295 | status = "disabled"; | |
296 | }; | |
297 | ||
298 | lpuart2: serial@2970000 { | |
299 | compatible = "fsl,ls1021a-lpuart"; | |
300 | reg = <0x0 0x2970000 0x0 0x1000>; | |
301 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
302 | clocks = <&platform_clk 1>; | |
303 | clock-names = "ipg"; | |
304 | status = "disabled"; | |
305 | }; | |
306 | ||
307 | lpuart3: serial@2980000 { | |
308 | compatible = "fsl,ls1021a-lpuart"; | |
309 | reg = <0x0 0x2980000 0x0 0x1000>; | |
310 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
311 | clocks = <&platform_clk 1>; | |
312 | clock-names = "ipg"; | |
313 | status = "disabled"; | |
314 | }; | |
315 | ||
316 | lpuart4: serial@2990000 { | |
317 | compatible = "fsl,ls1021a-lpuart"; | |
318 | reg = <0x0 0x2990000 0x0 0x1000>; | |
319 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
320 | clocks = <&platform_clk 1>; | |
321 | clock-names = "ipg"; | |
322 | status = "disabled"; | |
323 | }; | |
324 | ||
325 | lpuart5: serial@29a0000 { | |
326 | compatible = "fsl,ls1021a-lpuart"; | |
327 | reg = <0x0 0x29a0000 0x0 0x1000>; | |
328 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
329 | clocks = <&platform_clk 1>; | |
330 | clock-names = "ipg"; | |
331 | status = "disabled"; | |
332 | }; | |
333 | ||
334 | wdog0: watchdog@2ad0000 { | |
335 | compatible = "fsl,imx21-wdt"; | |
336 | reg = <0x0 0x2ad0000 0x0 0x10000>; | |
337 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
338 | clocks = <&platform_clk 1>; | |
339 | clock-names = "wdog-en"; | |
340 | big-endian; | |
341 | }; | |
342 | ||
343 | sai1: sai@2b50000 { | |
344 | compatible = "fsl,vf610-sai"; | |
345 | reg = <0x0 0x2b50000 0x0 0x10000>; | |
346 | interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; | |
347 | clocks = <&platform_clk 1>; | |
348 | clock-names = "sai"; | |
349 | dma-names = "tx", "rx"; | |
350 | dmas = <&edma0 1 47>, | |
351 | <&edma0 1 46>; | |
352 | big-endian; | |
353 | status = "disabled"; | |
354 | }; | |
355 | ||
356 | sai2: sai@2b60000 { | |
357 | compatible = "fsl,vf610-sai"; | |
358 | reg = <0x0 0x2b60000 0x0 0x10000>; | |
359 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; | |
360 | clocks = <&platform_clk 1>; | |
361 | clock-names = "sai"; | |
362 | dma-names = "tx", "rx"; | |
363 | dmas = <&edma0 1 45>, | |
364 | <&edma0 1 44>; | |
365 | big-endian; | |
366 | status = "disabled"; | |
367 | }; | |
368 | ||
369 | edma0: edma@2c00000 { | |
370 | #dma-cells = <2>; | |
371 | compatible = "fsl,vf610-edma"; | |
372 | reg = <0x0 0x2c00000 0x0 0x10000>, | |
373 | <0x0 0x2c10000 0x0 0x10000>, | |
374 | <0x0 0x2c20000 0x0 0x10000>; | |
375 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
376 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
377 | interrupt-names = "edma-tx", "edma-err"; | |
378 | dma-channels = <32>; | |
379 | big-endian; | |
380 | clock-names = "dmamux0", "dmamux1"; | |
381 | clocks = <&platform_clk 1>, | |
382 | <&platform_clk 1>; | |
383 | }; | |
384 | ||
385 | mdio0: mdio@2d24000 { | |
386 | compatible = "gianfar"; | |
387 | device_type = "mdio"; | |
388 | #address-cells = <1>; | |
389 | #size-cells = <0>; | |
390 | reg = <0x0 0x2d24000 0x0 0x4000>; | |
391 | }; | |
392 | ||
393 | usb@8600000 { | |
394 | compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; | |
395 | reg = <0x0 0x8600000 0x0 0x1000>; | |
396 | interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; | |
397 | dr_mode = "host"; | |
398 | phy_type = "ulpi"; | |
399 | }; | |
400 | ||
401 | usb3@3100000 { | |
402 | compatible = "snps,dwc3"; | |
403 | reg = <0x0 0x3100000 0x0 0x10000>; | |
404 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | |
405 | dr_mode = "host"; | |
406 | }; | |
407 | }; | |
408 | }; |