projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 68b3f115 | 1 | // SPDX-License-Identifier: GPL-2.0 OR MIT |
| 6b112e24 CC |
2 | /* |
| 3 | * Copyright 2014 Carlo Caione <carlo@caione.org> | |
| 6b112e24 CC |
4 | */ |
| 5 | ||
| 7a16f06b | 6 | #include "meson.dtsi" |
| 6b112e24 CC |
7 | |
| 8 | / { | |
| 9 | model = "Amlogic Meson6 SoC"; | |
| 10 | compatible = "amlogic,meson6"; | |
| 11 | ||
| 6b112e24 CC |
12 | cpus { |
| 13 | #address-cells = <1>; | |
| 14 | #size-cells = <0>; | |
| 15 | ||
| 16 | cpu@200 { | |
| 17 | device_type = "cpu"; | |
| 18 | compatible = "arm,cortex-a9"; | |
| 550ab390 | 19 | next-level-cache = <&L2>; |
| 6b112e24 CC |
20 | reg = <0x200>; |
| 21 | }; | |
| 22 | ||
| 23 | cpu@201 { | |
| 24 | device_type = "cpu"; | |
| 25 | compatible = "arm,cortex-a9"; | |
| 550ab390 | 26 | next-level-cache = <&L2>; |
| 6b112e24 CC |
27 | reg = <0x201>; |
| 28 | }; | |
| 29 | }; | |
| 30 | ||
| 2fc6f377 MB |
31 | apb2: bus@d0000000 { |
| 32 | compatible = "simple-bus"; | |
| 33 | reg = <0xd0000000 0x40000>; | |
| 34 | #address-cells = <1>; | |
| 35 | #size-cells = <1>; | |
| 36 | ranges = <0x0 0xd0000000 0x40000>; | |
| 37 | }; | |
| 38 | ||
| ec9b5916 NA |
39 | xtal: xtal-clk { |
| 40 | compatible = "fixed-clock"; | |
| 41 | clock-frequency = <24000000>; | |
| 42 | clock-output-names = "xtal"; | |
| 43 | #clock-cells = <0>; | |
| 44 | }; | |
| 45 | ||
| 6b112e24 CC |
46 | clk81: clk@0 { |
| 47 | #clock-cells = <0>; | |
| 48 | compatible = "fixed-clock"; | |
| 49 | clock-frequency = <200000000>; | |
| 50 | }; | |
| 51 | }; /* end of / */ | |
| ec9b5916 | 52 | |
| 2cb51a8d MB |
53 | &efuse { |
| 54 | status = "disabled"; | |
| 55 | }; | |
| ec9b5916 | 56 | |
| 7b141abe MB |
57 | &timer_abcde { |
| 58 | clocks = <&xtal>, <&clk81>; | |
| 59 | clock-names = "xtal", "pclk"; | |
| 60 | }; | |
| 61 | ||
| ec9b5916 NA |
62 | &uart_AO { |
| 63 | clocks = <&xtal>, <&clk81>, <&clk81>; | |
| 64 | clock-names = "xtal", "pclk", "baud"; | |
| 65 | }; | |
| 66 | ||
| 67 | &uart_A { | |
| 68 | clocks = <&xtal>, <&clk81>, <&clk81>; | |
| 69 | clock-names = "xtal", "pclk", "baud"; | |
| 70 | }; | |
| 71 | ||
| 72 | &uart_B { | |
| 73 | clocks = <&xtal>, <&clk81>, <&clk81>; | |
| 74 | clock-names = "xtal", "pclk", "baud"; | |
| 75 | }; | |
| 76 | ||
| 77 | &uart_C { | |
| 78 | clocks = <&xtal>, <&clk81>, <&clk81>; | |
| 79 | clock-names = "xtal", "pclk", "baud"; | |
| 80 | }; |