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448e7ede JJ |
1 | /* moxart.dtsi - Device Tree Include file for MOXA ART family SoC |
2 | * | |
3 | * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com> | |
4 | * | |
5 | * Licensed under GPLv2 or later. | |
6 | */ | |
7 | ||
8 | /include/ "skeleton.dtsi" | |
9 | ||
10 | / { | |
11 | compatible = "moxa,moxart"; | |
12 | model = "MOXART"; | |
13 | interrupt-parent = <&intc>; | |
14 | ||
15 | cpus { | |
16 | #address-cells = <1>; | |
17 | #size-cells = <0>; | |
18 | ||
19 | cpu@0 { | |
20 | device_type = "cpu"; | |
21 | compatible = "faraday,fa526"; | |
22 | reg = <0>; | |
23 | }; | |
24 | }; | |
25 | ||
26 | clocks { | |
27 | #address-cells = <1>; | |
28 | #size-cells = <0>; | |
448e7ede JJ |
29 | }; |
30 | ||
31 | soc { | |
32 | compatible = "simple-bus"; | |
33 | #address-cells = <1>; | |
34 | #size-cells = <1>; | |
35 | reg = <0x90000000 0x10000000>; | |
36 | ranges; | |
37 | ||
38 | intc: interrupt-controller@98800000 { | |
39 | compatible = "moxa,moxart-ic"; | |
40 | reg = <0x98800000 0x38>; | |
41 | interrupt-controller; | |
42 | #interrupt-cells = <2>; | |
43 | interrupt-mask = <0x00080000>; | |
44 | }; | |
45 | ||
46 | clk_pll: clk_pll@98100000 { | |
47 | compatible = "moxa,moxart-pll-clock"; | |
48 | #clock-cells = <0>; | |
49 | reg = <0x98100000 0x34>; | |
50 | }; | |
51 | ||
52 | clk_apb: clk_apb@98100000 { | |
53 | compatible = "moxa,moxart-apb-clock"; | |
54 | #clock-cells = <0>; | |
55 | reg = <0x98100000 0x34>; | |
56 | clocks = <&clk_pll>; | |
57 | }; | |
58 | ||
59 | timer: timer@98400000 { | |
60 | compatible = "moxa,moxart-timer"; | |
61 | reg = <0x98400000 0x42>; | |
62 | interrupts = <19 1>; | |
63 | clocks = <&clk_apb>; | |
64 | }; | |
65 | ||
66 | gpio: gpio@98700000 { | |
67 | gpio-controller; | |
68 | #gpio-cells = <2>; | |
69 | compatible = "moxa,moxart-gpio"; | |
70 | reg = <0x98700000 0xC>; | |
71 | }; | |
72 | ||
73 | rtc: rtc { | |
74 | compatible = "moxa,moxart-rtc"; | |
75 | gpio-rtc-sclk = <&gpio 5 0>; | |
76 | gpio-rtc-data = <&gpio 6 0>; | |
77 | gpio-rtc-reset = <&gpio 7 0>; | |
78 | }; | |
79 | ||
80 | dma: dma@90500000 { | |
81 | compatible = "moxa,moxart-dma"; | |
82 | reg = <0x90500080 0x40>; | |
83 | interrupts = <24 0>; | |
84 | #dma-cells = <1>; | |
85 | }; | |
86 | ||
87 | watchdog: watchdog@98500000 { | |
88 | compatible = "moxa,moxart-watchdog"; | |
89 | reg = <0x98500000 0x10>; | |
90 | clocks = <&clk_apb>; | |
91 | }; | |
92 | ||
93 | sdhci: sdhci@98e00000 { | |
94 | compatible = "moxa,moxart-sdhci"; | |
95 | reg = <0x98e00000 0x5C>; | |
96 | interrupts = <5 0>; | |
97 | clocks = <&clk_apb>; | |
98 | dmas = <&dma 5>, | |
99 | <&dma 5>; | |
100 | dma-names = "tx", "rx"; | |
101 | status = "disabled"; | |
102 | }; | |
103 | ||
104 | mdio0: mdio@90900090 { | |
105 | compatible = "moxa,moxart-mdio"; | |
106 | reg = <0x90900090 0x8>; | |
107 | #address-cells = <1>; | |
108 | #size-cells = <0>; | |
109 | status = "disabled"; | |
110 | }; | |
111 | ||
112 | mdio1: mdio@92000090 { | |
113 | compatible = "moxa,moxart-mdio"; | |
114 | reg = <0x92000090 0x8>; | |
115 | #address-cells = <1>; | |
116 | #size-cells = <0>; | |
117 | status = "disabled"; | |
118 | }; | |
119 | ||
120 | mac0: mac@90900000 { | |
121 | compatible = "moxa,moxart-mac"; | |
122 | reg = <0x90900000 0x90>; | |
123 | interrupts = <25 0>; | |
124 | phy-handle = <ðphy0>; | |
125 | phy-mode = "mii"; | |
126 | status = "disabled"; | |
127 | }; | |
128 | ||
129 | mac1: mac@92000000 { | |
130 | compatible = "moxa,moxart-mac"; | |
131 | reg = <0x92000000 0x90>; | |
132 | interrupts = <27 0>; | |
133 | phy-handle = <ðphy1>; | |
134 | phy-mode = "mii"; | |
135 | status = "disabled"; | |
136 | }; | |
137 | ||
138 | uart0: uart@98200000 { | |
139 | compatible = "ns16550a"; | |
140 | reg = <0x98200000 0x20>; | |
141 | interrupts = <31 8>; | |
142 | reg-shift = <2>; | |
143 | reg-io-width = <4>; | |
144 | clock-frequency = <14745600>; | |
145 | status = "disabled"; | |
146 | }; | |
147 | }; | |
148 | }; |