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Merge remote-tracking branch 'mkp-scsi/fixes' into fixes
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1/*
2 * Copyright (C) 2015 ARM Limited
3 *
4 * Author: Vladimir Murzin <vladimir.murzin@arm.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include "armv7-m.dtsi"
46
47/ {
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48 #address-cells = <1>;
49 #size-cells = <1>;
50
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51 oscclk0: clk-osc0 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <50000000>;
55 };
56
57 oscclk1: clk-osc1 {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <24576000>;
61 };
62
63 oscclk2: clk-osc2 {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <25000000>;
67 };
68
69 cfgclk: clk-cfg {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <5000000>;
73 };
74
75 spicfgclk: clk-spicfg {
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <75000000>;
79 };
80
81 sysclk: clk-sys {
82 compatible = "fixed-factor-clock";
83 clocks = <&oscclk0>;
84 #clock-cells = <0>;
85 clock-div = <2>;
86 clock-mult = <1>;
87 };
88
89 audmclk: clk-audm {
90 compatible = "fixed-factor-clock";
91 clocks = <&oscclk1>;
92 #clock-cells = <0>;
93 clock-div = <2>;
94 clock-mult = <1>;
95 };
96
97 audsclk: clk-auds {
98 compatible = "fixed-factor-clock";
99 clocks = <&oscclk1>;
100 #clock-cells = <0>;
101 clock-div = <8>;
102 clock-mult = <1>;
103 };
104
105 spiclcd: clk-cpiclcd {
106 compatible = "fixed-factor-clock";
107 clocks = <&oscclk0>;
108 #clock-cells = <0>;
109 clock-div = <2>;
110 clock-mult = <1>;
111 };
112
113 spicon: clk-spicon {
114 compatible = "fixed-factor-clock";
115 clocks = <&oscclk0>;
116 #clock-cells = <0>;
117 clock-div = <2>;
118 clock-mult = <1>;
119 };
120
121 i2cclcd: clk-i2cclcd {
122 compatible = "fixed-factor-clock";
123 clocks = <&oscclk0>;
124 #clock-cells = <0>;
125 clock-div = <2>;
126 clock-mult = <1>;
127 };
128
129 i2caud: clk-i2caud {
130 compatible = "fixed-factor-clock";
131 clocks = <&oscclk0>;
132 #clock-cells = <0>;
133 clock-div = <2>;
134 clock-mult = <1>;
135 };
136
137 soc {
138 compatible = "simple-bus";
139 ranges;
140
141 apb@40000000 {
142 compatible = "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 ranges = <0 0x40000000 0x10000>;
146
147 timer0: mps2-timer0@0 {
148 compatible = "arm,mps2-timer";
149 reg = <0x0 0x1000>;
150 interrupts = <8>;
151 clocks = <&sysclk>;
152 status = "disabled";
153 };
154
155 timer1: mps2-timer1@1000 {
156 compatible = "arm,mps2-timer";
157 reg = <0x1000 0x1000>;
158 interrupts = <9>;
159 clocks = <&sysclk>;
160 status = "disabled";
161 };
162
163 timer2: dual-timer@2000 {
164 compatible = "arm,sp804";
165 reg = <0x2000 0x1000>;
166 clocks = <&sysclk>;
167 interrupts = <10>;
168 status = "disabled";
169 };
170
171 uart0: serial@4000 {
172 compatible = "arm,mps2-uart";
173 reg = <0x4000 0x1000>;
174 interrupts = <0 1 12>;
175 clocks = <&sysclk>;
176 status = "disabled";
177 };
178
179 uart1: serial@5000 {
180 compatible = "arm,mps2-uart";
181 reg = <0x5000 0x1000>;
182 interrupts = <2 3 12>;
183 clocks = <&sysclk>;
184 status = "disabled";
185 };
186
187 uart2: serial@6000 {
188 compatible = "arm,mps2-uart";
189 reg = <0x6000 0x1000>;
190 interrupts = <4 5 12>;
191 clocks = <&sysclk>;
192 status = "disabled";
193 };
194
195 wdt: watchdog@8000 {
196 compatible = "arm,sp805", "arm,primecell";
197 arm,primecell-periphid = <0x00141805>;
198 reg = <0x8000 0x1000>;
199 interrupts = <0>;
200 clocks = <&sysclk>;
201 clock-names = "apb_pclk";
202 status = "disabled";
203 };
204 };
205 };
206
207 fpga@40020000 {
208 compatible = "simple-bus";
209 #address-cells = <1>;
210 #size-cells = <1>;
211 ranges = <0 0x40020000 0x10000>;
212
213 fpgaio@8000 {
214 compatible = "syscon", "simple-mfd";
215 reg = <0x8000 0x10>;
216
217 led0 {
218 compatible = "register-bit-led";
219 offset = <0x0>;
220 mask = <0x01>;
221 label = "userled:0";
222 linux,default-trigger = "heartbeat";
223 default-state = "on";
224 };
225
226 led1 {
227 compatible = "register-bit-led";
228 offset = <0x0>;
229 mask = <0x02>;
230 label = "userled:1";
231 linux,default-trigger = "usr";
232 default-state = "off";
233 };
234 };
235 };
236
237 smb {
238 compatible = "simple-bus";
239 #address-cells = <2>;
240 #size-cells = <1>;
241 ranges = <0 0 0x40200000 0x10000>,
242 <1 0 0xa0000000 0x10000>;
243 };
244};