[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / mt2701.dtsi

/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Erin.Lo <erin.lo@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"

/ {
	compatible = "mediatek,mt2701";
	interrupt-parent = <&sysirq>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt81xx-tz-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		trustzone-bootinfo@80002000 {
			compatible = "mediatek,trustzone-bootinfo";
			reg = <0 0x80002000 0 0x1000>;
		};
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	rtc_clk: dummy32k {
		compatible = "fixed-clock";
		clock-frequency = <32000>;
		#clock-cells = <0>;
	};

	clk26m: oscillator@0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	rtc32k: oscillator@1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32000>;
		clock-output-names = "rtc32k";
	};

	thermal-zones {
		cpu_thermal: cpu_thermal {
			polling-delay-passive = <1000>; /* milliseconds */
			polling-delay = <1000>; /* milliseconds */

			thermal-sensors = <&thermal 0>;
			sustainable-power = <1000>;

			trips {
				threshold: trip-point@0 {
					temperature = <68000>;
					hysteresis = <2000>;
					type = "passive";
				};

				target: trip-point@1 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit@0 {
					temperature = <115000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	topckgen: syscon@10000000 {
		compatible = "mediatek,mt2701-topckgen", "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
		compatible = "mediatek,mt2701-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pericfg: syscon@10003000 {
		compatible = "mediatek,mt2701-pericfg", "syscon";
		reg = <0 0x10003000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	syscfg_pctl_a: syscfg@10005000 {
		compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
		reg = <0 0x10005000 0 0x1000>;
	};

	scpsys: scpsys@10006000 {
		compatible = "mediatek,mt2701-scpsys", "syscon";
		#power-domain-cells = <1>;
		reg = <0 0x10006000 0 0x1000>;
		infracfg = <&infracfg>;
		clocks = <&topckgen CLK_TOP_MM_SEL>,
			 <&topckgen CLK_TOP_MFG_SEL>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "mm", "mfg", "ethif";
	};

	watchdog: watchdog@10007000 {
		compatible = "mediatek,mt2701-wdt",
			     "mediatek,mt6589-wdt";
		reg = <0 0x10007000 0 0x100>;
	};

	timer: timer@10008000 {
		compatible = "mediatek,mt2701-timer",
			     "mediatek,mt6577-timer";
		reg = <0 0x10008000 0 0x80>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>, <&rtc_clk>;
		clock-names = "system-clk", "rtc-clk";
	};

	pio: pinctrl@1000b000 {
		compatible = "mediatek,mt2701-pinctrl";
		reg = <0 0x1000b000 0 0x1000>;
		mediatek,pctl-regmap = <&syscfg_pctl_a>;
		pins-are-numbered;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};

	smi_common: smi@1000c000 {
		compatible = "mediatek,mt2701-smi-common";
		reg = <0 0x1000c000 0 0x1000>;
		clocks = <&infracfg CLK_INFRA_SMI>,
			 <&mmsys CLK_MM_SMI_COMMON>,
			 <&infracfg CLK_INFRA_SMI>;
		clock-names = "apb", "smi", "async";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	sysirq: interrupt-controller@10200100 {
		compatible = "mediatek,mt2701-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10200100 0 0x1c>;
	};

	iommu: mmsys_iommu@10205000 {
		compatible = "mediatek,mt2701-m4u";
		reg = <0 0x10205000 0 0x1000>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg CLK_INFRA_M4U>;
		clock-names = "bclk";
		mediatek,larbs = <&larb0 &larb1 &larb2>;
		#iommu-cells = <1>;
	};

	apmixedsys: syscon@10209000 {
		compatible = "mediatek,mt2701-apmixedsys", "syscon";
		reg = <0 0x10209000 0 0x1000>;
		#clock-cells = <1>;
	};

	gic: interrupt-controller@10211000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10211000 0 0x1000>,
		      <0 0x10212000 0 0x2000>,
		      <0 0x10214000 0 0x2000>,
		      <0 0x10216000 0 0x2000>;
	};

	auxadc: adc@11001000 {
		compatible = "mediatek,mt2701-auxadc";
		reg = <0 0x11001000 0 0x1000>;
		clocks = <&pericfg CLK_PERI_AUXADC>;
		clock-names = "main";
		#io-channel-cells = <1>;
		status = "disabled";
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	spi0: spi@1100a000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x1100a000 0 0x100>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI0_SEL>,
			 <&pericfg CLK_PERI_SPI0>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	thermal: thermal@1100b000 {
		#thermal-sensor-cells = <0>;
		compatible = "mediatek,mt2701-thermal";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
		clock-names = "therm", "auxadc";
		resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
		reset-names = "therm";
		mediatek,auxadc = <&auxadc>;
		mediatek,apmixedsys = <&apmixedsys>;
	};

	nandc: nfi@1100d000 {
		compatible = "mediatek,mt2701-nfc";
		reg = <0 0x1100d000 0 0x1000>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI>,
			 <&pericfg CLK_PERI_NFI_PAD>;
		clock-names = "nfi_clk", "pad_clk";
		status = "disabled";
		ecc-engine = <&bch>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	bch: ecc@1100e000 {
		compatible = "mediatek,mt2701-ecc";
		reg = <0 0x1100e000 0 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI_ECC>;
		clock-names = "nfiecc_clk";
		status = "disabled";
	};

	spi1: spi@11016000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x11016000 0 0x100>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI1_SEL>,
			 <&pericfg CLK_PERI_SPI1>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	spi2: spi@11017000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x11017000 0 0x1000>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI2_SEL>,
			 <&pericfg CLK_PERI_SPI2>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	mmsys: syscon@14000000 {
		compatible = "mediatek,mt2701-mmsys", "syscon";
		reg = <0 0x14000000 0 0x1000>;
		#clock-cells = <1>;
	};

	larb0: larb@14010000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x14010000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		clocks = <&mmsys CLK_MM_SMI_LARB0>,
			 <&mmsys CLK_MM_SMI_LARB0>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	imgsys: syscon@15000000 {
		compatible = "mediatek,mt2701-imgsys", "syscon";
		reg = <0 0x15000000 0 0x1000>;
		#clock-cells = <1>;
	};

	larb2: larb@15001000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x15001000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		clocks = <&imgsys CLK_IMG_SMI_COMM>,
			 <&imgsys CLK_IMG_SMI_COMM>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	};

	vdecsys: syscon@16000000 {
		compatible = "mediatek,mt2701-vdecsys", "syscon";
		reg = <0 0x16000000 0 0x1000>;
		#clock-cells = <1>;
	};

	larb1: larb@16010000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x16010000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		clocks = <&vdecsys CLK_VDEC_CKGEN>,
			 <&vdecsys CLK_VDEC_LARB>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
	};

	hifsys: syscon@1a000000 {
		compatible = "mediatek,mt2701-hifsys", "syscon";
		reg = <0 0x1a000000 0 0x1000>;
		#clock-cells = <1>;
	};

	ethsys: syscon@1b000000 {
		compatible = "mediatek,mt2701-ethsys", "syscon";
		reg = <0 0x1b000000 0 0x1000>;
		#clock-cells = <1>;
	};

	bdpsys: syscon@1c000000 {
		compatible = "mediatek,mt2701-bdpsys", "syscon";
		reg = <0 0x1c000000 0 0x1000>;
		#clock-cells = <1>;
	};
};
Commit	Line	Data
74d25721 EL	1	/*
	2	* Copyright (c) 2015 MediaTek Inc.
	3	* Author: Erin.Lo <erin.lo@mediatek.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
adf6eb77	15	#include <dt-bindings/clock/mt2701-clk.h>
9f3746af	16	#include <dt-bindings/power/mt2701-power.h>
74d25721 EL	17	#include <dt-bindings/interrupt-controller/irq.h>
74d25721 EL	18	#include <dt-bindings/interrupt-controller/arm-gic.h>
adf6eb77	19	#include <dt-bindings/reset/mt2701-resets.h>
74d25721	20	#include "skeleton64.dtsi"
8369337e	21	#include "mt2701-pinfunc.h"
74d25721 EL	22
	23	/ {
	24	compatible = "mediatek,mt2701";
	25	interrupt-parent = <&sysirq>;
	26
	27	cpus {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
dfb89528	30	enable-method = "mediatek,mt81xx-tz-smp";
74d25721 EL	31
	32	cpu@0 {
	33	device_type = "cpu";
	34	compatible = "arm,cortex-a7";
	35	reg = <0x0>;
	36	};
	37	cpu@1 {
	38	device_type = "cpu";
	39	compatible = "arm,cortex-a7";
	40	reg = <0x1>;
	41	};
	42	cpu@2 {
	43	device_type = "cpu";
	44	compatible = "arm,cortex-a7";
	45	reg = <0x2>;
	46	};
	47	cpu@3 {
	48	device_type = "cpu";
	49	compatible = "arm,cortex-a7";
	50	reg = <0x3>;
	51	};
	52	};
	53
dfb89528 LY	54	reserved-memory {
	55	#address-cells = <2>;
	56	#size-cells = <2>;
	57	ranges;
	58
	59	trustzone-bootinfo@80002000 {
	60	compatible = "mediatek,trustzone-bootinfo";
	61	reg = <0 0x80002000 0 0x1000>;
	62	};
	63	};
	64
74d25721 EL	65	system_clk: dummy13m {
	66	compatible = "fixed-clock";
	67	clock-frequency = <13000000>;
	68	#clock-cells = <0>;
	69	};
	70
	71	rtc_clk: dummy32k {
	72	compatible = "fixed-clock";
	73	clock-frequency = <32000>;
	74	#clock-cells = <0>;
	75	};
	76
adf6eb77 JL	77	clk26m: oscillator@0 {
	78	compatible = "fixed-clock";
	79	#clock-cells = <0>;
	80	clock-frequency = <26000000>;
	81	clock-output-names = "clk26m";
	82	};
	83
	84	rtc32k: oscillator@1 {
	85	compatible = "fixed-clock";
	86	#clock-cells = <0>;
	87	clock-frequency = <32000>;
	88	clock-output-names = "rtc32k";
	89	};
	90
e348dc74 DC	91	thermal-zones {
	92	cpu_thermal: cpu_thermal {
	93	polling-delay-passive = <1000>; /* milliseconds */
	94	polling-delay = <1000>; /* milliseconds */
	95
	96	thermal-sensors = <&thermal 0>;
	97	sustainable-power = <1000>;
	98
	99	trips {
	100	threshold: trip-point@0 {
	101	temperature = <68000>;
	102	hysteresis = <2000>;
	103	type = "passive";
	104	};
	105
	106	target: trip-point@1 {
	107	temperature = <85000>;
	108	hysteresis = <2000>;
	109	type = "passive";
	110	};
	111
	112	cpu_crit: cpu_crit@0 {
	113	temperature = <115000>;
	114	hysteresis = <2000>;
	115	type = "critical";
	116	};
	117	};
	118	};
	119	};
	120
74d25721 EL	121	timer {
	122	compatible = "arm,armv7-timer";
	123	interrupt-parent = <&gic>;
	124	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	125	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	126	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	127	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	128	};
	129
adf6eb77 JL	130	topckgen: syscon@10000000 {
	131	compatible = "mediatek,mt2701-topckgen", "syscon";
	132	reg = <0 0x10000000 0 0x1000>;
	133	#clock-cells = <1>;
	134	};
	135
	136	infracfg: syscon@10001000 {
	137	compatible = "mediatek,mt2701-infracfg", "syscon";
	138	reg = <0 0x10001000 0 0x1000>;
	139	#clock-cells = <1>;
	140	#reset-cells = <1>;
	141	};
	142
	143	pericfg: syscon@10003000 {
	144	compatible = "mediatek,mt2701-pericfg", "syscon";
	145	reg = <0 0x10003000 0 0x1000>;
	146	#clock-cells = <1>;
	147	#reset-cells = <1>;
	148	};
	149
42e4d6d5 JL	150	syscfg_pctl_a: syscfg@10005000 {
	151	compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
	152	reg = <0 0x10005000 0 0x1000>;
	153	};
	154
9f3746af JL	155	scpsys: scpsys@10006000 {
	156	compatible = "mediatek,mt2701-scpsys", "syscon";
	157	#power-domain-cells = <1>;
	158	reg = <0 0x10006000 0 0x1000>;
	159	infracfg = <&infracfg>;
	160	clocks = <&topckgen CLK_TOP_MM_SEL>,
	161	<&topckgen CLK_TOP_MFG_SEL>,
	162	<&topckgen CLK_TOP_ETHIF_SEL>;
	163	clock-names = "mm", "mfg", "ethif";
	164	};
	165
74d25721 EL	166	watchdog: watchdog@10007000 {
	167	compatible = "mediatek,mt2701-wdt",
	168	"mediatek,mt6589-wdt";
	169	reg = <0 0x10007000 0 0x100>;
	170	};
	171
	172	timer: timer@10008000 {
	173	compatible = "mediatek,mt2701-timer",
	174	"mediatek,mt6577-timer";
	175	reg = <0 0x10008000 0 0x80>;
	176	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
	177	clocks = <&system_clk>, <&rtc_clk>;
	178	clock-names = "system-clk", "rtc-clk";
	179	};
	180
42e4d6d5 JL	181	pio: pinctrl@1000b000 {
	182	compatible = "mediatek,mt2701-pinctrl";
	183	reg = <0 0x1000b000 0 0x1000>;
	184	mediatek,pctl-regmap = <&syscfg_pctl_a>;
	185	pins-are-numbered;
	186	gpio-controller;
	187	#gpio-cells = <2>;
	188	interrupt-controller;
	189	#interrupt-cells = <2>;
	190	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	191	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	192	};
	193
f3cba0f4 HZ	194	smi_common: smi@1000c000 {
	195	compatible = "mediatek,mt2701-smi-common";
	196	reg = <0 0x1000c000 0 0x1000>;
	197	clocks = <&infracfg CLK_INFRA_SMI>,
	198	<&mmsys CLK_MM_SMI_COMMON>,
	199	<&infracfg CLK_INFRA_SMI>;
	200	clock-names = "apb", "smi", "async";
	201	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	202	};
	203
74d25721 EL	204	sysirq: interrupt-controller@10200100 {
	205	compatible = "mediatek,mt2701-sysirq",
	206	"mediatek,mt6577-sysirq";
	207	interrupt-controller;
	208	#interrupt-cells = <3>;
	209	interrupt-parent = <&gic>;
	210	reg = <0 0x10200100 0 0x1c>;
	211	};
	212
f3cba0f4 HZ	213	iommu: mmsys_iommu@10205000 {
	214	compatible = "mediatek,mt2701-m4u";
	215	reg = <0 0x10205000 0 0x1000>;
	216	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
	217	clocks = <&infracfg CLK_INFRA_M4U>;
	218	clock-names = "bclk";
	219	mediatek,larbs = <&larb0 &larb1 &larb2>;
	220	#iommu-cells = <1>;
	221	};
	222
adf6eb77 JL	223	apmixedsys: syscon@10209000 {
	224	compatible = "mediatek,mt2701-apmixedsys", "syscon";
	225	reg = <0 0x10209000 0 0x1000>;
	226	#clock-cells = <1>;
	227	};
	228
74d25721 EL	229	gic: interrupt-controller@10211000 {
	230	compatible = "arm,cortex-a7-gic";
	231	interrupt-controller;
	232	#interrupt-cells = <3>;
	233	interrupt-parent = <&gic>;
	234	reg = <0 0x10211000 0 0x1000>,
387720c9	235	<0 0x10212000 0 0x2000>,
74d25721 EL	236	<0 0x10214000 0 0x2000>,
	237	<0 0x10216000 0 0x2000>;
	238	};
	239
301501d3 ZT	240	auxadc: adc@11001000 {
	241	compatible = "mediatek,mt2701-auxadc";
	242	reg = <0 0x11001000 0 0x1000>;
	243	clocks = <&pericfg CLK_PERI_AUXADC>;
	244	clock-names = "main";
	245	#io-channel-cells = <1>;
	246	status = "disabled";
	247	};
	248
74d25721 EL	249	uart0: serial@11002000 {
	250	compatible = "mediatek,mt2701-uart",
	251	"mediatek,mt6577-uart";
	252	reg = <0 0x11002000 0 0x400>;
	253	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	254	clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
28d6e364 EL	255	clock-names = "baud", "bus";
74d25721 EL	256	status = "disabled";
	257	};
	258
	259	uart1: serial@11003000 {
	260	compatible = "mediatek,mt2701-uart",
	261	"mediatek,mt6577-uart";
	262	reg = <0 0x11003000 0 0x400>;
	263	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	264	clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
28d6e364 EL	265	clock-names = "baud", "bus";
74d25721 EL	266	status = "disabled";
	267	};
	268
	269	uart2: serial@11004000 {
	270	compatible = "mediatek,mt2701-uart",
	271	"mediatek,mt6577-uart";
	272	reg = <0 0x11004000 0 0x400>;
	273	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	274	clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
28d6e364 EL	275	clock-names = "baud", "bus";
74d25721 EL	276	status = "disabled";
	277	};
	278
	279	uart3: serial@11005000 {
	280	compatible = "mediatek,mt2701-uart",
	281	"mediatek,mt6577-uart";
	282	reg = <0 0x11005000 0 0x400>;
	283	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	284	clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
28d6e364 EL	285	clock-names = "baud", "bus";
74d25721 EL	286	status = "disabled";
74d25721 EL	287	};
f235c7e7	288
159f5ae7 LL	289	spi0: spi@1100a000 {
	290	compatible = "mediatek,mt2701-spi";
	291	#address-cells = <1>;
	292	#size-cells = <0>;
	293	reg = <0 0x1100a000 0 0x100>;
	294	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
	295	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	296	<&topckgen CLK_TOP_SPI0_SEL>,
	297	<&pericfg CLK_PERI_SPI0>;
	298	clock-names = "parent-clk", "sel-clk", "spi-clk";
	299	status = "disabled";
	300	};
	301
e348dc74 DC	302	thermal: thermal@1100b000 {
	303	#thermal-sensor-cells = <0>;
	304	compatible = "mediatek,mt2701-thermal";
	305	reg = <0 0x1100b000 0 0x1000>;
	306	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
	307	clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
	308	clock-names = "therm", "auxadc";
	309	resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
	310	reset-names = "therm";
	311	mediatek,auxadc = <&auxadc>;
	312	mediatek,apmixedsys = <&apmixedsys>;
	313	};
	314
111758b7 XL	315	nandc: nfi@1100d000 {
	316	compatible = "mediatek,mt2701-nfc";
	317	reg = <0 0x1100d000 0 0x1000>;
	318	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
	319	clocks = <&pericfg CLK_PERI_NFI>,
	320	<&pericfg CLK_PERI_NFI_PAD>;
	321	clock-names = "nfi_clk", "pad_clk";
	322	status = "disabled";
	323	ecc-engine = <&bch>;
	324	#address-cells = <1>;
	325	#size-cells = <0>;
	326	};
	327
	328	bch: ecc@1100e000 {
	329	compatible = "mediatek,mt2701-ecc";
	330	reg = <0 0x1100e000 0 0x1000>;
	331	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
	332	clocks = <&pericfg CLK_PERI_NFI_ECC>;
	333	clock-names = "nfiecc_clk";
	334	status = "disabled";
	335	};
	336
159f5ae7 LL	337	spi1: spi@11016000 {
	338	compatible = "mediatek,mt2701-spi";
	339	#address-cells = <1>;
	340	#size-cells = <0>;
	341	reg = <0 0x11016000 0 0x100>;
	342	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
	343	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	344	<&topckgen CLK_TOP_SPI1_SEL>,
	345	<&pericfg CLK_PERI_SPI1>;
	346	clock-names = "parent-clk", "sel-clk", "spi-clk";
	347	status = "disabled";
	348	};
	349
	350	spi2: spi@11017000 {
	351	compatible = "mediatek,mt2701-spi";
	352	#address-cells = <1>;
	353	#size-cells = <0>;
	354	reg = <0 0x11017000 0 0x1000>;
	355	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
	356	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	357	<&topckgen CLK_TOP_SPI2_SEL>,
	358	<&pericfg CLK_PERI_SPI2>;
	359	clock-names = "parent-clk", "sel-clk", "spi-clk";
	360	status = "disabled";
	361	};
	362
f235c7e7 JL	363	mmsys: syscon@14000000 {
	364	compatible = "mediatek,mt2701-mmsys", "syscon";
	365	reg = <0 0x14000000 0 0x1000>;
	366	#clock-cells = <1>;
	367	};
	368
f3cba0f4 HZ	369	larb0: larb@14010000 {
	370	compatible = "mediatek,mt2701-smi-larb";
	371	reg = <0 0x14010000 0 0x1000>;
	372	mediatek,smi = <&smi_common>;
	373	clocks = <&mmsys CLK_MM_SMI_LARB0>,
	374	<&mmsys CLK_MM_SMI_LARB0>;
	375	clock-names = "apb", "smi";
	376	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	377	};
	378
f235c7e7 JL	379	imgsys: syscon@15000000 {
	380	compatible = "mediatek,mt2701-imgsys", "syscon";
	381	reg = <0 0x15000000 0 0x1000>;
	382	#clock-cells = <1>;
	383	};
	384
f3cba0f4 HZ	385	larb2: larb@15001000 {
	386	compatible = "mediatek,mt2701-smi-larb";
	387	reg = <0 0x15001000 0 0x1000>;
	388	mediatek,smi = <&smi_common>;
	389	clocks = <&imgsys CLK_IMG_SMI_COMM>,
	390	<&imgsys CLK_IMG_SMI_COMM>;
	391	clock-names = "apb", "smi";
	392	power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	393	};
	394
f235c7e7 JL	395	vdecsys: syscon@16000000 {
	396	compatible = "mediatek,mt2701-vdecsys", "syscon";
	397	reg = <0 0x16000000 0 0x1000>;
	398	#clock-cells = <1>;
	399	};
	400
f3cba0f4 HZ	401	larb1: larb@16010000 {
	402	compatible = "mediatek,mt2701-smi-larb";
	403	reg = <0 0x16010000 0 0x1000>;
	404	mediatek,smi = <&smi_common>;
	405	clocks = <&vdecsys CLK_VDEC_CKGEN>,
	406	<&vdecsys CLK_VDEC_LARB>;
	407	clock-names = "apb", "smi";
	408	power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
	409	};
	410
f235c7e7 JL	411	hifsys: syscon@1a000000 {
	412	compatible = "mediatek,mt2701-hifsys", "syscon";
	413	reg = <0 0x1a000000 0 0x1000>;
	414	#clock-cells = <1>;
	415	};
	416
	417	ethsys: syscon@1b000000 {
	418	compatible = "mediatek,mt2701-ethsys", "syscon";
	419	reg = <0 0x1b000000 0 0x1000>;
	420	#clock-cells = <1>;
	421	};
	422
	423	bdpsys: syscon@1c000000 {
	424	compatible = "mediatek,mt2701-bdpsys", "syscon";
	425	reg = <0 0x1c000000 0 0x1000>;
	426	#clock-cells = <1>;
	427	};
74d25721	428	};