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74d25721 EL |
1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * Author: Erin.Lo <erin.lo@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
adf6eb77 | 15 | #include <dt-bindings/clock/mt2701-clk.h> |
74d25721 EL |
16 | #include <dt-bindings/interrupt-controller/irq.h> |
17 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
adf6eb77 | 18 | #include <dt-bindings/reset/mt2701-resets.h> |
74d25721 | 19 | #include "skeleton64.dtsi" |
8369337e | 20 | #include "mt2701-pinfunc.h" |
74d25721 EL |
21 | |
22 | / { | |
23 | compatible = "mediatek,mt2701"; | |
24 | interrupt-parent = <&sysirq>; | |
25 | ||
26 | cpus { | |
27 | #address-cells = <1>; | |
28 | #size-cells = <0>; | |
dfb89528 | 29 | enable-method = "mediatek,mt81xx-tz-smp"; |
74d25721 EL |
30 | |
31 | cpu@0 { | |
32 | device_type = "cpu"; | |
33 | compatible = "arm,cortex-a7"; | |
34 | reg = <0x0>; | |
35 | }; | |
36 | cpu@1 { | |
37 | device_type = "cpu"; | |
38 | compatible = "arm,cortex-a7"; | |
39 | reg = <0x1>; | |
40 | }; | |
41 | cpu@2 { | |
42 | device_type = "cpu"; | |
43 | compatible = "arm,cortex-a7"; | |
44 | reg = <0x2>; | |
45 | }; | |
46 | cpu@3 { | |
47 | device_type = "cpu"; | |
48 | compatible = "arm,cortex-a7"; | |
49 | reg = <0x3>; | |
50 | }; | |
51 | }; | |
52 | ||
dfb89528 LY |
53 | reserved-memory { |
54 | #address-cells = <2>; | |
55 | #size-cells = <2>; | |
56 | ranges; | |
57 | ||
58 | trustzone-bootinfo@80002000 { | |
59 | compatible = "mediatek,trustzone-bootinfo"; | |
60 | reg = <0 0x80002000 0 0x1000>; | |
61 | }; | |
62 | }; | |
63 | ||
74d25721 EL |
64 | system_clk: dummy13m { |
65 | compatible = "fixed-clock"; | |
66 | clock-frequency = <13000000>; | |
67 | #clock-cells = <0>; | |
68 | }; | |
69 | ||
70 | rtc_clk: dummy32k { | |
71 | compatible = "fixed-clock"; | |
72 | clock-frequency = <32000>; | |
73 | #clock-cells = <0>; | |
74 | }; | |
75 | ||
adf6eb77 JL |
76 | clk26m: oscillator@0 { |
77 | compatible = "fixed-clock"; | |
78 | #clock-cells = <0>; | |
79 | clock-frequency = <26000000>; | |
80 | clock-output-names = "clk26m"; | |
81 | }; | |
82 | ||
83 | rtc32k: oscillator@1 { | |
84 | compatible = "fixed-clock"; | |
85 | #clock-cells = <0>; | |
86 | clock-frequency = <32000>; | |
87 | clock-output-names = "rtc32k"; | |
88 | }; | |
89 | ||
74d25721 EL |
90 | timer { |
91 | compatible = "arm,armv7-timer"; | |
92 | interrupt-parent = <&gic>; | |
93 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
94 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
95 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, | |
96 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
97 | }; | |
98 | ||
8369337e BH |
99 | pio: pinctrl@10005000 { |
100 | compatible = "mediatek,mt2701-pinctrl"; | |
101 | reg = <0 0x1000b000 0 0x1000>; | |
102 | mediatek,pctl-regmap = <&syscfg_pctl_a>; | |
103 | pins-are-numbered; | |
104 | gpio-controller; | |
105 | #gpio-cells = <2>; | |
106 | interrupt-controller; | |
107 | #interrupt-cells = <2>; | |
108 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
109 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
110 | }; | |
111 | ||
112 | syscfg_pctl_a: syscfg@10005000 { | |
113 | compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon"; | |
114 | reg = <0 0x10005000 0 0x1000>; | |
115 | }; | |
116 | ||
adf6eb77 JL |
117 | topckgen: syscon@10000000 { |
118 | compatible = "mediatek,mt2701-topckgen", "syscon"; | |
119 | reg = <0 0x10000000 0 0x1000>; | |
120 | #clock-cells = <1>; | |
121 | }; | |
122 | ||
123 | infracfg: syscon@10001000 { | |
124 | compatible = "mediatek,mt2701-infracfg", "syscon"; | |
125 | reg = <0 0x10001000 0 0x1000>; | |
126 | #clock-cells = <1>; | |
127 | #reset-cells = <1>; | |
128 | }; | |
129 | ||
130 | pericfg: syscon@10003000 { | |
131 | compatible = "mediatek,mt2701-pericfg", "syscon"; | |
132 | reg = <0 0x10003000 0 0x1000>; | |
133 | #clock-cells = <1>; | |
134 | #reset-cells = <1>; | |
135 | }; | |
136 | ||
74d25721 EL |
137 | watchdog: watchdog@10007000 { |
138 | compatible = "mediatek,mt2701-wdt", | |
139 | "mediatek,mt6589-wdt"; | |
140 | reg = <0 0x10007000 0 0x100>; | |
141 | }; | |
142 | ||
143 | timer: timer@10008000 { | |
144 | compatible = "mediatek,mt2701-timer", | |
145 | "mediatek,mt6577-timer"; | |
146 | reg = <0 0x10008000 0 0x80>; | |
147 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; | |
148 | clocks = <&system_clk>, <&rtc_clk>; | |
149 | clock-names = "system-clk", "rtc-clk"; | |
150 | }; | |
151 | ||
152 | sysirq: interrupt-controller@10200100 { | |
153 | compatible = "mediatek,mt2701-sysirq", | |
154 | "mediatek,mt6577-sysirq"; | |
155 | interrupt-controller; | |
156 | #interrupt-cells = <3>; | |
157 | interrupt-parent = <&gic>; | |
158 | reg = <0 0x10200100 0 0x1c>; | |
159 | }; | |
160 | ||
adf6eb77 JL |
161 | apmixedsys: syscon@10209000 { |
162 | compatible = "mediatek,mt2701-apmixedsys", "syscon"; | |
163 | reg = <0 0x10209000 0 0x1000>; | |
164 | #clock-cells = <1>; | |
165 | }; | |
166 | ||
74d25721 EL |
167 | gic: interrupt-controller@10211000 { |
168 | compatible = "arm,cortex-a7-gic"; | |
169 | interrupt-controller; | |
170 | #interrupt-cells = <3>; | |
171 | interrupt-parent = <&gic>; | |
172 | reg = <0 0x10211000 0 0x1000>, | |
173 | <0 0x10212000 0 0x1000>, | |
174 | <0 0x10214000 0 0x2000>, | |
175 | <0 0x10216000 0 0x2000>; | |
176 | }; | |
177 | ||
178 | uart0: serial@11002000 { | |
179 | compatible = "mediatek,mt2701-uart", | |
180 | "mediatek,mt6577-uart"; | |
181 | reg = <0 0x11002000 0 0x400>; | |
182 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; | |
28d6e364 EL |
183 | clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; |
184 | clock-names = "baud", "bus"; | |
74d25721 EL |
185 | status = "disabled"; |
186 | }; | |
187 | ||
188 | uart1: serial@11003000 { | |
189 | compatible = "mediatek,mt2701-uart", | |
190 | "mediatek,mt6577-uart"; | |
191 | reg = <0 0x11003000 0 0x400>; | |
192 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; | |
28d6e364 EL |
193 | clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; |
194 | clock-names = "baud", "bus"; | |
74d25721 EL |
195 | status = "disabled"; |
196 | }; | |
197 | ||
198 | uart2: serial@11004000 { | |
199 | compatible = "mediatek,mt2701-uart", | |
200 | "mediatek,mt6577-uart"; | |
201 | reg = <0 0x11004000 0 0x400>; | |
202 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; | |
28d6e364 EL |
203 | clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; |
204 | clock-names = "baud", "bus"; | |
74d25721 EL |
205 | status = "disabled"; |
206 | }; | |
207 | ||
208 | uart3: serial@11005000 { | |
209 | compatible = "mediatek,mt2701-uart", | |
210 | "mediatek,mt6577-uart"; | |
211 | reg = <0 0x11005000 0 0x400>; | |
212 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; | |
28d6e364 EL |
213 | clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; |
214 | clock-names = "baud", "bus"; | |
74d25721 EL |
215 | status = "disabled"; |
216 | }; | |
217 | }; |