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1cf30709 | 1 | // SPDX-License-Identifier: GPL-2.0 |
7d4938c1 MC |
2 | /* |
3 | * Copyright (c) 2015 MediaTek Inc. | |
4 | * Author: Mars.C <mars.cheng@mediatek.com> | |
5 | * | |
7d4938c1 MC |
6 | */ |
7 | ||
8 | #include <dt-bindings/interrupt-controller/irq.h> | |
9 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
7d4938c1 MC |
10 | |
11 | / { | |
12 | compatible = "mediatek,mt6580"; | |
13 | #address-cells = <1>; | |
14 | #size-cells = <1>; | |
15 | interrupt-parent = <&sysirq>; | |
16 | ||
17 | cpus { | |
18 | #address-cells = <1>; | |
19 | #size-cells = <0>; | |
20 | ||
21 | cpu@0 { | |
22 | device_type = "cpu"; | |
23 | compatible = "arm,cortex-a7"; | |
24 | reg = <0x0>; | |
25 | }; | |
26 | cpu@1 { | |
27 | device_type = "cpu"; | |
28 | compatible = "arm,cortex-a7"; | |
29 | reg = <0x1>; | |
30 | }; | |
31 | cpu@2 { | |
32 | device_type = "cpu"; | |
33 | compatible = "arm,cortex-a7"; | |
34 | reg = <0x2>; | |
35 | }; | |
36 | cpu@3 { | |
37 | device_type = "cpu"; | |
38 | compatible = "arm,cortex-a7"; | |
39 | reg = <0x3>; | |
40 | }; | |
41 | ||
42 | }; | |
43 | ||
44 | system_clk: dummy13m { | |
45 | compatible = "fixed-clock"; | |
46 | clock-frequency = <13000000>; | |
47 | #clock-cells = <0>; | |
48 | }; | |
49 | ||
50 | rtc_clk: dummy32k { | |
51 | compatible = "fixed-clock"; | |
52 | clock-frequency = <32000>; | |
53 | #clock-cells = <0>; | |
54 | }; | |
55 | ||
56 | uart_clk: dummy26m { | |
57 | compatible = "fixed-clock"; | |
58 | clock-frequency = <26000000>; | |
59 | #clock-cells = <0>; | |
60 | }; | |
61 | ||
62 | timer: timer@10008000 { | |
63 | compatible = "mediatek,mt6580-timer", | |
64 | "mediatek,mt6577-timer"; | |
65 | reg = <0x10008000 0x80>; | |
66 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; | |
67 | clocks = <&system_clk>, <&rtc_clk>; | |
68 | clock-names = "system-clk", "rtc-clk"; | |
69 | }; | |
70 | ||
71 | sysirq: interrupt-controller@10200100 { | |
72 | compatible = "mediatek,mt6580-sysirq", | |
73 | "mediatek,mt6577-sysirq"; | |
74 | interrupt-controller; | |
75 | #interrupt-cells = <3>; | |
76 | interrupt-parent = <&gic>; | |
77 | reg = <0x10200100 0x1c>; | |
78 | }; | |
79 | ||
80 | gic: interrupt-controller@10211000 { | |
81 | compatible = "arm,cortex-a7-gic"; | |
82 | interrupt-controller; | |
83 | #interrupt-cells = <3>; | |
84 | interrupt-parent = <&gic>; | |
85 | reg = <0x10211000 0x1000>, | |
387720c9 | 86 | <0x10212000 0x2000>, |
7d4938c1 MC |
87 | <0x10214000 0x2000>, |
88 | <0x10216000 0x2000>; | |
89 | }; | |
90 | ||
91 | uart0: serial@11005000 { | |
92 | compatible = "mediatek,mt6580-uart", | |
93 | "mediatek,mt6577-uart"; | |
94 | reg = <0x11005000 0x400>; | |
95 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>; | |
96 | clocks = <&uart_clk>; | |
97 | status = "disabled"; | |
98 | }; | |
99 | ||
100 | uart1: serial@11006000 { | |
101 | compatible = "mediatek,mt6580-uart", | |
102 | "mediatek,mt6577-uart"; | |
103 | reg = <0x11006000 0x400>; | |
104 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>; | |
105 | clocks = <&uart_clk>; | |
106 | status = "disabled"; | |
107 | }; | |
108 | }; |