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arm: dts: mediatek: converted to using SPDX identifiers
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / mt7623.dtsi
CommitLineData
1cf30709 1// SPDX-License-Identifier: GPL-2.0
31ac0d69 2/*
d4c794f3 3 * Copyright (c) 2017 MediaTek Inc.
571b9589 4 * Author: John Crispin <john@phrozen.org>
d4c794f3 5 * Sean Wang <sean.wang@mediatek.com>
31ac0d69 6 *
31ac0d69
JC		 7 */
8
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
fbf6ad10 11#include <dt-bindings/clock/mt2701-clk.h>
7ed9672f 12#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
608cc0c0 13#include <dt-bindings/power/mt2701-power.h>
7ed9672f
JC		 14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/phy/phy.h>
fbf6ad10 16#include <dt-bindings/reset/mt2701-resets.h>
f4ff257c 17#include <dt-bindings/thermal/thermal.h>
31ac0d69
JC		 18#include "skeleton64.dtsi"
19
20/ {
21 compatible = "mediatek,mt7623";
22 interrupt-parent = <&sysirq>;
23
58b36967 24 cpu_opp_table: opp-table {
f4ff257c
SW		 25 compatible = "operating-points-v2";
26 opp-shared;
27
28 opp-98000000 {
29 opp-hz = /bits/ 64 <98000000>;
30 opp-microvolt = <1050000>;
31 };
32
33 opp-198000000 {
34 opp-hz = /bits/ 64 <198000000>;
35 opp-microvolt = <1050000>;
36 };
37
38 opp-398000000 {
39 opp-hz = /bits/ 64 <398000000>;
40 opp-microvolt = <1050000>;
41 };
42
43 opp-598000000 {
44 opp-hz = /bits/ 64 <598000000>;
45 opp-microvolt = <1050000>;
46 };
47
48 opp-747500000 {
49 opp-hz = /bits/ 64 <747500000>;
50 opp-microvolt = <1050000>;
51 };
52
53 opp-1040000000 {
54 opp-hz = /bits/ 64 <1040000000>;
55 opp-microvolt = <1150000>;
56 };
57
58 opp-1196000000 {
59 opp-hz = /bits/ 64 <1196000000>;
60 opp-microvolt = <1200000>;
61 };
62
63 opp-1300000000 {
64 opp-hz = /bits/ 64 <1300000000>;
65 opp-microvolt = <1300000>;
66 };
67 };
68
31ac0d69
JC		 69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
27f99788 72 enable-method = "mediatek,mt6589-smp";
31ac0d69 73
c5749d34 74 cpu0: cpu@0 {
31ac0d69
JC		 75 device_type = "cpu";
76 compatible = "arm,cortex-a7";
77 reg = <0x0>;
f4ff257c
SW		 78 clocks = <&infracfg CLK_INFRA_CPUSEL>,
79 <&apmixedsys CLK_APMIXED_MAINPLL>;
80 clock-names = "cpu", "intermediate";
81 operating-points-v2 = <&cpu_opp_table>;
82 #cooling-cells = <2>;
63edf128 83 clock-frequency = <1300000000>;
31ac0d69 84 };
dfff569a 85
c5749d34 86 cpu1: cpu@1 {
31ac0d69
JC		 87 device_type = "cpu";
88 compatible = "arm,cortex-a7";
89 reg = <0x1>;
8e908df6
SW		 90 clocks = <&infracfg CLK_INFRA_CPUSEL>,
91 <&apmixedsys CLK_APMIXED_MAINPLL>;
92 clock-names = "cpu", "intermediate";
f4ff257c 93 operating-points-v2 = <&cpu_opp_table>;
63edf128 94 clock-frequency = <1300000000>;
31ac0d69 95 };
dfff569a 96
c5749d34 97 cpu2: cpu@2 {
31ac0d69
JC		 98 device_type = "cpu";
99 compatible = "arm,cortex-a7";
100 reg = <0x2>;
8e908df6
SW		 101 clocks = <&infracfg CLK_INFRA_CPUSEL>,
102 <&apmixedsys CLK_APMIXED_MAINPLL>;
103 clock-names = "cpu", "intermediate";
f4ff257c 104 operating-points-v2 = <&cpu_opp_table>;
63edf128 105 clock-frequency = <1300000000>;
31ac0d69 106 };
dfff569a 107
c5749d34 108 cpu3: cpu@3 {
31ac0d69
JC		 109 device_type = "cpu";
110 compatible = "arm,cortex-a7";
111 reg = <0x3>;
8e908df6
SW		 112 clocks = <&infracfg CLK_INFRA_CPUSEL>,
113 <&apmixedsys CLK_APMIXED_MAINPLL>;
114 clock-names = "cpu", "intermediate";
f4ff257c 115 operating-points-v2 = <&cpu_opp_table>;
63edf128 116 clock-frequency = <1300000000>;
31ac0d69
JC		 117 };
118 };
119
120 system_clk: dummy13m {
121 compatible = "fixed-clock";
122 clock-frequency = <13000000>;
123 #clock-cells = <0>;
124 };
125
fbf6ad10 126 rtc32k: oscillator@1 {
31ac0d69 127 compatible = "fixed-clock";
31ac0d69 128 #clock-cells = <0>;
fbf6ad10
JC		 129 clock-frequency = <32000>;
130 clock-output-names = "rtc32k";
31ac0d69
JC		 131 };
132
fbf6ad10 133 clk26m: oscillator@0 {
31ac0d69 134 compatible = "fixed-clock";
31ac0d69 135 #clock-cells = <0>;
fbf6ad10
JC		 136 clock-frequency = <26000000>;
137 clock-output-names = "clk26m";
31ac0d69
JC		 138 };
139
f4ff257c 140 thermal-zones {
58b36967 141 cpu_thermal: cpu-thermal {
f4ff257c
SW		 142 polling-delay-passive = <1000>;
143 polling-delay = <1000>;
144
145 thermal-sensors = <&thermal 0>;
146
147 trips {
58b36967 148 cpu_passive: cpu-passive {
f4ff257c
SW		 149 temperature = <47000>;
150 hysteresis = <2000>;
151 type = "passive";
152 };
153
58b36967 154 cpu_active: cpu-active {
f4ff257c
SW		 155 temperature = <67000>;
156 hysteresis = <2000>;
157 type = "active";
158 };
159
58b36967 160 cpu_hot: cpu-hot {
f4ff257c
SW		 161 temperature = <87000>;
162 hysteresis = <2000>;
163 type = "hot";
164 };
165
58b36967 166 cpu-crit {
f4ff257c
SW		 167 temperature = <107000>;
168 hysteresis = <2000>;
169 type = "critical";
170 };
171 };
172
173 cooling-maps {
174 map0 {
175 trip = <&cpu_passive>;
176 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
177 };
dfff569a 178
f4ff257c
SW		 179 map1 {
180 trip = <&cpu_active>;
181 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
182 };
dfff569a 183
f4ff257c
SW		 184 map2 {
185 trip = <&cpu_hot>;
186 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
187 };
188 };
189 };
190 };
191
31ac0d69
JC		 192 timer {
193 compatible = "arm,armv7-timer";
194 interrupt-parent = <&gic>;
195 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
196 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
197 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
198 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
7e6c7fe9
JC		 199 clock-frequency = <13000000>;
200 arm,cpu-registers-not-fw-configured;
31ac0d69
JC		 201 };
202
fbf6ad10
JC		 203 topckgen: syscon@10000000 {
204 compatible = "mediatek,mt7623-topckgen",
205 "mediatek,mt2701-topckgen",
206 "syscon";
207 reg = <0 0x10000000 0 0x1000>;
208 #clock-cells = <1>;
209 };
210
211 infracfg: syscon@10001000 {
212 compatible = "mediatek,mt7623-infracfg",
213 "mediatek,mt2701-infracfg",
214 "syscon";
215 reg = <0 0x10001000 0 0x1000>;
216 #clock-cells = <1>;
217 #reset-cells = <1>;
218 };
219
220 pericfg: syscon@10003000 {
221 compatible = "mediatek,mt7623-pericfg",
222 "mediatek,mt2701-pericfg",
223 "syscon";
224 reg = <0 0x10003000 0 0x1000>;
225 #clock-cells = <1>;
226 #reset-cells = <1>;
227 };
7ed9672f
JC		 228
229 pio: pinctrl@10005000 {
eb54a522 230 compatible = "mediatek,mt7623-pinctrl";
7ed9672f
JC		 231 reg = <0 0x1000b000 0 0x1000>;
232 mediatek,pctl-regmap = <&syscfg_pctl_a>;
233 pins-are-numbered;
234 gpio-controller;
235 #gpio-cells = <2>;
236 interrupt-controller;
237 interrupt-parent = <&gic>;
238 #interrupt-cells = <2>;
239 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
241 };
242
243 syscfg_pctl_a: syscfg@10005000 {
244 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
245 reg = <0 0x10005000 0 0x1000>;
246 };
fbf6ad10 247
608cc0c0
JC		 248 scpsys: scpsys@10006000 {
249 compatible = "mediatek,mt7623-scpsys",
250 "mediatek,mt2701-scpsys",
251 "syscon";
252 #power-domain-cells = <1>;
253 reg = <0 0x10006000 0 0x1000>;
254 infracfg = <&infracfg>;
255 clocks = <&topckgen CLK_TOP_MM_SEL>,
256 <&topckgen CLK_TOP_MFG_SEL>,
257 <&topckgen CLK_TOP_ETHIF_SEL>;
258 clock-names = "mm", "mfg", "ethif";
259 };
260
31ac0d69
JC		 261 watchdog: watchdog@10007000 {
262 compatible = "mediatek,mt7623-wdt",
263 "mediatek,mt6589-wdt";
264 reg = <0 0x10007000 0 0x100>;
265 };
266
267 timer: timer@10008000 {
268 compatible = "mediatek,mt7623-timer",
269 "mediatek,mt6577-timer";
270 reg = <0 0x10008000 0 0x80>;
271 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
fbf6ad10 272 clocks = <&system_clk>, <&rtc32k>;
31ac0d69
JC		 273 clock-names = "system-clk", "rtc-clk";
274 };
275
cd294fb0
JC		 276 pwrap: pwrap@1000d000 {
277 compatible = "mediatek,mt7623-pwrap",
278 "mediatek,mt2701-pwrap";
279 reg = <0 0x1000d000 0 0x1000>;
280 reg-names = "pwrap";
281 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
282 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
283 reset-names = "pwrap";
284 clocks = <&infracfg CLK_INFRA_PMICSPI>,
285 <&infracfg CLK_INFRA_PMICWRAP>;
286 clock-names = "spi", "wrap";
287 };
288
f4ff257c 289 cir: cir@10013000 {
91044f38
SW		 290 compatible = "mediatek,mt7623-cir";
291 reg = <0 0x10013000 0 0x1000>;
292 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
293 clocks = <&infracfg CLK_INFRA_IRRX>;
294 clock-names = "clk";
295 status = "disabled";
296 };
297
31ac0d69
JC		 298 sysirq: interrupt-controller@10200100 {
299 compatible = "mediatek,mt7623-sysirq",
300 "mediatek,mt6577-sysirq";
301 interrupt-controller;
302 #interrupt-cells = <3>;
303 interrupt-parent = <&gic>;
304 reg = <0 0x10200100 0 0x1c>;
305 };
306
43c7a91b
SW		 307 efuse: efuse@10206000 {
308 compatible = "mediatek,mt7623-efuse",
309 "mediatek,mt8173-efuse";
f4ff257c 310 reg = <0 0x10206000 0 0x1000>;
43c7a91b
SW		 311 #address-cells = <1>;
312 #size-cells = <1>;
313 thermal_calibration_data: calib@424 {
314 reg = <0x424 0xc>;
315 };
316 };
317
fbf6ad10
JC		 318 apmixedsys: syscon@10209000 {
319 compatible = "mediatek,mt7623-apmixedsys",
320 "mediatek,mt2701-apmixedsys",
321 "syscon";
322 reg = <0 0x10209000 0 0x1000>;
323 #clock-cells = <1>;
324 };
325
88b43a7b
SW		 326 rng: rng@1020f000 {
327 compatible = "mediatek,mt7623-rng";
328 reg = <0 0x1020f000 0 0x1000>;
329 clocks = <&infracfg CLK_INFRA_TRNG>;
330 clock-names = "rng";
331 };
332
31ac0d69
JC		 333 gic: interrupt-controller@10211000 {
334 compatible = "arm,cortex-a7-gic";
335 interrupt-controller;
336 #interrupt-cells = <3>;
337 interrupt-parent = <&gic>;
338 reg = <0 0x10211000 0 0x1000>,
387720c9 339 <0 0x10212000 0 0x2000>,
31ac0d69
JC		 340 <0 0x10214000 0 0x2000>,
341 <0 0x10216000 0 0x2000>;
342 };
343
38b244b5
SW		 344 auxadc: adc@11001000 {
345 compatible = "mediatek,mt7623-auxadc",
346 "mediatek,mt2701-auxadc";
347 reg = <0 0x11001000 0 0x1000>;
348 clocks = <&pericfg CLK_PERI_AUXADC>;
349 clock-names = "main";
350 #io-channel-cells = <1>;
351 };
352
31ac0d69
JC		 353 uart0: serial@11002000 {
354 compatible = "mediatek,mt7623-uart",
355 "mediatek,mt6577-uart";
356 reg = <0 0x11002000 0 0x400>;
357 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
fbf6ad10
JC		 358 clocks = <&pericfg CLK_PERI_UART0_SEL>,
359 <&pericfg CLK_PERI_UART0>;
360 clock-names = "baud", "bus";
31ac0d69
JC		 361 status = "disabled";
362 };
363
364 uart1: serial@11003000 {
365 compatible = "mediatek,mt7623-uart",
366 "mediatek,mt6577-uart";
367 reg = <0 0x11003000 0 0x400>;
368 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
fbf6ad10
JC		 369 clocks = <&pericfg CLK_PERI_UART1_SEL>,
370 <&pericfg CLK_PERI_UART1>;
371 clock-names = "baud", "bus";
31ac0d69
JC		 372 status = "disabled";
373 };
374
375 uart2: serial@11004000 {
376 compatible = "mediatek,mt7623-uart",
377 "mediatek,mt6577-uart";
378 reg = <0 0x11004000 0 0x400>;
379 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
fbf6ad10
JC		 380 clocks = <&pericfg CLK_PERI_UART2_SEL>,
381 <&pericfg CLK_PERI_UART2>;
382 clock-names = "baud", "bus";
31ac0d69
JC		 383 status = "disabled";
384 };
385
386 uart3: serial@11005000 {
387 compatible = "mediatek,mt7623-uart",
388 "mediatek,mt6577-uart";
389 reg = <0 0x11005000 0 0x400>;
390 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
fbf6ad10
JC		 391 clocks = <&pericfg CLK_PERI_UART3_SEL>,
392 <&pericfg CLK_PERI_UART3>;
393 clock-names = "baud", "bus";
31ac0d69
JC		 394 status = "disabled";
395 };
8bb656d9 396
ffdbc3cf
SW		 397 pwm: pwm@11006000 {
398 compatible = "mediatek,mt7623-pwm";
399 reg = <0 0x11006000 0 0x1000>;
400 #pwm-cells = <2>;
401 clocks = <&topckgen CLK_TOP_PWM_SEL>,
402 <&pericfg CLK_PERI_PWM>,
403 <&pericfg CLK_PERI_PWM1>,
404 <&pericfg CLK_PERI_PWM2>,
405 <&pericfg CLK_PERI_PWM3>,
406 <&pericfg CLK_PERI_PWM4>,
407 <&pericfg CLK_PERI_PWM5>;
408 clock-names = "top", "main", "pwm1", "pwm2",
409 "pwm3", "pwm4", "pwm5";
410 status = "disabled";
411 };
412
076f8710
JC		 413 i2c0: i2c@11007000 {
414 compatible = "mediatek,mt7623-i2c",
415 "mediatek,mt6577-i2c";
416 reg = <0 0x11007000 0 0x70>,
417 <0 0x11000200 0 0x80>;
418 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
419 clock-div = <16>;
420 clocks = <&pericfg CLK_PERI_I2C0>,
421 <&pericfg CLK_PERI_AP_DMA>;
422 clock-names = "main", "dma";
423 #address-cells = <1>;
424 #size-cells = <0>;
425 status = "disabled";
426 };
427
428 i2c1: i2c@11008000 {
429 compatible = "mediatek,mt7623-i2c",
430 "mediatek,mt6577-i2c";
431 reg = <0 0x11008000 0 0x70>,
432 <0 0x11000280 0 0x80>;
433 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
434 clock-div = <16>;
435 clocks = <&pericfg CLK_PERI_I2C1>,
436 <&pericfg CLK_PERI_AP_DMA>;
437 clock-names = "main", "dma";
438 #address-cells = <1>;
439 #size-cells = <0>;
440 status = "disabled";
441 };
442
443 i2c2: i2c@11009000 {
444 compatible = "mediatek,mt7623-i2c",
445 "mediatek,mt6577-i2c";
446 reg = <0 0x11009000 0 0x70>,
447 <0 0x11000300 0 0x80>;
448 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
449 clock-div = <16>;
450 clocks = <&pericfg CLK_PERI_I2C2>,
451 <&pericfg CLK_PERI_AP_DMA>;
452 clock-names = "main", "dma";
453 #address-cells = <1>;
454 #size-cells = <0>;
455 status = "disabled";
456 };
457
44893591
SW		 458 spi0: spi@1100a000 {
459 compatible = "mediatek,mt7623-spi",
460 "mediatek,mt2701-spi";
461 #address-cells = <1>;
462 #size-cells = <0>;
463 reg = <0 0x1100a000 0 0x100>;
464 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
465 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
466 <&topckgen CLK_TOP_SPI0_SEL>,
467 <&pericfg CLK_PERI_SPI0>;
468 clock-names = "parent-clk", "sel-clk", "spi-clk";
469 status = "disabled";
470 };
471
9794a090
SW		 472 thermal: thermal@1100b000 {
473 #thermal-sensor-cells = <1>;
474 compatible = "mediatek,mt7623-thermal",
475 "mediatek,mt2701-thermal";
476 reg = <0 0x1100b000 0 0x1000>;
477 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
478 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
479 clock-names = "therm", "auxadc";
480 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
481 reset-names = "therm";
482 mediatek,auxadc = <&auxadc>;
483 mediatek,apmixedsys = <&apmixedsys>;
484 nvmem-cells = <&thermal_calibration_data>;
485 nvmem-cell-names = "calibration-data";
486 };
487
dfff569a
RL		 488 nandc: nfi@1100d000 {
489 compatible = "mediatek,mt7623-nfc",
490 "mediatek,mt2701-nfc";
491 reg = <0 0x1100d000 0 0x1000>;
492 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
493 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
494 clocks = <&pericfg CLK_PERI_NFI>,
495 <&pericfg CLK_PERI_NFI_PAD>;
496 clock-names = "nfi_clk", "pad_clk";
497 status = "disabled";
498 ecc-engine = <&bch>;
499 #address-cells = <1>;
500 #size-cells = <0>;
501 };
502
503 bch: ecc@1100e000 {
504 compatible = "mediatek,mt7623-ecc",
505 "mediatek,mt2701-ecc";
506 reg = <0 0x1100e000 0 0x1000>;
507 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
508 clocks = <&pericfg CLK_PERI_NFI_ECC>;
509 clock-names = "nfiecc_clk";
510 status = "disabled";
511 };
512
44893591
SW		 513 spi1: spi@11016000 {
514 compatible = "mediatek,mt7623-spi",
515 "mediatek,mt2701-spi";
516 #address-cells = <1>;
517 #size-cells = <0>;
518 reg = <0 0x11016000 0 0x100>;
519 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
520 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
521 <&topckgen CLK_TOP_SPI1_SEL>,
522 <&pericfg CLK_PERI_SPI1>;
523 clock-names = "parent-clk", "sel-clk", "spi-clk";
524 status = "disabled";
525 };
526
527 spi2: spi@11017000 {
528 compatible = "mediatek,mt7623-spi",
529 "mediatek,mt2701-spi";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 reg = <0 0x11017000 0 0x1000>;
533 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
534 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
535 <&topckgen CLK_TOP_SPI2_SEL>,
536 <&pericfg CLK_PERI_SPI2>;
537 clock-names = "parent-clk", "sel-clk", "spi-clk";
538 status = "disabled";
539 };
540
8eef6dea
RL		 541 audsys: clock-controller@11220000 {
542 compatible = "mediatek,mt7623-audsys",
543 "mediatek,mt2701-audsys",
544 "syscon";
545 reg = <0 0x11220000 0 0x2000>;
546 #clock-cells = <1>;
96c390a7 547
8eef6dea
RL		 548 afe: audio-controller {
549 compatible = "mediatek,mt7623-audio",
550 "mediatek,mt2701-audio";
551 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
552 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
553 interrupt-names = "afe", "asys";
554 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
555
556 clocks = <&infracfg CLK_INFRA_AUDIO>,
557 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
558 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
559 <&topckgen CLK_TOP_AUD_48K_TIMING>,
560 <&topckgen CLK_TOP_AUD_44K_TIMING>,
561 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
562 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
563 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
564 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
565 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
566 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
567 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
568 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
569 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
570 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
571 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
572 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
573 <&audsys CLK_AUD_I2SO1>,
574 <&audsys CLK_AUD_I2SO2>,
575 <&audsys CLK_AUD_I2SO3>,
576 <&audsys CLK_AUD_I2SO4>,
577 <&audsys CLK_AUD_I2SIN1>,
578 <&audsys CLK_AUD_I2SIN2>,
579 <&audsys CLK_AUD_I2SIN3>,
580 <&audsys CLK_AUD_I2SIN4>,
581 <&audsys CLK_AUD_ASRCO1>,
582 <&audsys CLK_AUD_ASRCO2>,
583 <&audsys CLK_AUD_ASRCO3>,
584 <&audsys CLK_AUD_ASRCO4>,
585 <&audsys CLK_AUD_AFE>,
586 <&audsys CLK_AUD_AFE_CONN>,
587 <&audsys CLK_AUD_A1SYS>,
588 <&audsys CLK_AUD_A2SYS>,
589 <&audsys CLK_AUD_AFE_MRGIF>;
590
591 clock-names = "infra_sys_audio_clk",
592 "top_audio_mux1_sel",
593 "top_audio_mux2_sel",
594 "top_audio_a1sys_hp",
595 "top_audio_a2sys_hp",
596 "i2s0_src_sel",
597 "i2s1_src_sel",
598 "i2s2_src_sel",
599 "i2s3_src_sel",
600 "i2s0_src_div",
601 "i2s1_src_div",
602 "i2s2_src_div",
603 "i2s3_src_div",
604 "i2s0_mclk_en",
605 "i2s1_mclk_en",
606 "i2s2_mclk_en",
607 "i2s3_mclk_en",
608 "i2so0_hop_ck",
609 "i2so1_hop_ck",
610 "i2so2_hop_ck",
611 "i2so3_hop_ck",
612 "i2si0_hop_ck",
613 "i2si1_hop_ck",
614 "i2si2_hop_ck",
615 "i2si3_hop_ck",
616 "asrc0_out_ck",
617 "asrc1_out_ck",
618 "asrc2_out_ck",
619 "asrc3_out_ck",
620 "audio_afe_pd",
621 "audio_afe_conn_pd",
622 "audio_a1sys_pd",
623 "audio_a2sys_pd",
624 "audio_mrgif_pd";
625
626 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
627 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
628 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
629 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
630 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
631 <&topckgen CLK_TOP_AUD2PLL_90M>;
632 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
633 };
96c390a7
SW		 634 };
635
ffa491c8
JC		 636 mmc0: mmc@11230000 {
637 compatible = "mediatek,mt7623-mmc",
3e2af579 638 "mediatek,mt2701-mmc";
ffa491c8
JC		 639 reg = <0 0x11230000 0 0x1000>;
640 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
641 clocks = <&pericfg CLK_PERI_MSDC30_0>,
642 <&topckgen CLK_TOP_MSDC30_0_SEL>;
643 clock-names = "source", "hclk";
644 status = "disabled";
645 };
646
647 mmc1: mmc@11240000 {
648 compatible = "mediatek,mt7623-mmc",
3e2af579 649 "mediatek,mt2701-mmc";
ffa491c8 650 reg = <0 0x11240000 0 0x1000>;
6dec760f 651 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
ffa491c8
JC		 652 clocks = <&pericfg CLK_PERI_MSDC30_1>,
653 <&topckgen CLK_TOP_MSDC30_1_SEL>;
654 clock-names = "source", "hclk";
655 status = "disabled";
656 };
657
dfff569a
RL		 658 hifsys: syscon@1a000000 {
659 compatible = "mediatek,mt7623-hifsys",
660 "mediatek,mt2701-hifsys",
661 "syscon";
662 reg = <0 0x1a000000 0 0x1000>;
663 #clock-cells = <1>;
664 #reset-cells = <1>;
665 };
666
c10a98c4
RL		 667 pcie: pcie@1a140000 {
668 compatible = "mediatek,mt7623-pcie";
669 device_type = "pci";
670 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
671 <0 0x1a142000 0 0x1000>, /* Port0 registers */
672 <0 0x1a143000 0 0x1000>, /* Port1 registers */
673 <0 0x1a144000 0 0x1000>; /* Port2 registers */
674 reg-names = "subsys", "port0", "port1", "port2";
675 #address-cells = <3>;
676 #size-cells = <2>;
677 #interrupt-cells = <1>;
678 interrupt-map-mask = <0xf800 0 0 0>;
679 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
680 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
681 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
682 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
683 <&hifsys CLK_HIFSYS_PCIE0>,
684 <&hifsys CLK_HIFSYS_PCIE1>,
685 <&hifsys CLK_HIFSYS_PCIE2>;
686 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
687 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
688 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
689 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
690 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
691 phys = <&pcie0_port PHY_TYPE_PCIE>,
692 <&pcie1_port PHY_TYPE_PCIE>,
693 <&u3port1 PHY_TYPE_PCIE>;
694 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
695 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
696 bus-range = <0x00 0xff>;
697 status = "disabled";
698 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
699 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
700
701 pcie@0,0 {
702 reg = <0x0000 0 0 0 0>;
703 #address-cells = <3>;
704 #size-cells = <2>;
705 #interrupt-cells = <1>;
706 interrupt-map-mask = <0 0 0 0>;
707 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
708 ranges;
709 num-lanes = <1>;
710 status = "disabled";
711 };
712
713 pcie@1,0 {
714 reg = <0x0800 0 0 0 0>;
715 #address-cells = <3>;
716 #size-cells = <2>;
717 #interrupt-cells = <1>;
718 interrupt-map-mask = <0 0 0 0>;
719 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
720 ranges;
721 num-lanes = <1>;
722 status = "disabled";
723 };
724
725 pcie@2,0 {
726 reg = <0x1000 0 0 0 0>;
727 #address-cells = <3>;
728 #size-cells = <2>;
729 #interrupt-cells = <1>;
730 interrupt-map-mask = <0 0 0 0>;
731 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
732 ranges;
733 num-lanes = <1>;
734 status = "disabled";
735 };
736 };
737
738 pcie0_phy: pcie-phy@1a149000 {
739 compatible = "mediatek,generic-tphy-v1";
740 reg = <0 0x1a149000 0 0x0700>;
741 #address-cells = <2>;
742 #size-cells = <2>;
743 ranges;
744 status = "disabled";
745
746 pcie0_port: pcie-phy@1a149900 {
747 reg = <0 0x1a149900 0 0x0700>;
748 clocks = <&clk26m>;
749 clock-names = "ref";
750 #phy-cells = <1>;
751 status = "okay";
752 };
753 };
754
755 pcie1_phy: pcie-phy@1a14a000 {
756 compatible = "mediatek,generic-tphy-v1";
757 reg = <0 0x1a14a000 0 0x0700>;
758 #address-cells = <2>;
759 #size-cells = <2>;
760 ranges;
761 status = "disabled";
762
763 pcie1_port: pcie-phy@1a14a900 {
764 reg = <0 0x1a14a900 0 0x0700>;
765 clocks = <&clk26m>;
766 clock-names = "ref";
767 #phy-cells = <1>;
768 status = "okay";
769 };
770 };
771
35fdd6c9
JC		 772 usb1: usb@1a1c0000 {
773 compatible = "mediatek,mt7623-xhci",
774 "mediatek,mt8173-xhci";
775 reg = <0 0x1a1c0000 0 0x1000>,
776 <0 0x1a1c4700 0 0x0100>;
777 reg-names = "mac", "ippc";
778 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
779 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
780 <&topckgen CLK_TOP_ETHIF_SEL>;
e4316d6f 781 clock-names = "sys_ck", "ref_ck";
35fdd6c9
JC		 782 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
783 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
784 status = "disabled";
785 };
786
787 u3phy1: usb-phy@1a1c4000 {
f4ff257c
SW		 788 compatible = "mediatek,mt7623-u3phy",
789 "mediatek,mt2701-u3phy";
35fdd6c9 790 reg = <0 0x1a1c4000 0 0x0700>;
35fdd6c9
JC		 791 #address-cells = <2>;
792 #size-cells = <2>;
793 ranges;
794 status = "disabled";
795
796 u2port0: usb-phy@1a1c4800 {
797 reg = <0 0x1a1c4800 0 0x0100>;
e4316d6f
RL		 798 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
799 clock-names = "ref";
35fdd6c9
JC		 800 #phy-cells = <1>;
801 status = "okay";
802 };
803
804 u3port0: usb-phy@1a1c4900 {
805 reg = <0 0x1a1c4900 0 0x0700>;
e4316d6f
RL		 806 clocks = <&clk26m>;
807 clock-names = "ref";
35fdd6c9
JC		 808 #phy-cells = <1>;
809 status = "okay";
810 };
811 };
812
813 usb2: usb@1a240000 {
814 compatible = "mediatek,mt7623-xhci",
815 "mediatek,mt8173-xhci";
816 reg = <0 0x1a240000 0 0x1000>,
817 <0 0x1a244700 0 0x0100>;
818 reg-names = "mac", "ippc";
819 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
820 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
821 <&topckgen CLK_TOP_ETHIF_SEL>;
e4316d6f 822 clock-names = "sys_ck", "ref_ck";
35fdd6c9
JC		 823 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
824 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
825 status = "disabled";
826 };
827
828 u3phy2: usb-phy@1a244000 {
f4ff257c
SW		 829 compatible = "mediatek,mt7623-u3phy",
830 "mediatek,mt2701-u3phy";
35fdd6c9 831 reg = <0 0x1a244000 0 0x0700>;
35fdd6c9
JC		 832 #address-cells = <2>;
833 #size-cells = <2>;
834 ranges;
835 status = "disabled";
836
837 u2port1: usb-phy@1a244800 {
838 reg = <0 0x1a244800 0 0x0100>;
e4316d6f
RL		 839 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
840 clock-names = "ref";
35fdd6c9
JC		 841 #phy-cells = <1>;
842 status = "okay";
843 };
844
845 u3port1: usb-phy@1a244900 {
846 reg = <0 0x1a244900 0 0x0700>;
e4316d6f
RL		 847 clocks = <&clk26m>;
848 clock-names = "ref";
35fdd6c9
JC		 849 #phy-cells = <1>;
850 status = "okay";
851 };
852 };
853
8bb656d9
JC		 854 ethsys: syscon@1b000000 {
855 compatible = "mediatek,mt7623-ethsys",
856 "mediatek,mt2701-ethsys",
857 "syscon";
858 reg = <0 0x1b000000 0 0x1000>;
859 #clock-cells = <1>;
76a09ce2 860 #reset-cells = <1>;
8bb656d9 861 };
687976ae
SW		 862
863 eth: ethernet@1b100000 {
f4ff257c
SW		 864 compatible = "mediatek,mt7623-eth",
865 "mediatek,mt2701-eth",
866 "syscon";
687976ae
SW		 867 reg = <0 0x1b100000 0 0x20000>;
868 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
869 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
870 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
871 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
872 <&ethsys CLK_ETHSYS_ESW>,
873 <&ethsys CLK_ETHSYS_GP1>,
874 <&ethsys CLK_ETHSYS_GP2>,
875 <&apmixedsys CLK_APMIXED_TRGPLL>;
876 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
d60129db
SW		 877 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
878 <&ethsys MT2701_ETHSYS_GMAC_RST>,
879 <&ethsys MT2701_ETHSYS_PPE_RST>;
880 reset-names = "fe", "gmac", "ppe";
687976ae
SW		 881 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
882 mediatek,ethsys = <&ethsys>;
883 mediatek,pctl = <&syscfg_pctl_a>;
884 #address-cells = <1>;
885 #size-cells = <0>;
886 status = "disabled";
887 };
465792e6
SW		 888
889 crypto: crypto@1b240000 {
a336ba44 890 compatible = "mediatek,eip97-crypto";
465792e6
SW		 891 reg = <0 0x1b240000 0 0x20000>;
892 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
893 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
894 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
895 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
896 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
a336ba44
RL		 897 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
898 clock-names = "cryp";
465792e6 899 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
31ac0d69
JC		 900 status = "disabled";
901 };
902};
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