[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / mt7623.dtsi

/*
 * Copyright (c) 2016 MediaTek Inc.
 * Author: John Crispin <john@phrozen.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton64.dtsi"

/ {
	compatible = "mediatek,mt7623";
	interrupt-parent = <&sysirq>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt6589-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	rtc_clk: dummy32k {
		compatible = "fixed-clock";
		clock-frequency = <32000>;
		#clock-cells = <0>;
	};

	uart_clk: dummy26m {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <13000000>;
		arm,cpu-registers-not-fw-configured;
	};

	watchdog: watchdog@10007000 {
		compatible = "mediatek,mt7623-wdt",
			     "mediatek,mt6589-wdt";
		reg = <0 0x10007000 0 0x100>;
	};

	timer: timer@10008000 {
		compatible = "mediatek,mt7623-timer",
			     "mediatek,mt6577-timer";
		reg = <0 0x10008000 0 0x80>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>, <&rtc_clk>;
		clock-names = "system-clk", "rtc-clk";
	};

	sysirq: interrupt-controller@10200100 {
		compatible = "mediatek,mt7623-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10200100 0 0x1c>;
	};

	gic: interrupt-controller@10211000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10211000 0 0x1000>,
		      <0 0x10212000 0 0x2000>,
		      <0 0x10214000 0 0x2000>,
		      <0 0x10216000 0 0x2000>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt7623-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt7623-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt7623-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt7623-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};
};
Commit	Line	Data
31ac0d69 JC	1	/*
31ac0d69 JC	2	* Copyright (c) 2016 MediaTek Inc.
571b9589	3	* Author: John Crispin <john@phrozen.org>
31ac0d69 JC	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <dt-bindings/interrupt-controller/irq.h>
	16	#include <dt-bindings/interrupt-controller/arm-gic.h>
	17	#include "skeleton64.dtsi"
	18
	19	/ {
	20	compatible = "mediatek,mt7623";
	21	interrupt-parent = <&sysirq>;
	22
	23	cpus {
	24	#address-cells = <1>;
	25	#size-cells = <0>;
27f99788	26	enable-method = "mediatek,mt6589-smp";
31ac0d69 JC	27
	28	cpu@0 {
	29	device_type = "cpu";
	30	compatible = "arm,cortex-a7";
	31	reg = <0x0>;
	32	};
	33	cpu@1 {
	34	device_type = "cpu";
	35	compatible = "arm,cortex-a7";
	36	reg = <0x1>;
	37	};
	38	cpu@2 {
	39	device_type = "cpu";
	40	compatible = "arm,cortex-a7";
	41	reg = <0x2>;
	42	};
	43	cpu@3 {
	44	device_type = "cpu";
	45	compatible = "arm,cortex-a7";
	46	reg = <0x3>;
	47	};
	48	};
	49
	50	system_clk: dummy13m {
	51	compatible = "fixed-clock";
	52	clock-frequency = <13000000>;
	53	#clock-cells = <0>;
	54	};
	55
	56	rtc_clk: dummy32k {
	57	compatible = "fixed-clock";
	58	clock-frequency = <32000>;
	59	#clock-cells = <0>;
	60	};
	61
	62	uart_clk: dummy26m {
	63	compatible = "fixed-clock";
	64	clock-frequency = <26000000>;
	65	#clock-cells = <0>;
	66	};
	67
	68	timer {
	69	compatible = "arm,armv7-timer";
	70	interrupt-parent = <&gic>;
	71	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	72	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	73	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	74	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
7e6c7fe9 JC	75	clock-frequency = <13000000>;
7e6c7fe9 JC	76	arm,cpu-registers-not-fw-configured;
31ac0d69 JC	77	};
	78
	79	watchdog: watchdog@10007000 {
	80	compatible = "mediatek,mt7623-wdt",
	81	"mediatek,mt6589-wdt";
	82	reg = <0 0x10007000 0 0x100>;
	83	};
	84
	85	timer: timer@10008000 {
	86	compatible = "mediatek,mt7623-timer",
	87	"mediatek,mt6577-timer";
	88	reg = <0 0x10008000 0 0x80>;
	89	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
	90	clocks = <&system_clk>, <&rtc_clk>;
	91	clock-names = "system-clk", "rtc-clk";
	92	};
	93
	94	sysirq: interrupt-controller@10200100 {
	95	compatible = "mediatek,mt7623-sysirq",
	96	"mediatek,mt6577-sysirq";
	97	interrupt-controller;
	98	#interrupt-cells = <3>;
	99	interrupt-parent = <&gic>;
	100	reg = <0 0x10200100 0 0x1c>;
	101	};
	102
	103	gic: interrupt-controller@10211000 {
	104	compatible = "arm,cortex-a7-gic";
	105	interrupt-controller;
	106	#interrupt-cells = <3>;
	107	interrupt-parent = <&gic>;
	108	reg = <0 0x10211000 0 0x1000>,
387720c9	109	<0 0x10212000 0 0x2000>,
31ac0d69 JC	110	<0 0x10214000 0 0x2000>,
	111	<0 0x10216000 0 0x2000>;
	112	};
	113
	114	uart0: serial@11002000 {
	115	compatible = "mediatek,mt7623-uart",
	116	"mediatek,mt6577-uart";
	117	reg = <0 0x11002000 0 0x400>;
	118	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
	119	clocks = <&uart_clk>;
	120	status = "disabled";
	121	};
	122
	123	uart1: serial@11003000 {
	124	compatible = "mediatek,mt7623-uart",
	125	"mediatek,mt6577-uart";
	126	reg = <0 0x11003000 0 0x400>;
	127	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
	128	clocks = <&uart_clk>;
	129	status = "disabled";
	130	};
	131
	132	uart2: serial@11004000 {
	133	compatible = "mediatek,mt7623-uart",
	134	"mediatek,mt6577-uart";
	135	reg = <0 0x11004000 0 0x400>;
	136	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
	137	clocks = <&uart_clk>;
	138	status = "disabled";
	139	};
	140
	141	uart3: serial@11005000 {
	142	compatible = "mediatek,mt7623-uart",
	143	"mediatek,mt6577-uart";
	144	reg = <0 0x11005000 0 0x400>;
	145	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
	146	clocks = <&uart_clk>;
	147	status = "disabled";
	148	};
	149	};