[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / mt8135.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Joe.C <yingjoe.chen@mediatek.com>
 *
 */

#include <dt-bindings/clock/mt8135-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/mt8135-resets.h>
#include "mt8135-pinfunc.h"

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "mediatek,mt8135";
	interrupt-parent = <&sysirq>;

	cpu-map {
		cluster0 {
			core0 {
				cpu = <&cpu0>;
			};
			core1 {
				cpu = <&cpu1>;
			};
		};

		cluster1 {
			core0 {
				cpu = <&cpu2>;
			};
			core1 {
				cpu = <&cpu3>;
			};
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt81xx-tz-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x001>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x100>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x101>;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		trustzone-bootinfo@80002000 {
			compatible = "mediatek,trustzone-bootinfo";
			reg = <0 0x80002000 0 0x1000>;
		};
	};

	clocks {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		system_clk: dummy13m {
			compatible = "fixed-clock";
			clock-frequency = <13000000>;
			#clock-cells = <0>;
		};

		rtc_clk: dummy32k {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			#clock-cells = <0>;
		};

		clk26m: clk26m {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <13000000>;
		arm,cpu-registers-not-fw-configured;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		topckgen: topckgen@10000000 {
			compatible = "mediatek,mt8135-topckgen";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg: infracfg@10001000 {
			#reset-cells = <1>;
			#clock-cells = <1>;
			compatible = "mediatek,mt8135-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
		};

		pericfg: pericfg@10003000 {
			#reset-cells = <1>;
			#clock-cells = <1>;
			compatible = "mediatek,mt8135-pericfg", "syscon";
			reg = <0 0x10003000 0 0x1000>;
		};

		/*
		 * Pinctrl access register at 0x10005000 and 0x1020c000 through
		 * regmap. Register 0x1000b000 is used by EINT.
		 */
		pio: pinctrl@10005000 {
			compatible = "mediatek,mt8135-pinctrl";
			reg = <0 0x1000b000 0 0x1000>;
			mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
			pins-are-numbered;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
		};

		syscfg_pctl_a: syscfg_pctl_a@10005000 {
			compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
			reg = <0 0x10005000 0 0x1000>;
		};

		timer: timer@10008000 {
			compatible = "mediatek,mt8135-timer",
					"mediatek,mt6577-timer";
			reg = <0 0x10008000 0 0x80>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&system_clk>, <&rtc_clk>;
			clock-names = "system-clk", "rtc-clk";
		};

		pwrap: pwrap@1000f000 {
			compatible = "mediatek,mt8135-pwrap";
			reg = <0 0x1000f000 0 0x1000>,
				<0 0x11017000 0 0x1000>;
			reg-names = "pwrap", "pwrap-bridge";
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
					<&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
			reset-names = "pwrap", "pwrap-bridge";
			clocks = <&clk26m>, <&clk26m>;
			clock-names = "spi", "wrap";
		};

		sysirq: interrupt-controller@10200030 {
			compatible = "mediatek,mt8135-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10200030 0 0x1c>;
		};

		apmixedsys: apmixedsys@10209000 {
			compatible = "mediatek,mt8135-apmixedsys";
			reg = <0 0x10209000 0 0x1000>;
			#clock-cells = <1>;
		};

		syscfg_pctl_b: syscfg_pctl_b@1020c000 {
			compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
			reg = <0 0x1020c000 0 0x1000>;
		};

		gic: interrupt-controller@10211000 {
			compatible = "arm,cortex-a15-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10211000 0 0x1000>,
			      <0 0x10212000 0 0x2000>,
			      <0 0x10214000 0 0x2000>,
			      <0 0x10216000 0 0x2000>;
		};

		uart0: serial@11006000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11006000 0 0x400>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart1: serial@11007000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11007000 0 0x400>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart2: serial@11008000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11008000 0 0x400>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart3: serial@11009000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11009000 0 0x400>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

	};
};
Commit	Line	Data
1cf30709	1	// SPDX-License-Identifier: GPL-2.0
0c3fb203 J	2	/*
	3	* Copyright (c) 2014 MediaTek Inc.
	4	* Author: Joe.C <yingjoe.chen@mediatek.com>
	5	*
0c3fb203 J	6	*/
0c3fb203 J	7
3cc17a5c	8	#include <dt-bindings/clock/mt8135-clk.h>
0c3fb203 J	9	#include <dt-bindings/interrupt-controller/irq.h>
0c3fb203 J	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
967313e2	11	#include <dt-bindings/reset/mt8135-resets.h>
cfb11671	12	#include "mt8135-pinfunc.h"
0c3fb203 J	13
0c3fb203 J	14	/ {
abe60a3a RH	15	#address-cells = <2>;
abe60a3a RH	16	#size-cells = <2>;
0c3fb203	17	compatible = "mediatek,mt8135";
e0bed077	18	interrupt-parent = <&sysirq>;
0c3fb203 J	19
	20	cpu-map {
	21	cluster0 {
	22	core0 {
	23	cpu = <&cpu0>;
	24	};
	25	core1 {
	26	cpu = <&cpu1>;
	27	};
	28	};
	29
	30	cluster1 {
	31	core0 {
	32	cpu = <&cpu2>;
	33	};
	34	core1 {
	35	cpu = <&cpu3>;
	36	};
	37	};
	38	};
	39
	40	cpus {
	41	#address-cells = <1>;
	42	#size-cells = <0>;
d186a394	43	enable-method = "mediatek,mt81xx-tz-smp";
0c3fb203 J	44
	45	cpu0: cpu@0 {
	46	device_type = "cpu";
	47	compatible = "arm,cortex-a7";
	48	reg = <0x000>;
	49	};
	50
	51	cpu1: cpu@1 {
	52	device_type = "cpu";
	53	compatible = "arm,cortex-a7";
	54	reg = <0x001>;
	55	};
	56
	57	cpu2: cpu@100 {
	58	device_type = "cpu";
	59	compatible = "arm,cortex-a15";
	60	reg = <0x100>;
	61	};
	62
	63	cpu3: cpu@101 {
	64	device_type = "cpu";
	65	compatible = "arm,cortex-a15";
	66	reg = <0x101>;
	67	};
	68	};
	69
d186a394 YC	70	reserved-memory {
	71	#address-cells = <2>;
	72	#size-cells = <2>;
	73	ranges;
	74
	75	trustzone-bootinfo@80002000 {
	76	compatible = "mediatek,trustzone-bootinfo";
	77	reg = <0 0x80002000 0 0x1000>;
	78	};
	79	};
	80
0c3fb203 J	81	clocks {
	82	#address-cells = <2>;
	83	#size-cells = <2>;
	84	compatible = "simple-bus";
	85	ranges;
	86
	87	system_clk: dummy13m {
	88	compatible = "fixed-clock";
	89	clock-frequency = <13000000>;
	90	#clock-cells = <0>;
	91	};
	92
	93	rtc_clk: dummy32k {
	94	compatible = "fixed-clock";
	95	clock-frequency = <32000>;
	96	#clock-cells = <0>;
	97	};
07149473	98
3cc17a5c JL	99	clk26m: clk26m {
	100	compatible = "fixed-clock";
	101	#clock-cells = <0>;
	102	clock-frequency = <26000000>;
	103	};
0c3fb203 J	104	};
0c3fb203 J	105
d186a394 YC	106	timer {
	107	compatible = "arm,armv7-timer";
	108	interrupt-parent = <&gic>;
	109	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \|
	110	IRQ_TYPE_LEVEL_LOW)>,
	111	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \|
	112	IRQ_TYPE_LEVEL_LOW)>,
	113	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \|
	114	IRQ_TYPE_LEVEL_LOW)>,
	115	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \|
	116	IRQ_TYPE_LEVEL_LOW)>;
	117	clock-frequency = <13000000>;
	118	arm,cpu-registers-not-fw-configured;
	119	};
	120
0c3fb203 J	121	soc {
	122	#address-cells = <2>;
	123	#size-cells = <2>;
	124	compatible = "simple-bus";
	125	ranges;
	126
3cc17a5c JL	127	topckgen: topckgen@10000000 {
	128	compatible = "mediatek,mt8135-topckgen";
	129	reg = <0 0x10000000 0 0x1000>;
	130	#clock-cells = <1>;
	131	};
	132
	133	infracfg: infracfg@10001000 {
	134	#reset-cells = <1>;
	135	#clock-cells = <1>;
	136	compatible = "mediatek,mt8135-infracfg", "syscon";
	137	reg = <0 0x10001000 0 0x1000>;
	138	};
	139
	140	pericfg: pericfg@10003000 {
	141	#reset-cells = <1>;
	142	#clock-cells = <1>;
	143	compatible = "mediatek,mt8135-pericfg", "syscon";
	144	reg = <0 0x10003000 0 0x1000>;
	145	};
	146
cfb11671 HY	147	/*
	148	* Pinctrl access register at 0x10005000 and 0x1020c000 through
	149	* regmap. Register 0x1000b000 is used by EINT.
	150	*/
	151	pio: pinctrl@10005000 {
	152	compatible = "mediatek,mt8135-pinctrl";
	153	reg = <0 0x1000b000 0 0x1000>;
	154	mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
	155	pins-are-numbered;
	156	gpio-controller;
	157	#gpio-cells = <2>;
	158	interrupt-controller;
	159	#interrupt-cells = <2>;
	160	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	161	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	162	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	163	};
	164
	165	syscfg_pctl_a: syscfg_pctl_a@10005000 {
	166	compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
	167	reg = <0 0x10005000 0 0x1000>;
	168	};
	169
0c3fb203 J	170	timer: timer@10008000 {
	171	compatible = "mediatek,mt8135-timer",
	172	"mediatek,mt6577-timer";
	173	reg = <0 0x10008000 0 0x80>;
e0bed077	174	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
0c3fb203 J	175	clocks = <&system_clk>, <&rtc_clk>;
	176	clock-names = "system-clk", "rtc-clk";
	177	};
	178
8dd29d28 SH	179	pwrap: pwrap@1000f000 {
	180	compatible = "mediatek,mt8135-pwrap";
	181	reg = <0 0x1000f000 0 0x1000>,
	182	<0 0x11017000 0 0x1000>;
	183	reg-names = "pwrap", "pwrap-bridge";
	184	interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
	185	resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
	186	<&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
	187	reset-names = "pwrap", "pwrap-bridge";
	188	clocks = <&clk26m>, <&clk26m>;
	189	clock-names = "spi", "wrap";
	190	};
	191
e0bed077 YC	192	sysirq: interrupt-controller@10200030 {
	193	compatible = "mediatek,mt8135-sysirq",
	194	"mediatek,mt6577-sysirq";
	195	interrupt-controller;
	196	#interrupt-cells = <3>;
	197	interrupt-parent = <&gic>;
	198	reg = <0 0x10200030 0 0x1c>;
	199	};
	200
3cc17a5c JL	201	apmixedsys: apmixedsys@10209000 {
	202	compatible = "mediatek,mt8135-apmixedsys";
	203	reg = <0 0x10209000 0 0x1000>;
	204	#clock-cells = <1>;
	205	};
	206
cfb11671 HY	207	syscfg_pctl_b: syscfg_pctl_b@1020c000 {
	208	compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
	209	reg = <0 0x1020c000 0 0x1000>;
	210	};
	211
0c3fb203 J	212	gic: interrupt-controller@10211000 {
	213	compatible = "arm,cortex-a15-gic";
	214	interrupt-controller;
	215	#interrupt-cells = <3>;
e0bed077	216	interrupt-parent = <&gic>;
0c3fb203	217	reg = <0 0x10211000 0 0x1000>,
387720c9	218	<0 0x10212000 0 0x2000>,
0c3fb203 J	219	<0 0x10214000 0 0x2000>,
	220	<0 0x10216000 0 0x2000>;
	221	};
07149473 EH	222
	223	uart0: serial@11006000 {
	224	compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
	225	reg = <0 0x11006000 0 0x400>;
	226	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
d57b1d28 SH	227	clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
d57b1d28 SH	228	clock-names = "baud", "bus";
07149473 EH	229	status = "disabled";
	230	};
	231
	232	uart1: serial@11007000 {
	233	compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
	234	reg = <0 0x11007000 0 0x400>;
	235	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
d57b1d28 SH	236	clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
d57b1d28 SH	237	clock-names = "baud", "bus";
07149473 EH	238	status = "disabled";
	239	};
	240
	241	uart2: serial@11008000 {
	242	compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
	243	reg = <0 0x11008000 0 0x400>;
	244	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
d57b1d28 SH	245	clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
d57b1d28 SH	246	clock-names = "baud", "bus";
07149473 EH	247	status = "disabled";
	248	};
	249
	250	uart3: serial@11009000 {
	251	compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
	252	reg = <0 0x11009000 0 0x400>;
	253	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
d57b1d28 SH	254	clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
d57b1d28 SH	255	clock-names = "baud", "bus";
07149473 EH	256	status = "disabled";
	257	};
	258
0c3fb203 J	259	};
0c3fb203 J	260	};