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Commit | Line | Data |
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3f187f82 PU |
1 | /* |
2 | * Device Tree Source for OMAP2420 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | /include/ "omap2.dtsi" | |
12 | ||
13 | / { | |
14 | compatible = "ti,omap2420", "ti,omap2"; | |
15 | ||
16 | ocp { | |
510c0ffd JH |
17 | counter32k: counter@48004000 { |
18 | compatible = "ti,omap-counter32k"; | |
19 | reg = <0x48004000 0x20>; | |
20 | ti,hwmods = "counter_32k"; | |
21 | }; | |
22 | ||
679e3310 TL |
23 | omap2420_pmx: pinmux@48000030 { |
24 | compatible = "ti,omap2420-padconf", "pinctrl-single"; | |
25 | reg = <0x48000030 0x0113>; | |
26 | #address-cells = <1>; | |
27 | #size-cells = <0>; | |
28 | pinctrl-single,register-width = <8>; | |
29 | pinctrl-single,function-mask = <0x3f>; | |
30 | }; | |
31 | ||
423182e3 JH |
32 | gpio1: gpio@48018000 { |
33 | compatible = "ti,omap2-gpio"; | |
34 | reg = <0x48018000 0x200>; | |
35 | interrupts = <29>; | |
36 | ti,hwmods = "gpio1"; | |
37 | #gpio-cells = <2>; | |
38 | gpio-controller; | |
39 | #interrupt-cells = <2>; | |
40 | interrupt-controller; | |
41 | }; | |
42 | ||
43 | gpio2: gpio@4801a000 { | |
44 | compatible = "ti,omap2-gpio"; | |
45 | reg = <0x4801a000 0x200>; | |
46 | interrupts = <30>; | |
47 | ti,hwmods = "gpio2"; | |
48 | #gpio-cells = <2>; | |
49 | gpio-controller; | |
50 | #interrupt-cells = <2>; | |
51 | interrupt-controller; | |
52 | }; | |
53 | ||
54 | gpio3: gpio@4801c000 { | |
55 | compatible = "ti,omap2-gpio"; | |
56 | reg = <0x4801c000 0x200>; | |
57 | interrupts = <31>; | |
58 | ti,hwmods = "gpio3"; | |
59 | #gpio-cells = <2>; | |
60 | gpio-controller; | |
61 | #interrupt-cells = <2>; | |
62 | interrupt-controller; | |
63 | }; | |
64 | ||
65 | gpio4: gpio@4801e000 { | |
66 | compatible = "ti,omap2-gpio"; | |
67 | reg = <0x4801e000 0x200>; | |
68 | interrupts = <32>; | |
69 | ti,hwmods = "gpio4"; | |
70 | #gpio-cells = <2>; | |
71 | gpio-controller; | |
72 | #interrupt-cells = <2>; | |
73 | interrupt-controller; | |
74 | }; | |
75 | ||
1c7dbb55 JH |
76 | gpmc: gpmc@6800a000 { |
77 | compatible = "ti,omap2420-gpmc"; | |
78 | reg = <0x6800a000 0x1000>; | |
79 | #address-cells = <2>; | |
80 | #size-cells = <1>; | |
81 | interrupts = <20>; | |
82 | gpmc,num-cs = <8>; | |
83 | gpmc,num-waitpins = <4>; | |
84 | ti,hwmods = "gpmc"; | |
85 | }; | |
86 | ||
3f187f82 PU |
87 | mcbsp1: mcbsp@48074000 { |
88 | compatible = "ti,omap2420-mcbsp"; | |
89 | reg = <0x48074000 0xff>; | |
90 | reg-names = "mpu"; | |
91 | interrupts = <59>, /* TX interrupt */ | |
92 | <60>; /* RX interrupt */ | |
93 | interrupt-names = "tx", "rx"; | |
3f187f82 PU |
94 | ti,hwmods = "mcbsp1"; |
95 | }; | |
96 | ||
97 | mcbsp2: mcbsp@48076000 { | |
98 | compatible = "ti,omap2420-mcbsp"; | |
99 | reg = <0x48076000 0xff>; | |
100 | reg-names = "mpu"; | |
101 | interrupts = <62>, /* TX interrupt */ | |
102 | <63>; /* RX interrupt */ | |
103 | interrupt-names = "tx", "rx"; | |
3f187f82 PU |
104 | ti,hwmods = "mcbsp2"; |
105 | }; | |
fab8ad0b JH |
106 | |
107 | timer1: timer@48028000 { | |
108 | compatible = "ti,omap2-timer"; | |
109 | reg = <0x48028000 0x400>; | |
110 | interrupts = <37>; | |
111 | ti,hwmods = "timer1"; | |
112 | ti,timer-alwon; | |
113 | }; | |
3f187f82 PU |
114 | }; |
115 | }; |