[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / omap3-igep.dtsi

/*
 * Common device tree for IGEP boards based on AM/DM37x
 *
 * Copyright (C) 2012 Javier Martinez Canillas <javier@osg.samsung.com>
 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "omap36xx.dtsi"

/ {
	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>; /* 512 MB */
	};

	chosen {
		stdout-path = &uart3;
	};

	sound {
		compatible = "ti,omap-twl4030";
		ti,model = "igep2";
		ti,mcbsp = <&mcbsp2>;
	};

	vdd33: regulator-vdd33 {
		compatible = "regulator-fixed";
		regulator-name = "vdd33";
		regulator-always-on;
	};

};

&omap3_pmx_core {
	uart1_pins: pinmux_uart1_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0)	/* uart1_rx.uart1_rx */
			OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0)	/* uart1_tx.uart1_tx */
		>;
	};

	uart3_pins: pinmux_uart3_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)	/* uart3_rx.uart3_rx */
			OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)	/* uart3_tx.uart3_tx */
		>;
	};

	mcbsp2_pins: pinmux_mcbsp2_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)	/* mcbsp2_fsx.mcbsp2_fsx */
			OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)	/* mcbsp2_clkx.mcbsp2_clkx */
			OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)	/* mcbsp2_dr.mcbsp2.dr */
			OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)	/* mcbsp2_dx.mcbsp2_dx */
		>;
	};

	mmc1_pins: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_clk.sdmmc1_clk */
			OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_cmd.sdmmc1_cmd */
			OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat1.sdmmc1_dat1 */
			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat2.sdmmc1_dat2 */
			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat3.sdmmc1_dat3 */
		>;
	};

	mmc2_pins: pinmux_mmc2_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_clk.sdmmc2_clk */
			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_cmd.sdmmc2_cmd */
			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat1.sdmmc2_dat1 */
			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat2.sdmmc2_dat2 */
			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat3.sdmmc2_dat3 */
		>;
	};

	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)	/* i2c1_scl.i2c1_scl */
			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)	/* i2c1_sda.i2c1_sda */
		>;
	};

	i2c3_pins: pinmux_i2c3_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl.i2c3_scl */
			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda.i2c3_sda */
		>;
	};
};

&gpmc {
	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		linux,mtd-name= "micron,mt29c4g96maz";
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		ti,nand-ecc-opt = "bch8";

		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <44>;
		gpmc,cs-wr-off-ns = <44>;
		gpmc,adv-on-ns = <6>;
		gpmc,adv-rd-off-ns = <34>;
		gpmc,adv-wr-off-ns = <44>;
		gpmc,we-off-ns = <40>;
		gpmc,oe-off-ns = <54>;
		gpmc,access-ns = <64>;
		gpmc,rd-cycle-ns = <82>;
		gpmc,wr-cycle-ns = <82>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;

		#address-cells = <1>;
		#size-cells = <1>;
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	clock-frequency = <2600000>;

	twl: twl@48 {
		reg = <0x48>;
		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
		interrupt-parent = <&intc>;

		twl_audio: audio {
			compatible = "ti,twl4030-audio";
			codec {
			};
		};
	};
};

#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;
};

&mcbsp2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcbsp2_pins>;
	status = "okay";
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	vmmc-supply = <&vmmc1>;
	vmmc_aux-supply = <&vsim>;
	bus-width = <4>;
	cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
};

&mmc3 {
	status = "disabled";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_pins>;
};

&twl_gpio {
	ti,use-leds;
};

&usb_otg_hs {
	interface-type = <0>;
	usb-phy = <&usb2_phy>;
	phys = <&usb2_phy>;
	phy-names = "usb2-phy";
	mode = <3>;
	power = <50>;
};
Commit	Line	Data
947fd0a2	1	/*
9aa36dfd	2	* Common device tree for IGEP boards based on AM/DM37x
947fd0a2	3	*
56a31e54	4	* Copyright (C) 2012 Javier Martinez Canillas <javier@osg.samsung.com>
947fd0a2 JMC	5	* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	/dts-v1/;
	12
9aa36dfd	13	#include "omap36xx.dtsi"
947fd0a2 JMC	14
947fd0a2 JMC	15	/ {
81777ff9	16	memory@80000000 {
947fd0a2 JMC	17	device_type = "memory";
	18	reg = <0x80000000 0x20000000>; /* 512 MB */
	19	};
	20
8d289cc6 EBS	21	chosen {
	22	stdout-path = &uart3;
	23	};
	24
947fd0a2 JMC	25	sound {
	26	compatible = "ti,omap-twl4030";
	27	ti,model = "igep2";
	28	ti,mcbsp = <&mcbsp2>;
947fd0a2	29	};
0e9fd777 EBS	30
	31	vdd33: regulator-vdd33 {
	32	compatible = "regulator-fixed";
	33	regulator-name = "vdd33";
	34	regulator-always-on;
	35	};
	36
947fd0a2 JMC	37	};
	38
	39	&omap3_pmx_core {
bc0b8b70 MB	40	uart1_pins: pinmux_uart1_pins {
bc0b8b70 MB	41	pinctrl-single,pins = <
be146412 LP	42	OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT \| MUX_MODE0) /* uart1_rx.uart1_rx */
be146412 LP	43	OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT \| MUX_MODE0) /* uart1_tx.uart1_tx */
bc0b8b70 MB	44	>;
	45	};
	46
947fd0a2 JMC	47	uart3_pins: pinmux_uart3_pins {
947fd0a2 JMC	48	pinctrl-single,pins = <
be146412 LP	49	OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT \| MUX_MODE0) /* uart3_rx.uart3_rx */
be146412 LP	50	OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT \| MUX_MODE0) /* uart3_tx.uart3_tx */
947fd0a2 JMC	51	>;
	52	};
	53
65399f03 EBS	54	mcbsp2_pins: pinmux_mcbsp2_pins {
65399f03 EBS	55	pinctrl-single,pins = <
be146412 LP	56	OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT \| MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
	57	OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT \| MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
	58	OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT \| MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
	59	OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT \| MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
65399f03 EBS	60	>;
	61	};
	62
947fd0a2 JMC	63	mmc1_pins: pinmux_mmc1_pins {
947fd0a2 JMC	64	pinctrl-single,pins = <
be146412 LP	65	OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
	66	OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
	67	OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
	68	OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
	69	OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
	70	OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
947fd0a2 JMC	71	>;
947fd0a2 JMC	72	};
d72b4415	73
0e9fd777 EBS	74	mmc2_pins: pinmux_mmc2_pins {
0e9fd777 EBS	75	pinctrl-single,pins = <
be146412 LP	76	OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
	77	OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
	78	OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
	79	OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
	80	OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
	81	OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP \| MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
0e9fd777 EBS	82	>;
	83	};
	84
d526daeb JMC	85	i2c1_pins: pinmux_i2c1_pins {
d526daeb JMC	86	pinctrl-single,pins = <
be146412 LP	87	OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT \| MUX_MODE0) /* i2c1_scl.i2c1_scl */
be146412 LP	88	OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT \| MUX_MODE0) /* i2c1_sda.i2c1_sda */
d526daeb JMC	89	>;
	90	};
	91
d526daeb JMC	92	i2c3_pins: pinmux_i2c3_pins {
d526daeb JMC	93	pinctrl-single,pins = <
be146412 LP	94	OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT \| MUX_MODE0) /* i2c3_scl.i2c3_scl */
be146412 LP	95	OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT \| MUX_MODE0) /* i2c3_sda.i2c3_sda */
d526daeb JMC	96	>;
d526daeb JMC	97	};
947fd0a2 JMC	98	};
947fd0a2 JMC	99
e170db3c EBS	100	&gpmc {
e170db3c EBS	101	nand@0,0 {
44e47164 RQ	102	compatible = "ti,omap2-nand";
	103	reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
	104	interrupt-parent = <&gpmc>;
	105	interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
	106	<1 IRQ_TYPE_NONE>; /* termcount */
e170db3c	107	linux,mtd-name= "micron,mt29c4g96maz";
e170db3c EBS	108	nand-bus-width = <16>;
	109	gpmc,device-width = <2>;
	110	ti,nand-ecc-opt = "bch8";
	111
	112	gpmc,sync-clk-ps = <0>;
	113	gpmc,cs-on-ns = <0>;
	114	gpmc,cs-rd-off-ns = <44>;
	115	gpmc,cs-wr-off-ns = <44>;
	116	gpmc,adv-on-ns = <6>;
	117	gpmc,adv-rd-off-ns = <34>;
	118	gpmc,adv-wr-off-ns = <44>;
	119	gpmc,we-off-ns = <40>;
	120	gpmc,oe-off-ns = <54>;
	121	gpmc,access-ns = <64>;
	122	gpmc,rd-cycle-ns = <82>;
	123	gpmc,wr-cycle-ns = <82>;
	124	gpmc,wr-access-ns = <40>;
	125	gpmc,wr-data-mux-bus-ns = <0>;
	126
	127	#address-cells = <1>;
	128	#size-cells = <1>;
e170db3c EBS	129	};
	130	};
	131
947fd0a2	132	&i2c1 {
d526daeb JMC	133	pinctrl-names = "default";
d526daeb JMC	134	pinctrl-0 = <&i2c1_pins>;
947fd0a2 JMC	135	clock-frequency = <2600000>;
	136
	137	twl: twl@48 {
	138	reg = <0x48>;
	139	interrupts = <7>; /* SYS_NIRQ cascaded to intc */
	140	interrupt-parent = <&intc>;
	141
	142	twl_audio: audio {
	143	compatible = "ti,twl4030-audio";
	144	codec {
272c789b	145	};
947fd0a2 JMC	146	};
	147	};
	148	};
	149
98ef7957	150	#include "twl4030.dtsi"
f9688457	151	#include "twl4030_omap3.dtsi"
947fd0a2	152
d526daeb JMC	153	&i2c3 {
	154	pinctrl-names = "default";
	155	pinctrl-0 = <&i2c3_pins>;
	156	};
	157
65399f03 EBS	158	&mcbsp2 {
	159	pinctrl-names = "default";
	160	pinctrl-0 = <&mcbsp2_pins>;
726322ce	161	status = "okay";
65399f03 EBS	162	};
65399f03 EBS	163
947fd0a2	164	&mmc1 {
272c789b LP	165	pinctrl-names = "default";
	166	pinctrl-0 = <&mmc1_pins>;
	167	vmmc-supply = <&vmmc1>;
	168	vmmc_aux-supply = <&vsim>;
	169	bus-width = <4>;
b44f788c	170	cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
947fd0a2 JMC	171	};
947fd0a2 JMC	172
947fd0a2 JMC	173	&mmc3 {
	174	status = "disabled";
	175	};
	176
bc0b8b70	177	&uart1 {
272c789b LP	178	pinctrl-names = "default";
272c789b LP	179	pinctrl-0 = <&uart1_pins>;
bc0b8b70 MB	180	};
bc0b8b70 MB	181
947fd0a2	182	&uart3 {
272c789b LP	183	pinctrl-names = "default";
272c789b LP	184	pinctrl-0 = <&uart3_pins>;
947fd0a2 JMC	185	};
	186
	187	&twl_gpio {
	188	ti,use-leds;
	189	};
aa496bde JMC	190
	191	&usb_otg_hs {
	192	interface-type = <0>;
	193	usb-phy = <&usb2_phy>;
	194	phys = <&usb2_phy>;
	195	phy-names = "usb2-phy";
	196	mode = <3>;
	197	power = <50>;
	198	};