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Merge remote-tracking branch 'asoc/fix/cs4271' into asoc-linus
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / omap3-n900.dts
CommitLineData
a4d4b153
PM		 1/*
2 * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
c3580bc1 3 * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
a4d4b153
PM		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 (or later) as
7 * published by the Free Software Foundation.
8 */
9
10/dts-v1/;
11
69540a7c 12#include "omap34xx.dtsi"
3fdb7717 13#include <dt-bindings/input/input.h>
a4d4b153 14
69540a7c
PR		 15/*
16 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
17 * for omap AES HW crypto support. When linux kernel try to access memory of AES
18 * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
19 * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
20 * crash anymore) omap AES support will be disabled for all Nokia N900 devices.
21 * There is "unofficial" version of bootloader which enables AES in L3 firewall
22 * but it is not widely used and to prevent kernel crash rather AES is disabled.
23 * There is also no runtime detection code if AES is disabled in L3 firewall...
24 */
25&aes {
26 status = "disabled";
27};
28
a4d4b153
PM		 29/ {
30 model = "Nokia N900";
c3580bc1 31 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
a4d4b153 32
1861cda0
ID		 33 aliases {
34 i2c0;
35 i2c1 = &i2c1;
36 i2c2 = &i2c2;
37 i2c3 = &i2c3;
38 };
39
a4d4b153
PM		 40 cpus {
41 cpu@0 {
42 cpu0-supply = <&vcc>;
43 };
44 };
45
c1be2032
TL		 46 leds {
47 compatible = "gpio-leds";
48 heartbeat {
49 label = "debug::sleep";
f585a15c 50 gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */
c1be2032
TL		 51 linux,default-trigger = "default-on";
52 pinctrl-names = "default";
53 pinctrl-0 = <&debug_leds>;
54 };
55 };
56
81777ff9 57 memory@80000000 {
a4d4b153
PM		 58 device_type = "memory";
59 reg = <0x80000000 0x10000000>; /* 256 MB */
60 };
61
3931c839
SR		 62 gpio_keys {
63 compatible = "gpio-keys";
64
65 camera_lens_cover {
66 label = "Camera Lens Cover";
67 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */
97d7f2ff
PR		 68 linux,input-type = <EV_SW>;
69 linux,code = <SW_CAMERA_LENS_COVER>;
05cf1e03 70 linux,can-disable;
3931c839
SR		 71 };
72
73 camera_focus {
74 label = "Camera Focus";
75 gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */
97d7f2ff 76 linux,code = <KEY_CAMERA_FOCUS>;
05cf1e03 77 linux,can-disable;
3931c839
SR		 78 };
79
80 camera_capture {
81 label = "Camera Capture";
82 gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */
97d7f2ff 83 linux,code = <KEY_CAMERA>;
05cf1e03 84 linux,can-disable;
3931c839
SR		 85 };
86
87 lock_button {
88 label = "Lock Button";
89 gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */
97d7f2ff 90 linux,code = <KEY_SCREENLOCK>;
05cf1e03 91 linux,can-disable;
3931c839
SR		 92 };
93
94 keypad_slide {
95 label = "Keypad Slide";
96 gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */
97d7f2ff
PR		 97 linux,input-type = <EV_SW>;
98 linux,code = <SW_KEYPAD_SLIDE>;
05cf1e03 99 linux,can-disable;
3931c839
SR		 100 };
101
102 proximity_sensor {
103 label = "Proximity Sensor";
104 gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */
97d7f2ff
PR		 105 linux,input-type = <EV_SW>;
106 linux,code = <SW_FRONT_PROXIMITY>;
05cf1e03 107 linux,can-disable;
3931c839
SR		 108 };
109 };
110
b950762c
PR		 111 isp1707: isp1707 {
112 compatible = "nxp,isp1707";
e17337a2
SR		 113 nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
114 usb-phy = <&usb2_phy>;
115 };
1133420f
TV		 116
117 tv: connector {
32797b3e 118 compatible = "composite-video-connector";
1133420f
TV		 119 label = "tv";
120
121 port {
122 tv_connector_in: endpoint {
123 remote-endpoint = <&venc_out>;
124 };
125 };
126 };
f7d0f2a0
SR		 127
128 sound: n900-audio {
129 compatible = "nokia,n900-audio";
130
131 nokia,cpu-dai = <&mcbsp2>;
132 nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>;
133 nokia,headphone-amplifier = <&tpa6130a2>;
134
135 tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */
136 jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */
137 eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
138 speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
139 };
28398c69
SR		 140
141 battery: n900-battery {
142 compatible = "nokia,n900-battery";
143 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
144 io-channel-names = "temp", "bsi", "vbat";
145 };
e7c86821 146
cc9a4bda 147 pwm9: dmtimer-pwm {
e7c86821
ID		 148 compatible = "ti,omap-dmtimer-pwm";
149 #pwm-cells = <3>;
150 ti,timers = <&timer9>;
151 ti,clock-source = <0x00>; /* timer_sys_ck */
152 };
153
154 ir: n900-ir {
155 compatible = "nokia,n900-ir";
156 pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
157 };
a4d4b153
PM		 158};
159
ac888a88
SR		 160&omap3_pmx_core {
161 pinctrl-names = "default";
162
7a89eecf
SR		 163 uart2_pins: pinmux_uart2_pins {
164 pinctrl-single,pins = <
675e457c
JMC		 165 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
166 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
7a89eecf
SR		 167 >;
168 };
169
170 uart3_pins: pinmux_uart3_pins {
171 pinctrl-single,pins = <
675e457c
JMC		 172 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */
173 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */
7a89eecf
SR		 174 >;
175 };
176
271d4c6b
TL		 177 ethernet_pins: pinmux_ethernet_pins {
178 pinctrl-single,pins = <
179 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
180 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
181 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
182 >;
183 };
184
9a894953
TL		 185 gpmc_pins: pinmux_gpmc_pins {
186 pinctrl-single,pins = <
187
188 /* address lines */
189 OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
190 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
191 OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
192
193 /* data lines, gpmc_d0..d7 not muxable according to TRM */
194 OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
195 OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
196 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
197 OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
198 OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
199 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
200 OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
201 OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
202
203 /*
204 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
205 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
206 */
207 OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
208 OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
209 >;
210 };
211
ac888a88
SR		 212 i2c1_pins: pinmux_i2c1_pins {
213 pinctrl-single,pins = <
675e457c
JMC		 214 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
215 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
ac888a88
SR		 216 >;
217 };
218
219 i2c2_pins: pinmux_i2c2_pins {
220 pinctrl-single,pins = <
675e457c
JMC		 221 OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
222 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
ac888a88
SR		 223 >;
224 };
225
226 i2c3_pins: pinmux_i2c3_pins {
227 pinctrl-single,pins = <
675e457c
JMC		 228 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
229 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
ac888a88
SR		 230 >;
231 };
f1751cff 232
c1be2032
TL		 233 debug_leds: pinmux_debug_led_pins {
234 pinctrl-single,pins = <
235 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */
236 >;
237 };
238
c1ad2206
SR		 239 mcspi4_pins: pinmux_mcspi4_pins {
240 pinctrl-single,pins = <
675e457c
JMC		 241 OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
242 OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
243 OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
244 OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
c1ad2206
SR		 245 >;
246 };
247
f1751cff
SR		 248 mmc1_pins: pinmux_mmc1_pins {
249 pinctrl-single,pins = <
675e457c
JMC		 250 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
251 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */
252 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */
253 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */
254 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */
255 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */
f1751cff
SR		 256 >;
257 };
d1e6f516 258
edd5eb4e
TL		 259 mmc2_pins: pinmux_mmc2_pins {
260 pinctrl-single,pins = <
675e457c
JMC		 261 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
262 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
263 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
264 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
265 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
266 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
267 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
268 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
269 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
270 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
edd5eb4e
TL		 271 >;
272 };
273
1133420f 274 acx565akm_pins: pinmux_acx565akm_pins {
d1e6f516 275 pinctrl-single,pins = <
675e457c 276 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
d1e6f516
SR		 277 >;
278 };
1133420f
TV		 279
280 dss_sdi_pins: pinmux_dss_sdi_pins {
281 pinctrl-single,pins = <
675e457c
JMC		 282 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */
283 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */
284 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */
285 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */
1133420f 286
675e457c
JMC		 287 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */
288 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */
1133420f
TV		 289 >;
290 };
c1ad2206
SR		 291
292 wl1251_pins: pinmux_wl1251 {
293 pinctrl-single,pins = <
675e457c
JMC		 294 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */
295 OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */
c1ad2206
SR		 296 >;
297 };
782e25a4
SR		 298
299 ssi_pins: pinmux_ssi {
300 pinctrl-single,pins = <
675e457c
JMC		 301 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
302 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
e0e80d43 303 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
675e457c
JMC		 304 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
305 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
306 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
307 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
308 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
782e25a4
SR		 309 >;
310 };
76ad4ac1
SR		 311
312 modem_pins: pinmux_modem {
313 pinctrl-single,pins = <
675e457c 314 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
e0e80d43 315 OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */
675e457c
JMC		 316 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
317 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
318 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
319 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
76ad4ac1
SR		 320 >;
321 };
ac888a88
SR		 322};
323
a4d4b153 324&i2c1 {
ac888a88
SR		 325 pinctrl-names = "default";
326 pinctrl-0 = <&i2c1_pins>;
327
a4d4b153
PM		 328 clock-frequency = <2200000>;
329
330 twl: twl@48 {
331 reg = <0x48>;
332 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
333 interrupt-parent = <&intc>;
334 };
335};
336
337#include "twl4030.dtsi"
ac888a88 338#include "twl4030_omap3.dtsi"
a4d4b153 339
9cdbbadd
SR		 340&vaux1 {
341 regulator-name = "V28";
342 regulator-min-microvolt = <2800000>;
343 regulator-max-microvolt = <2800000>;
0698178c 344 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
14fd7330 345 regulator-always-on; /* due to battery cover sensor */
9cdbbadd
SR		 346};
347
348&vaux2 {
349 regulator-name = "VCSI";
350 regulator-min-microvolt = <1800000>;
351 regulator-max-microvolt = <1800000>;
0698178c 352 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 353};
354
355&vaux3 {
356 regulator-name = "VMMC2_30";
357 regulator-min-microvolt = <2800000>;
358 regulator-max-microvolt = <3000000>;
0698178c 359 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 360};
361
362&vaux4 {
363 regulator-name = "VCAM_ANA_28";
364 regulator-min-microvolt = <2800000>;
365 regulator-max-microvolt = <2800000>;
0698178c 366 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 367};
368
369&vmmc1 {
370 regulator-name = "VMMC1";
371 regulator-min-microvolt = <1850000>;
372 regulator-max-microvolt = <3150000>;
0698178c 373 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 374};
375
376&vmmc2 {
377 regulator-name = "V28_A";
378 regulator-min-microvolt = <2800000>;
379 regulator-max-microvolt = <3000000>;
0698178c 380 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 381 regulator-always-on; /* due VIO leak to AIC34 VDDs */
382};
383
384&vpll1 {
385 regulator-name = "VPLL";
386 regulator-min-microvolt = <1800000>;
387 regulator-max-microvolt = <1800000>;
0698178c 388 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 389 regulator-always-on;
390};
391
392&vpll2 {
393 regulator-name = "VSDI_CSI";
394 regulator-min-microvolt = <1800000>;
395 regulator-max-microvolt = <1800000>;
0698178c 396 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 397 regulator-always-on;
398};
399
400&vsim {
401 regulator-name = "VMMC2_IO_18";
402 regulator-min-microvolt = <1800000>;
403 regulator-max-microvolt = <1800000>;
0698178c 404 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 405};
406
407&vio {
408 regulator-name = "VIO";
409 regulator-min-microvolt = <1800000>;
410 regulator-max-microvolt = <1800000>;
9cdbbadd
SR		 411};
412
413&vintana1 {
414 regulator-name = "VINTANA1";
415 /* fixed to 1500000 */
416 regulator-always-on;
417};
418
419&vintana2 {
420 regulator-name = "VINTANA2";
421 regulator-min-microvolt = <2750000>;
422 regulator-max-microvolt = <2750000>;
423 regulator-always-on;
424};
425
426&vintdig {
427 regulator-name = "VINTDIG";
428 /* fixed to 1500000 */
429 regulator-always-on;
430};
431
06ba7a61
SR		 432&twl {
433 twl_audio: audio {
434 compatible = "ti,twl4030-audio";
435 ti,enable-vibra = <1>;
436 };
9188883f
TL		 437
438 twl_power: power {
daebabd5 439 compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
9188883f
TL		 440 ti,use_poweroff;
441 };
06ba7a61
SR		 442};
443
85c215f3 444&twl_keypad {
3fdb7717
SR		 445 linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q)
446 MATRIX_KEY(0x00, 0x01, KEY_O)
447 MATRIX_KEY(0x00, 0x02, KEY_P)
448 MATRIX_KEY(0x00, 0x03, KEY_COMMA)
449 MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE)
450 MATRIX_KEY(0x00, 0x06, KEY_A)
451 MATRIX_KEY(0x00, 0x07, KEY_S)
452
453 MATRIX_KEY(0x01, 0x00, KEY_W)
454 MATRIX_KEY(0x01, 0x01, KEY_D)
455 MATRIX_KEY(0x01, 0x02, KEY_F)
456 MATRIX_KEY(0x01, 0x03, KEY_G)
457 MATRIX_KEY(0x01, 0x04, KEY_H)
458 MATRIX_KEY(0x01, 0x05, KEY_J)
459 MATRIX_KEY(0x01, 0x06, KEY_K)
460 MATRIX_KEY(0x01, 0x07, KEY_L)
461
462 MATRIX_KEY(0x02, 0x00, KEY_E)
463 MATRIX_KEY(0x02, 0x01, KEY_DOT)
464 MATRIX_KEY(0x02, 0x02, KEY_UP)
465 MATRIX_KEY(0x02, 0x03, KEY_ENTER)
466 MATRIX_KEY(0x02, 0x05, KEY_Z)
467 MATRIX_KEY(0x02, 0x06, KEY_X)
468 MATRIX_KEY(0x02, 0x07, KEY_C)
469 MATRIX_KEY(0x02, 0x08, KEY_F9)
470
471 MATRIX_KEY(0x03, 0x00, KEY_R)
472 MATRIX_KEY(0x03, 0x01, KEY_V)
473 MATRIX_KEY(0x03, 0x02, KEY_B)
474 MATRIX_KEY(0x03, 0x03, KEY_N)
475 MATRIX_KEY(0x03, 0x04, KEY_M)
476 MATRIX_KEY(0x03, 0x05, KEY_SPACE)
477 MATRIX_KEY(0x03, 0x06, KEY_SPACE)
478 MATRIX_KEY(0x03, 0x07, KEY_LEFT)
479
480 MATRIX_KEY(0x04, 0x00, KEY_T)
481 MATRIX_KEY(0x04, 0x01, KEY_DOWN)
482 MATRIX_KEY(0x04, 0x02, KEY_RIGHT)
483 MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL)
484 MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT)
485 MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT)
486 MATRIX_KEY(0x04, 0x08, KEY_F10)
487
488 MATRIX_KEY(0x05, 0x00, KEY_Y)
489 MATRIX_KEY(0x05, 0x08, KEY_F11)
490
491 MATRIX_KEY(0x06, 0x00, KEY_U)
492
493 MATRIX_KEY(0x07, 0x00, KEY_I)
494 MATRIX_KEY(0x07, 0x01, KEY_F7)
495 MATRIX_KEY(0x07, 0x02, KEY_F8)
85c215f3
SR		 496 >;
497};
498
a4d4b153
PM		 499&twl_gpio {
500 ti,pullups = <0x0>;
501 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
502};
503
504&i2c2 {
ac888a88
SR		 505 pinctrl-names = "default";
506 pinctrl-0 = <&i2c2_pins>;
507
48fc9864 508 clock-frequency = <100000>;
b2b9b258 509
14e3e295
SR		 510 tlv320aic3x: tlv320aic3x@18 {
511 compatible = "ti,tlv320aic3x";
512 reg = <0x18>;
513 gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
514 ai3x-gpio-func = <
515 0 /* AIC3X_GPIO1_FUNC_DISABLED */
516 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
517 >;
518
519 AVDD-supply = <&vmmc2>;
520 DRVDD-supply = <&vmmc2>;
521 IOVDD-supply = <&vio>;
522 DVDD-supply = <&vio>;
1819e303
PM		 523
524 ai3x-micbias-vg = <1>;
14e3e295
SR		 525 };
526
527 tlv320aic3x_aux: tlv320aic3x@19 {
528 compatible = "ti,tlv320aic3x";
529 reg = <0x19>;
530 gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
531
532 AVDD-supply = <&vmmc2>;
533 DRVDD-supply = <&vmmc2>;
534 IOVDD-supply = <&vio>;
535 DVDD-supply = <&vio>;
1819e303
PM		 536
537 ai3x-micbias-vg = <2>;
14e3e295
SR		 538 };
539
12f2f873
SR		 540 tsl2563: tsl2563@29 {
541 compatible = "amstaos,tsl2563";
542 reg = <0x29>;
543
544 amstaos,cover-comp-gain = <16>;
545 };
546
14628e44
PR		 547 adp1653: led-controller@30 {
548 compatible = "adi,adp1653";
549 reg = <0x30>;
550 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */
551
552 flash {
553 flash-timeout-us = <500000>;
554 flash-max-microamp = <320000>;
555 led-max-microamp = <50000>;
556 };
557 indicator {
558 led-max-microamp = <17500>;
559 };
560 };
561
a0bf1f3e
SR		 562 lp5523: lp5523@32 {
563 compatible = "national,lp5523";
564 reg = <0x32>;
565 clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
566 enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */
567
568 chan0 {
569 chan-name = "lp5523:kb1";
570 led-cur = /bits/ 8 <50>;
571 max-cur = /bits/ 8 <100>;
572 };
573
574 chan1 {
575 chan-name = "lp5523:kb2";
576 led-cur = /bits/ 8 <50>;
577 max-cur = /bits/ 8 <100>;
578 };
579
580 chan2 {
581 chan-name = "lp5523:kb3";
582 led-cur = /bits/ 8 <50>;
583 max-cur = /bits/ 8 <100>;
584 };
585
586 chan3 {
587 chan-name = "lp5523:kb4";
588 led-cur = /bits/ 8 <50>;
589 max-cur = /bits/ 8 <100>;
590 };
591
592 chan4 {
593 chan-name = "lp5523:b";
594 led-cur = /bits/ 8 <50>;
595 max-cur = /bits/ 8 <100>;
596 };
597
598 chan5 {
599 chan-name = "lp5523:g";
600 led-cur = /bits/ 8 <50>;
601 max-cur = /bits/ 8 <100>;
602 };
603
604 chan6 {
605 chan-name = "lp5523:r";
606 led-cur = /bits/ 8 <50>;
607 max-cur = /bits/ 8 <100>;
608 };
609
610 chan7 {
611 chan-name = "lp5523:kb5";
612 led-cur = /bits/ 8 <50>;
613 max-cur = /bits/ 8 <100>;
614 };
615
616 chan8 {
617 chan-name = "lp5523:kb6";
618 led-cur = /bits/ 8 <50>;
619 max-cur = /bits/ 8 <100>;
620 };
621 };
622
b2b9b258
SR		 623 bq27200: bq27200@55 {
624 compatible = "ti,bq27200";
625 reg = <0x55>;
626 };
9e2367c8 627
f585a15c 628 /* Stereo headphone amplifier */
9e2367c8
SR		 629 tpa6130a2: tpa6130a2@60 {
630 compatible = "ti,tpa6130a2";
631 reg = <0x60>;
632
633 Vdd-supply = <&vmmc2>;
634
635 power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
636 };
334a09c8 637
406c07e7
SR		 638 si4713: si4713@63 {
639 compatible = "silabs,si4713";
640 reg = <0x63>;
641
642 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
643 reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
644 vio-supply = <&vio>;
645 vdd-supply = <&vaux1>;
646 };
647
334a09c8
SR		 648 bq24150a: bq24150a@6b {
649 compatible = "ti,bq24150a";
650 reg = <0x6b>;
651
652 ti,current-limit = <100>;
653 ti,weak-battery-voltage = <3400>;
654 ti,battery-regulation-voltage = <4200>;
655 ti,charge-current = <650>;
656 ti,termination-current = <100>;
657 ti,resistor-sense = <68>;
658
b950762c 659 ti,usb-charger-detection = <&isp1707>;
334a09c8 660 };
a4d4b153
PM		 661};
662
663&i2c3 {
ac888a88
SR		 664 pinctrl-names = "default";
665 pinctrl-0 = <&i2c3_pins>;
666
48fc9864 667 clock-frequency = <400000>;
1ac4e6fe
SR		 668
669 lis302dl: lis3lv02d@1d {
670 compatible = "st,lis3lv02d";
671 reg = <0x1d>;
672
673 Vdd-supply = <&vaux1>;
674 Vdd_IO-supply = <&vio>;
675
676 interrupt-parent = <&gpio6>;
677 interrupts = <21 20>; /* 181 and 180 */
678
679 /* click flags */
680 st,click-single-x;
681 st,click-single-y;
682 st,click-single-z;
683
684 /* Limits are 0.5g * value */
685 st,click-threshold-x = <8>;
686 st,click-threshold-y = <8>;
687 st,click-threshold-z = <10>;
688
689 /* Click must be longer than time limit */
690 st,click-time-limit = <9>;
691
692 /* Kind of debounce filter */
693 st,click-latency = <50>;
694
695 /* Interrupt line 2 for click detection */
696 st,irq2-click;
697
698 st,wakeup-x-hi;
699 st,wakeup-y-hi;
700 st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
701
702 st,wakeup2-z-hi;
703 st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */
704
705 st,hipass1-disable;
706 st,hipass2-disable;
707
708 st,axis-x = <1>; /* LIS3_DEV_X */
709 st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
710 st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
711
712 st,min-limit-x = <(-32)>;
713 st,min-limit-y = <3>;
714 st,min-limit-z = <3>;
715
716 st,max-limit-x = <(-3)>;
717 st,max-limit-y = <32>;
718 st,max-limit-z = <32>;
719 };
a4d4b153
PM		 720};
721
722&mmc1 {
f1751cff
SR		 723 pinctrl-names = "default";
724 pinctrl-0 = <&mmc1_pins>;
725 vmmc-supply = <&vmmc1>;
726 bus-width = <4>;
727 cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
a4d4b153
PM		 728};
729
edd5eb4e 730/* most boards use vaux3, only some old versions use vmmc2 instead */
a4d4b153 731&mmc2 {
edd5eb4e
TL		 732 pinctrl-names = "default";
733 pinctrl-0 = <&mmc2_pins>;
734 vmmc-supply = <&vaux3>;
735 vmmc_aux-supply = <&vsim>;
736 bus-width = <8>;
737 non-removable;
4cf48f1d
PR		 738 no-sdio;
739 no-sd;
a4d4b153
PM		 740};
741
742&mmc3 {
743 status = "disabled";
744};
745
8699d2dd 746&gpmc {
271d4c6b
TL		 747 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
748 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
9a894953
TL		 749 pinctrl-names = "default";
750 pinctrl-0 = <&gpmc_pins>;
8699d2dd 751
e2c5eb78 752 /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
8699d2dd
SR		 753 onenand@0,0 {
754 #address-cells = <1>;
755 #size-cells = <1>;
e2c5eb78 756 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
8699d2dd
SR		 757
758 gpmc,sync-read;
759 gpmc,sync-write;
760 gpmc,burst-length = <16>;
761 gpmc,burst-read;
762 gpmc,burst-wrap;
763 gpmc,burst-write;
764 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
765 gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
766 gpmc,cs-on-ns = <0>;
767 gpmc,cs-rd-off-ns = <87>;
768 gpmc,cs-wr-off-ns = <87>;
769 gpmc,adv-on-ns = <0>;
770 gpmc,adv-rd-off-ns = <10>;
771 gpmc,adv-wr-off-ns = <10>;
772 gpmc,oe-on-ns = <15>;
773 gpmc,oe-off-ns = <87>;
774 gpmc,we-on-ns = <0>;
775 gpmc,we-off-ns = <87>;
776 gpmc,rd-cycle-ns = <112>;
777 gpmc,wr-cycle-ns = <112>;
778 gpmc,access-ns = <81>;
779 gpmc,page-burst-access-ns = <15>;
780 gpmc,bus-turnaround-ns = <0>;
781 gpmc,cycle2cycle-delay-ns = <0>;
782 gpmc,wait-monitoring-ns = <0>;
783 gpmc,clk-activation-ns = <5>;
784 gpmc,wr-data-mux-bus-ns = <30>;
785 gpmc,wr-access-ns = <81>;
786 gpmc,sync-clk-ps = <15000>;
787
788 /*
789 * MTD partition table corresponding to Nokia's
790 * Maemo 5 (Fremantle) release.
791 */
792 partition@0 {
793 label = "bootloader";
794 reg = <0x00000000 0x00020000>;
795 read-only;
796 };
797 partition@1 {
798 label = "config";
799 reg = <0x00020000 0x00060000>;
800 };
801 partition@2 {
802 label = "log";
803 reg = <0x00080000 0x00040000>;
804 };
805 partition@3 {
806 label = "kernel";
807 reg = <0x000c0000 0x00200000>;
808 };
809 partition@4 {
810 label = "initfs";
811 reg = <0x002c0000 0x00200000>;
812 };
813 partition@5 {
814 label = "rootfs";
815 reg = <0x004c0000 0x0fb40000>;
816 };
817 };
271d4c6b 818
7ac72746 819 /* Ethernet is on some early development boards and qemu */
271d4c6b
TL		 820 ethernet@gpmc {
821 compatible = "smsc,lan91c94";
822 interrupt-parent = <&gpio2>;
823 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
cb9071d4 824 reg = <1 0 0xf>; /* 16 byte IO range */
271d4c6b
TL		 825 bank-width = <2>;
826 pinctrl-names = "default";
827 pinctrl-0 = <&ethernet_pins>;
7d2911c4
TL		 828 power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */
829 reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */
271d4c6b
TL		 830 gpmc,device-width = <2>;
831 gpmc,sync-clk-ps = <0>;
832 gpmc,cs-on-ns = <0>;
833 gpmc,cs-rd-off-ns = <48>;
834 gpmc,cs-wr-off-ns = <24>;
835 gpmc,adv-on-ns = <0>;
836 gpmc,adv-rd-off-ns = <0>;
837 gpmc,adv-wr-off-ns = <0>;
838 gpmc,we-on-ns = <12>;
839 gpmc,we-off-ns = <18>;
840 gpmc,oe-on-ns = <12>;
841 gpmc,oe-off-ns = <48>;
842 gpmc,page-burst-access-ns = <0>;
843 gpmc,access-ns = <42>;
844 gpmc,rd-cycle-ns = <180>;
845 gpmc,wr-cycle-ns = <180>;
846 gpmc,bus-turnaround-ns = <0>;
847 gpmc,cycle2cycle-delay-ns = <0>;
848 gpmc,wait-monitoring-ns = <0>;
849 gpmc,clk-activation-ns = <0>;
850 gpmc,wr-access-ns = <0>;
851 gpmc,wr-data-mux-bus-ns = <12>;
852 };
8699d2dd
SR		 853};
854
a4d4b153
PM		 855&mcspi1 {
856 /*
857 * For some reason, touchscreen is necessary for screen to work at
858 * all on real hw. It works well without it on emulator.
859 *
860 * Also... order in the device tree actually matters here.
861 */
862 tsc2005@0 {
50525891 863 compatible = "ti,tsc2005";
a4d4b153
PM		 864 spi-max-frequency = <6000000>;
865 reg = <0>;
50525891
SR		 866
867 vio-supply = <&vio>;
868
869 reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
870 interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */
871
872 touchscreen-fuzz-x = <4>;
873 touchscreen-fuzz-y = <7>;
874 touchscreen-fuzz-pressure = <2>;
8770d089
PM		 875 touchscreen-size-x = <4096>;
876 touchscreen-size-y = <4096>;
50525891
SR		 877 touchscreen-max-pressure = <2048>;
878
879 ti,x-plate-ohms = <280>;
880 ti,esd-recovery-timeout-ms = <8000>;
a4d4b153 881 };
1133420f
TV		 882
883 acx565akm@2 {
884 compatible = "sony,acx565akm";
a4d4b153
PM		 885 spi-max-frequency = <6000000>;
886 reg = <2>;
d1e6f516
SR		 887
888 pinctrl-names = "default";
1133420f
TV		 889 pinctrl-0 = <&acx565akm_pins>;
890
891 label = "lcd";
892 reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */
893
894 port {
895 lcd_in: endpoint {
896 remote-endpoint = <&sdi_out>;
897 };
898 };
a4d4b153
PM		 899 };
900};
901
c1ad2206
SR		 902&mcspi4 {
903 pinctrl-names = "default";
904 pinctrl-0 = <&mcspi4_pins>;
905
906 wl1251@0 {
907 pinctrl-names = "default";
908 pinctrl-0 = <&wl1251_pins>;
909
910 vio-supply = <&vio>;
911
912 compatible = "ti,wl1251";
913 reg = <0>;
914 spi-max-frequency = <48000000>;
915
916 spi-cpol;
917 spi-cpha;
918
919 ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
920
921 interrupt-parent = <&gpio2>;
922 interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */
923 };
924};
925
a4d4b153
PM		 926&usb_otg_hs {
927 interface-type = <0>;
928 usb-phy = <&usb2_phy>;
d2afcf09
RQ		 929 phys = <&usb2_phy>;
930 phy-names = "usb2-phy";
a4d4b153
PM		 931 mode = <2>;
932 power = <50>;
933};
7a89eecf
SR		 934
935&uart1 {
936 status = "disabled";
937};
938
939&uart2 {
31f0820a 940 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
7a89eecf
SR		 941 pinctrl-names = "default";
942 pinctrl-0 = <&uart2_pins>;
943};
944
945&uart3 {
31f0820a 946 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
7a89eecf
SR		 947 pinctrl-names = "default";
948 pinctrl-0 = <&uart3_pins>;
949};
1133420f
TV		 950
951&dss {
952 status = "ok";
953
954 pinctrl-names = "default";
955 pinctrl-0 = <&dss_sdi_pins>;
956
957 vdds_sdi-supply = <&vaux1>;
958
959 ports {
960 #address-cells = <1>;
961 #size-cells = <0>;
962
963 port@1 {
964 reg = <1>;
965
966 sdi_out: endpoint {
967 remote-endpoint = <&lcd_in>;
968 datapairs = <2>;
969 };
970 };
971 };
972};
973
974&venc {
975 status = "ok";
976
977 vdda-supply = <&vdac>;
978
979 port {
980 venc_out: endpoint {
981 remote-endpoint = <&tv_connector_in>;
982 ti,channels = <1>;
983 };
984 };
985};
f7d0f2a0
SR		 986
987&mcbsp2 {
988 status = "ok";
989};
782e25a4
SR		 990
991&ssi_port1 {
992 pinctrl-names = "default";
993 pinctrl-0 = <&ssi_pins>;
994
995 ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
76ad4ac1
SR		 996
997 modem: hsi-client {
998 compatible = "nokia,n900-modem";
999
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&modem_pins>;
1002
1003 hsi-channel-ids = <0>, <1>, <2>, <3>;
1004 hsi-channel-names = "mcsaab-control",
1005 "speech-control",
1006 "speech-data",
1007 "mcsaab-data";
1008 hsi-speed-kbps = <55000>;
1009 hsi-mode = "frame";
1010 hsi-flow = "synchronized";
1011 hsi-arb-mode = "round-robin";
1012
1013 interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
1014
1015 gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */
1016 <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */
1017 <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
1018 <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
1019 <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
1020 gpio-names = "cmt_apeslpx",
1021 "cmt_rst_rq",
1022 "cmt_en",
1023 "cmt_rst",
1024 "cmt_bsi";
1025 };
782e25a4
SR		 1026};
1027
1028&ssi_port2 {
1029 status = "disabled";
76ad4ac1 1030};
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