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Merge branch 'work.misc' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[mirror_ubuntu-jammy-kernel.git] / arch / arm / boot / dts / omap3-n900.dts
CommitLineData
a4d4b153
PM		 1/*
2 * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
c3580bc1 3 * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
a4d4b153
PM		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 (or later) as
7 * published by the Free Software Foundation.
8 */
9
10/dts-v1/;
11
69540a7c 12#include "omap34xx.dtsi"
3fdb7717 13#include <dt-bindings/input/input.h>
a4d4b153 14
69540a7c
PR		 15/*
16 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
17 * for omap AES HW crypto support. When linux kernel try to access memory of AES
18 * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
19 * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
20 * crash anymore) omap AES support will be disabled for all Nokia N900 devices.
21 * There is "unofficial" version of bootloader which enables AES in L3 firewall
22 * but it is not widely used and to prevent kernel crash rather AES is disabled.
23 * There is also no runtime detection code if AES is disabled in L3 firewall...
24 */
25&aes {
26 status = "disabled";
27};
28
a4d4b153
PM		 29/ {
30 model = "Nokia N900";
c3580bc1 31 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
a4d4b153 32
1861cda0
ID		 33 aliases {
34 i2c0;
35 i2c1 = &i2c1;
36 i2c2 = &i2c2;
37 i2c3 = &i2c3;
38 };
39
a4d4b153
PM		 40 cpus {
41 cpu@0 {
42 cpu0-supply = <&vcc>;
43 };
44 };
45
c1be2032
TL		 46 leds {
47 compatible = "gpio-leds";
48 heartbeat {
49 label = "debug::sleep";
f585a15c 50 gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */
c1be2032
TL		 51 linux,default-trigger = "default-on";
52 pinctrl-names = "default";
53 pinctrl-0 = <&debug_leds>;
54 };
55 };
56
81777ff9 57 memory@80000000 {
a4d4b153
PM		 58 device_type = "memory";
59 reg = <0x80000000 0x10000000>; /* 256 MB */
60 };
61
3931c839
SR		 62 gpio_keys {
63 compatible = "gpio-keys";
64
65 camera_lens_cover {
66 label = "Camera Lens Cover";
67 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */
97d7f2ff
PR		 68 linux,input-type = <EV_SW>;
69 linux,code = <SW_CAMERA_LENS_COVER>;
05cf1e03 70 linux,can-disable;
3931c839
SR		 71 };
72
73 camera_focus {
74 label = "Camera Focus";
75 gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */
97d7f2ff 76 linux,code = <KEY_CAMERA_FOCUS>;
05cf1e03 77 linux,can-disable;
3931c839
SR		 78 };
79
80 camera_capture {
81 label = "Camera Capture";
82 gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */
97d7f2ff 83 linux,code = <KEY_CAMERA>;
05cf1e03 84 linux,can-disable;
3931c839
SR		 85 };
86
87 lock_button {
88 label = "Lock Button";
89 gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */
97d7f2ff 90 linux,code = <KEY_SCREENLOCK>;
05cf1e03 91 linux,can-disable;
3931c839
SR		 92 };
93
94 keypad_slide {
95 label = "Keypad Slide";
96 gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */
97d7f2ff
PR		 97 linux,input-type = <EV_SW>;
98 linux,code = <SW_KEYPAD_SLIDE>;
05cf1e03 99 linux,can-disable;
3931c839
SR		 100 };
101
102 proximity_sensor {
103 label = "Proximity Sensor";
104 gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */
97d7f2ff
PR		 105 linux,input-type = <EV_SW>;
106 linux,code = <SW_FRONT_PROXIMITY>;
05cf1e03 107 linux,can-disable;
3931c839
SR		 108 };
109 };
110
b950762c
PR		 111 isp1707: isp1707 {
112 compatible = "nxp,isp1707";
e17337a2
SR		 113 nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
114 usb-phy = <&usb2_phy>;
115 };
1133420f
TV		 116
117 tv: connector {
32797b3e 118 compatible = "composite-video-connector";
1133420f
TV		 119 label = "tv";
120
121 port {
122 tv_connector_in: endpoint {
123 remote-endpoint = <&venc_out>;
124 };
125 };
126 };
f7d0f2a0
SR		 127
128 sound: n900-audio {
129 compatible = "nokia,n900-audio";
130
131 nokia,cpu-dai = <&mcbsp2>;
132 nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>;
133 nokia,headphone-amplifier = <&tpa6130a2>;
134
135 tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */
136 jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */
137 eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
138 speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
139 };
28398c69
SR		 140
141 battery: n900-battery {
142 compatible = "nokia,n900-battery";
143 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
144 io-channel-names = "temp", "bsi", "vbat";
145 };
e7c86821 146
cc9a4bda 147 pwm9: dmtimer-pwm {
e7c86821
ID		 148 compatible = "ti,omap-dmtimer-pwm";
149 #pwm-cells = <3>;
150 ti,timers = <&timer9>;
151 ti,clock-source = <0x00>; /* timer_sys_ck */
152 };
153
154 ir: n900-ir {
155 compatible = "nokia,n900-ir";
156 pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
157 };
3d5c6568
SR		 158
159 /* controlled (enabled/disabled) directly by bcm2048 and wl1251 */
160 vctcxo: vctcxo {
161 compatible = "fixed-clock";
162 #clock-cells = <0>;
163 clock-frequency = <38400000>;
164 };
a4d4b153
PM		 165};
166
d510d12f
PM		 167&isp {
168 vdds_csib-supply = <&vaux2>;
169
170 pinctrl-names = "default";
171 pinctrl-0 = <&camera_pins>;
172
173 ports {
174 port@1 {
175 reg = <1>;
176
177 csi_isp: endpoint {
178 remote-endpoint = <&csi_cam1>;
179 bus-type = <3>; /* CCP2 */
180 clock-lanes = <1>;
181 data-lanes = <0>;
182 lane-polarity = <0 0>;
d510d12f
PM		 183 /* Select strobe = <1> for back camera, <0> for front camera */
184 strobe = <1>;
d510d12f
PM		 185 };
186 };
187 };
188};
189
ac888a88
SR		 190&omap3_pmx_core {
191 pinctrl-names = "default";
192
7a89eecf
SR		 193 uart2_pins: pinmux_uart2_pins {
194 pinctrl-single,pins = <
3d5c6568
SR		 195 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
196 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */
675e457c 197 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
3d5c6568 198 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
7a89eecf
SR		 199 >;
200 };
201
202 uart3_pins: pinmux_uart3_pins {
203 pinctrl-single,pins = <
675e457c
JMC		 204 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */
205 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */
7a89eecf
SR		 206 >;
207 };
208
271d4c6b
TL		 209 ethernet_pins: pinmux_ethernet_pins {
210 pinctrl-single,pins = <
211 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
212 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
213 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
214 >;
215 };
216
9a894953
TL		 217 gpmc_pins: pinmux_gpmc_pins {
218 pinctrl-single,pins = <
219
220 /* address lines */
221 OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
222 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
223 OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
224
225 /* data lines, gpmc_d0..d7 not muxable according to TRM */
226 OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
227 OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
228 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
229 OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
230 OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
231 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
232 OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
233 OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
234
235 /*
236 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
237 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
238 */
239 OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
240 OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
241 >;
242 };
243
ac888a88
SR		 244 i2c1_pins: pinmux_i2c1_pins {
245 pinctrl-single,pins = <
675e457c
JMC		 246 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
247 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
ac888a88
SR		 248 >;
249 };
250
251 i2c2_pins: pinmux_i2c2_pins {
252 pinctrl-single,pins = <
675e457c
JMC		 253 OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
254 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
ac888a88
SR		 255 >;
256 };
257
258 i2c3_pins: pinmux_i2c3_pins {
259 pinctrl-single,pins = <
675e457c
JMC		 260 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
261 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
ac888a88
SR		 262 >;
263 };
f1751cff 264
c1be2032
TL		 265 debug_leds: pinmux_debug_led_pins {
266 pinctrl-single,pins = <
267 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */
268 >;
269 };
270
c1ad2206
SR		 271 mcspi4_pins: pinmux_mcspi4_pins {
272 pinctrl-single,pins = <
675e457c
JMC		 273 OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
274 OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
275 OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
276 OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
c1ad2206
SR		 277 >;
278 };
279
f1751cff
SR		 280 mmc1_pins: pinmux_mmc1_pins {
281 pinctrl-single,pins = <
675e457c
JMC		 282 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
283 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */
284 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */
285 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */
286 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */
287 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */
f1751cff
SR		 288 >;
289 };
d1e6f516 290
edd5eb4e
TL		 291 mmc2_pins: pinmux_mmc2_pins {
292 pinctrl-single,pins = <
675e457c
JMC		 293 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
294 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
295 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
296 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
297 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
298 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
299 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
300 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
301 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
302 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
edd5eb4e
TL		 303 >;
304 };
305
1133420f 306 acx565akm_pins: pinmux_acx565akm_pins {
d1e6f516 307 pinctrl-single,pins = <
675e457c 308 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
d1e6f516
SR		 309 >;
310 };
1133420f
TV		 311
312 dss_sdi_pins: pinmux_dss_sdi_pins {
313 pinctrl-single,pins = <
675e457c
JMC		 314 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */
315 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */
316 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */
317 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */
1133420f 318
675e457c
JMC		 319 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */
320 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */
1133420f
TV		 321 >;
322 };
c1ad2206
SR		 323
324 wl1251_pins: pinmux_wl1251 {
325 pinctrl-single,pins = <
675e457c
JMC		 326 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */
327 OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */
c1ad2206
SR		 328 >;
329 };
782e25a4
SR		 330
331 ssi_pins: pinmux_ssi {
332 pinctrl-single,pins = <
675e457c
JMC		 333 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
334 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
e0e80d43 335 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
675e457c
JMC		 336 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
337 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
338 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
339 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
340 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
782e25a4
SR		 341 >;
342 };
76ad4ac1
SR		 343
344 modem_pins: pinmux_modem {
345 pinctrl-single,pins = <
675e457c 346 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
e0e80d43 347 OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */
675e457c
JMC		 348 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
349 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
350 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
351 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
76ad4ac1
SR		 352 >;
353 };
d510d12f
PM		 354
355 camera_pins: pinmux_camera {
356 pinctrl-single,pins = <
357 OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */
358 OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */
359 OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */
360 OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */
361 OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */
362 OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */
363 OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */
364 OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */
365 OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */
366 OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */
367 OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */
368 >;
369 };
ac888a88
SR		 370};
371
a4d4b153 372&i2c1 {
ac888a88
SR		 373 pinctrl-names = "default";
374 pinctrl-0 = <&i2c1_pins>;
375
a4d4b153
PM		 376 clock-frequency = <2200000>;
377
378 twl: twl@48 {
379 reg = <0x48>;
380 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
381 interrupt-parent = <&intc>;
382 };
383};
384
385#include "twl4030.dtsi"
ac888a88 386#include "twl4030_omap3.dtsi"
a4d4b153 387
9cdbbadd
SR		 388&vaux1 {
389 regulator-name = "V28";
390 regulator-min-microvolt = <2800000>;
391 regulator-max-microvolt = <2800000>;
0698178c 392 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
14fd7330 393 regulator-always-on; /* due to battery cover sensor */
9cdbbadd
SR		 394};
395
396&vaux2 {
397 regulator-name = "VCSI";
398 regulator-min-microvolt = <1800000>;
399 regulator-max-microvolt = <1800000>;
0698178c 400 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 401};
402
403&vaux3 {
404 regulator-name = "VMMC2_30";
405 regulator-min-microvolt = <2800000>;
406 regulator-max-microvolt = <3000000>;
0698178c 407 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 408};
409
410&vaux4 {
411 regulator-name = "VCAM_ANA_28";
412 regulator-min-microvolt = <2800000>;
413 regulator-max-microvolt = <2800000>;
0698178c 414 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 415};
416
417&vmmc1 {
418 regulator-name = "VMMC1";
419 regulator-min-microvolt = <1850000>;
420 regulator-max-microvolt = <3150000>;
0698178c 421 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 422};
423
424&vmmc2 {
425 regulator-name = "V28_A";
426 regulator-min-microvolt = <2800000>;
427 regulator-max-microvolt = <3000000>;
0698178c 428 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 429 regulator-always-on; /* due VIO leak to AIC34 VDDs */
430};
431
432&vpll1 {
433 regulator-name = "VPLL";
434 regulator-min-microvolt = <1800000>;
435 regulator-max-microvolt = <1800000>;
0698178c 436 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 437 regulator-always-on;
438};
439
440&vpll2 {
441 regulator-name = "VSDI_CSI";
442 regulator-min-microvolt = <1800000>;
443 regulator-max-microvolt = <1800000>;
0698178c 444 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 445 regulator-always-on;
446};
447
448&vsim {
449 regulator-name = "VMMC2_IO_18";
450 regulator-min-microvolt = <1800000>;
451 regulator-max-microvolt = <1800000>;
0698178c 452 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 453};
454
455&vio {
456 regulator-name = "VIO";
457 regulator-min-microvolt = <1800000>;
458 regulator-max-microvolt = <1800000>;
9cdbbadd
SR		 459};
460
461&vintana1 {
462 regulator-name = "VINTANA1";
463 /* fixed to 1500000 */
464 regulator-always-on;
465};
466
467&vintana2 {
468 regulator-name = "VINTANA2";
469 regulator-min-microvolt = <2750000>;
470 regulator-max-microvolt = <2750000>;
471 regulator-always-on;
472};
473
474&vintdig {
475 regulator-name = "VINTDIG";
476 /* fixed to 1500000 */
477 regulator-always-on;
478};
479
06ba7a61
SR		 480&twl {
481 twl_audio: audio {
482 compatible = "ti,twl4030-audio";
483 ti,enable-vibra = <1>;
484 };
9188883f
TL		 485
486 twl_power: power {
daebabd5 487 compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
9188883f
TL		 488 ti,use_poweroff;
489 };
06ba7a61
SR		 490};
491
85c215f3 492&twl_keypad {
3fdb7717
SR		 493 linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q)
494 MATRIX_KEY(0x00, 0x01, KEY_O)
495 MATRIX_KEY(0x00, 0x02, KEY_P)
496 MATRIX_KEY(0x00, 0x03, KEY_COMMA)
497 MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE)
498 MATRIX_KEY(0x00, 0x06, KEY_A)
499 MATRIX_KEY(0x00, 0x07, KEY_S)
500
501 MATRIX_KEY(0x01, 0x00, KEY_W)
502 MATRIX_KEY(0x01, 0x01, KEY_D)
503 MATRIX_KEY(0x01, 0x02, KEY_F)
504 MATRIX_KEY(0x01, 0x03, KEY_G)
505 MATRIX_KEY(0x01, 0x04, KEY_H)
506 MATRIX_KEY(0x01, 0x05, KEY_J)
507 MATRIX_KEY(0x01, 0x06, KEY_K)
508 MATRIX_KEY(0x01, 0x07, KEY_L)
509
510 MATRIX_KEY(0x02, 0x00, KEY_E)
511 MATRIX_KEY(0x02, 0x01, KEY_DOT)
512 MATRIX_KEY(0x02, 0x02, KEY_UP)
513 MATRIX_KEY(0x02, 0x03, KEY_ENTER)
514 MATRIX_KEY(0x02, 0x05, KEY_Z)
515 MATRIX_KEY(0x02, 0x06, KEY_X)
516 MATRIX_KEY(0x02, 0x07, KEY_C)
517 MATRIX_KEY(0x02, 0x08, KEY_F9)
518
519 MATRIX_KEY(0x03, 0x00, KEY_R)
520 MATRIX_KEY(0x03, 0x01, KEY_V)
521 MATRIX_KEY(0x03, 0x02, KEY_B)
522 MATRIX_KEY(0x03, 0x03, KEY_N)
523 MATRIX_KEY(0x03, 0x04, KEY_M)
524 MATRIX_KEY(0x03, 0x05, KEY_SPACE)
525 MATRIX_KEY(0x03, 0x06, KEY_SPACE)
526 MATRIX_KEY(0x03, 0x07, KEY_LEFT)
527
528 MATRIX_KEY(0x04, 0x00, KEY_T)
529 MATRIX_KEY(0x04, 0x01, KEY_DOWN)
530 MATRIX_KEY(0x04, 0x02, KEY_RIGHT)
531 MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL)
532 MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT)
533 MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT)
534 MATRIX_KEY(0x04, 0x08, KEY_F10)
535
536 MATRIX_KEY(0x05, 0x00, KEY_Y)
537 MATRIX_KEY(0x05, 0x08, KEY_F11)
538
539 MATRIX_KEY(0x06, 0x00, KEY_U)
540
541 MATRIX_KEY(0x07, 0x00, KEY_I)
542 MATRIX_KEY(0x07, 0x01, KEY_F7)
543 MATRIX_KEY(0x07, 0x02, KEY_F8)
85c215f3
SR		 544 >;
545};
546
a4d4b153
PM		 547&twl_gpio {
548 ti,pullups = <0x0>;
549 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
550};
551
552&i2c2 {
ac888a88
SR		 553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c2_pins>;
555
48fc9864 556 clock-frequency = <100000>;
b2b9b258 557
14e3e295
SR		 558 tlv320aic3x: tlv320aic3x@18 {
559 compatible = "ti,tlv320aic3x";
560 reg = <0x18>;
561 gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
562 ai3x-gpio-func = <
563 0 /* AIC3X_GPIO1_FUNC_DISABLED */
564 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
565 >;
566
567 AVDD-supply = <&vmmc2>;
568 DRVDD-supply = <&vmmc2>;
569 IOVDD-supply = <&vio>;
570 DVDD-supply = <&vio>;
1819e303
PM		 571
572 ai3x-micbias-vg = <1>;
14e3e295
SR		 573 };
574
575 tlv320aic3x_aux: tlv320aic3x@19 {
576 compatible = "ti,tlv320aic3x";
577 reg = <0x19>;
578 gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
579
580 AVDD-supply = <&vmmc2>;
581 DRVDD-supply = <&vmmc2>;
582 IOVDD-supply = <&vio>;
583 DVDD-supply = <&vio>;
1819e303
PM		 584
585 ai3x-micbias-vg = <2>;
14e3e295
SR		 586 };
587
12f2f873
SR		 588 tsl2563: tsl2563@29 {
589 compatible = "amstaos,tsl2563";
590 reg = <0x29>;
591
592 amstaos,cover-comp-gain = <16>;
593 };
594
14628e44
PR		 595 adp1653: led-controller@30 {
596 compatible = "adi,adp1653";
597 reg = <0x30>;
598 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */
599
600 flash {
601 flash-timeout-us = <500000>;
602 flash-max-microamp = <320000>;
603 led-max-microamp = <50000>;
604 };
605 indicator {
606 led-max-microamp = <17500>;
607 };
608 };
609
a0bf1f3e
SR		 610 lp5523: lp5523@32 {
611 compatible = "national,lp5523";
612 reg = <0x32>;
613 clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
614 enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */
615
616 chan0 {
617 chan-name = "lp5523:kb1";
618 led-cur = /bits/ 8 <50>;
619 max-cur = /bits/ 8 <100>;
620 };
621
622 chan1 {
623 chan-name = "lp5523:kb2";
624 led-cur = /bits/ 8 <50>;
625 max-cur = /bits/ 8 <100>;
626 };
627
628 chan2 {
629 chan-name = "lp5523:kb3";
630 led-cur = /bits/ 8 <50>;
631 max-cur = /bits/ 8 <100>;
632 };
633
634 chan3 {
635 chan-name = "lp5523:kb4";
636 led-cur = /bits/ 8 <50>;
637 max-cur = /bits/ 8 <100>;
638 };
639
640 chan4 {
641 chan-name = "lp5523:b";
642 led-cur = /bits/ 8 <50>;
643 max-cur = /bits/ 8 <100>;
644 };
645
646 chan5 {
647 chan-name = "lp5523:g";
648 led-cur = /bits/ 8 <50>;
649 max-cur = /bits/ 8 <100>;
650 };
651
652 chan6 {
653 chan-name = "lp5523:r";
654 led-cur = /bits/ 8 <50>;
655 max-cur = /bits/ 8 <100>;
656 };
657
658 chan7 {
659 chan-name = "lp5523:kb5";
660 led-cur = /bits/ 8 <50>;
661 max-cur = /bits/ 8 <100>;
662 };
663
664 chan8 {
665 chan-name = "lp5523:kb6";
666 led-cur = /bits/ 8 <50>;
667 max-cur = /bits/ 8 <100>;
668 };
669 };
670
b2b9b258
SR		 671 bq27200: bq27200@55 {
672 compatible = "ti,bq27200";
673 reg = <0x55>;
674 };
9e2367c8 675
f585a15c 676 /* Stereo headphone amplifier */
9e2367c8
SR		 677 tpa6130a2: tpa6130a2@60 {
678 compatible = "ti,tpa6130a2";
679 reg = <0x60>;
680
681 Vdd-supply = <&vmmc2>;
682
683 power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
684 };
334a09c8 685
406c07e7
SR		 686 si4713: si4713@63 {
687 compatible = "silabs,si4713";
688 reg = <0x63>;
689
690 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
691 reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
692 vio-supply = <&vio>;
693 vdd-supply = <&vaux1>;
694 };
695
334a09c8
SR		 696 bq24150a: bq24150a@6b {
697 compatible = "ti,bq24150a";
698 reg = <0x6b>;
699
700 ti,current-limit = <100>;
701 ti,weak-battery-voltage = <3400>;
702 ti,battery-regulation-voltage = <4200>;
703 ti,charge-current = <650>;
704 ti,termination-current = <100>;
705 ti,resistor-sense = <68>;
706
b950762c 707 ti,usb-charger-detection = <&isp1707>;
334a09c8 708 };
a4d4b153
PM		 709};
710
711&i2c3 {
ac888a88
SR		 712 pinctrl-names = "default";
713 pinctrl-0 = <&i2c3_pins>;
714
48fc9864 715 clock-frequency = <400000>;
1ac4e6fe
SR		 716
717 lis302dl: lis3lv02d@1d {
718 compatible = "st,lis3lv02d";
719 reg = <0x1d>;
720
721 Vdd-supply = <&vaux1>;
722 Vdd_IO-supply = <&vio>;
723
724 interrupt-parent = <&gpio6>;
725 interrupts = <21 20>; /* 181 and 180 */
726
727 /* click flags */
728 st,click-single-x;
729 st,click-single-y;
730 st,click-single-z;
731
732 /* Limits are 0.5g * value */
733 st,click-threshold-x = <8>;
734 st,click-threshold-y = <8>;
735 st,click-threshold-z = <10>;
736
737 /* Click must be longer than time limit */
738 st,click-time-limit = <9>;
739
740 /* Kind of debounce filter */
741 st,click-latency = <50>;
742
743 /* Interrupt line 2 for click detection */
744 st,irq2-click;
745
746 st,wakeup-x-hi;
747 st,wakeup-y-hi;
748 st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
749
750 st,wakeup2-z-hi;
751 st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */
752
753 st,hipass1-disable;
754 st,hipass2-disable;
755
756 st,axis-x = <1>; /* LIS3_DEV_X */
757 st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
758 st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
759
760 st,min-limit-x = <(-32)>;
761 st,min-limit-y = <3>;
762 st,min-limit-z = <3>;
763
764 st,max-limit-x = <(-3)>;
765 st,max-limit-y = <32>;
766 st,max-limit-z = <32>;
767 };
d510d12f
PM		 768
769 cam1: camera@3e {
770 compatible = "toshiba,et8ek8";
771 reg = <0x3e>;
772
773 vana-supply = <&vaux4>;
774
775 clocks = <&isp 0>;
776 clock-names = "extclk";
777 clock-frequency = <9600000>;
778
779 reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
780
781 port {
782 csi_cam1: endpoint {
783 bus-type = <3>; /* CCP2 */
784 strobe = <1>;
785 clock-inv = <0>;
786 crc = <1>;
787
788 remote-endpoint = <&csi_isp>;
789 };
790 };
791 };
792
793 /* D/A converter for auto-focus */
8dccafaa 794 ad5820: dac@c {
d510d12f
PM		 795 compatible = "adi,ad5820";
796 reg = <0x0c>;
797
798 VANA-supply = <&vaux4>;
799
800 #io-channel-cells = <0>;
801 };
a4d4b153
PM		 802};
803
804&mmc1 {
f1751cff
SR		 805 pinctrl-names = "default";
806 pinctrl-0 = <&mmc1_pins>;
807 vmmc-supply = <&vmmc1>;
808 bus-width = <4>;
d510d12f
PM		 809 /* For debugging, it is often good idea to remove this GPIO.
810 It means you can remove back cover (to reboot by removing
811 battery) and still use the MMC card. */
f1751cff 812 cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
a4d4b153
PM		 813};
814
edd5eb4e 815/* most boards use vaux3, only some old versions use vmmc2 instead */
a4d4b153 816&mmc2 {
edd5eb4e
TL		 817 pinctrl-names = "default";
818 pinctrl-0 = <&mmc2_pins>;
819 vmmc-supply = <&vaux3>;
45ea75eb 820 vqmmc-supply = <&vsim>;
edd5eb4e
TL		 821 bus-width = <8>;
822 non-removable;
4cf48f1d
PR		 823 no-sdio;
824 no-sd;
a4d4b153
PM		 825};
826
827&mmc3 {
828 status = "disabled";
829};
830
8699d2dd 831&gpmc {
271d4c6b
TL		 832 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
833 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
9a894953
TL		 834 pinctrl-names = "default";
835 pinctrl-0 = <&gpmc_pins>;
8699d2dd 836
e2c5eb78 837 /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
8699d2dd
SR		 838 onenand@0,0 {
839 #address-cells = <1>;
840 #size-cells = <1>;
396744b7 841 compatible = "ti,omap2-onenand";
e2c5eb78 842 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
8699d2dd
SR		 843
844 gpmc,sync-read;
845 gpmc,sync-write;
846 gpmc,burst-length = <16>;
847 gpmc,burst-read;
848 gpmc,burst-wrap;
849 gpmc,burst-write;
850 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
851 gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
852 gpmc,cs-on-ns = <0>;
853 gpmc,cs-rd-off-ns = <87>;
854 gpmc,cs-wr-off-ns = <87>;
855 gpmc,adv-on-ns = <0>;
856 gpmc,adv-rd-off-ns = <10>;
857 gpmc,adv-wr-off-ns = <10>;
858 gpmc,oe-on-ns = <15>;
859 gpmc,oe-off-ns = <87>;
860 gpmc,we-on-ns = <0>;
861 gpmc,we-off-ns = <87>;
862 gpmc,rd-cycle-ns = <112>;
863 gpmc,wr-cycle-ns = <112>;
864 gpmc,access-ns = <81>;
865 gpmc,page-burst-access-ns = <15>;
866 gpmc,bus-turnaround-ns = <0>;
867 gpmc,cycle2cycle-delay-ns = <0>;
868 gpmc,wait-monitoring-ns = <0>;
869 gpmc,clk-activation-ns = <5>;
870 gpmc,wr-data-mux-bus-ns = <30>;
871 gpmc,wr-access-ns = <81>;
872 gpmc,sync-clk-ps = <15000>;
873
874 /*
875 * MTD partition table corresponding to Nokia's
876 * Maemo 5 (Fremantle) release.
877 */
878 partition@0 {
879 label = "bootloader";
880 reg = <0x00000000 0x00020000>;
881 read-only;
882 };
883 partition@1 {
884 label = "config";
885 reg = <0x00020000 0x00060000>;
886 };
887 partition@2 {
888 label = "log";
889 reg = <0x00080000 0x00040000>;
890 };
891 partition@3 {
892 label = "kernel";
893 reg = <0x000c0000 0x00200000>;
894 };
895 partition@4 {
896 label = "initfs";
897 reg = <0x002c0000 0x00200000>;
898 };
899 partition@5 {
900 label = "rootfs";
901 reg = <0x004c0000 0x0fb40000>;
902 };
903 };
271d4c6b 904
7ac72746 905 /* Ethernet is on some early development boards and qemu */
271d4c6b
TL		 906 ethernet@gpmc {
907 compatible = "smsc,lan91c94";
908 interrupt-parent = <&gpio2>;
909 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
cb9071d4 910 reg = <1 0 0xf>; /* 16 byte IO range */
271d4c6b
TL		 911 bank-width = <2>;
912 pinctrl-names = "default";
913 pinctrl-0 = <&ethernet_pins>;
7d2911c4
TL		 914 power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */
915 reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */
271d4c6b
TL		 916 gpmc,device-width = <2>;
917 gpmc,sync-clk-ps = <0>;
918 gpmc,cs-on-ns = <0>;
919 gpmc,cs-rd-off-ns = <48>;
920 gpmc,cs-wr-off-ns = <24>;
921 gpmc,adv-on-ns = <0>;
922 gpmc,adv-rd-off-ns = <0>;
923 gpmc,adv-wr-off-ns = <0>;
924 gpmc,we-on-ns = <12>;
925 gpmc,we-off-ns = <18>;
926 gpmc,oe-on-ns = <12>;
927 gpmc,oe-off-ns = <48>;
928 gpmc,page-burst-access-ns = <0>;
929 gpmc,access-ns = <42>;
930 gpmc,rd-cycle-ns = <180>;
931 gpmc,wr-cycle-ns = <180>;
932 gpmc,bus-turnaround-ns = <0>;
933 gpmc,cycle2cycle-delay-ns = <0>;
934 gpmc,wait-monitoring-ns = <0>;
935 gpmc,clk-activation-ns = <0>;
936 gpmc,wr-access-ns = <0>;
937 gpmc,wr-data-mux-bus-ns = <12>;
938 };
8699d2dd
SR		 939};
940
a4d4b153
PM		 941&mcspi1 {
942 /*
943 * For some reason, touchscreen is necessary for screen to work at
944 * all on real hw. It works well without it on emulator.
945 *
946 * Also... order in the device tree actually matters here.
947 */
948 tsc2005@0 {
50525891 949 compatible = "ti,tsc2005";
a4d4b153
PM		 950 spi-max-frequency = <6000000>;
951 reg = <0>;
50525891
SR		 952
953 vio-supply = <&vio>;
954
955 reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
956 interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */
957
958 touchscreen-fuzz-x = <4>;
959 touchscreen-fuzz-y = <7>;
960 touchscreen-fuzz-pressure = <2>;
8770d089
PM		 961 touchscreen-size-x = <4096>;
962 touchscreen-size-y = <4096>;
50525891
SR		 963 touchscreen-max-pressure = <2048>;
964
965 ti,x-plate-ohms = <280>;
966 ti,esd-recovery-timeout-ms = <8000>;
a4d4b153 967 };
1133420f
TV		 968
969 acx565akm@2 {
970 compatible = "sony,acx565akm";
a4d4b153
PM		 971 spi-max-frequency = <6000000>;
972 reg = <2>;
d1e6f516
SR		 973
974 pinctrl-names = "default";
1133420f
TV		 975 pinctrl-0 = <&acx565akm_pins>;
976
977 label = "lcd";
978 reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */
979
980 port {
981 lcd_in: endpoint {
982 remote-endpoint = <&sdi_out>;
983 };
984 };
a4d4b153
PM		 985 };
986};
987
c1ad2206
SR		 988&mcspi4 {
989 pinctrl-names = "default";
990 pinctrl-0 = <&mcspi4_pins>;
991
992 wl1251@0 {
993 pinctrl-names = "default";
994 pinctrl-0 = <&wl1251_pins>;
995
996 vio-supply = <&vio>;
997
998 compatible = "ti,wl1251";
999 reg = <0>;
1000 spi-max-frequency = <48000000>;
1001
1002 spi-cpol;
1003 spi-cpha;
1004
1005 ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
1006
1007 interrupt-parent = <&gpio2>;
1008 interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */
3d5c6568
SR		 1009
1010 clocks = <&vctcxo>;
c1ad2206
SR		 1011 };
1012};
1013
a4d4b153
PM		 1014&usb_otg_hs {
1015 interface-type = <0>;
1016 usb-phy = <&usb2_phy>;
d2afcf09
RQ		 1017 phys = <&usb2_phy>;
1018 phy-names = "usb2-phy";
a4d4b153
PM		 1019 mode = <2>;
1020 power = <50>;
1021};
7a89eecf
SR		 1022
1023&uart1 {
1024 status = "disabled";
1025};
1026
1027&uart2 {
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&uart2_pins>;
3d5c6568
SR		 1030
1031 bcm2048: bluetooth {
1032 compatible = "brcm,bcm2048-nokia", "nokia,h4p-bluetooth";
1033 reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; /* 91 */
1034 host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */
1035 bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */
1036 clocks = <&vctcxo>;
1037 clock-names = "sysclk";
1038 };
7a89eecf
SR		 1039};
1040
1041&uart3 {
31f0820a 1042 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
7a89eecf
SR		 1043 pinctrl-names = "default";
1044 pinctrl-0 = <&uart3_pins>;
1045};
1133420f
TV		 1046
1047&dss {
1048 status = "ok";
1049
1050 pinctrl-names = "default";
1051 pinctrl-0 = <&dss_sdi_pins>;
1052
1053 vdds_sdi-supply = <&vaux1>;
1054
1055 ports {
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1058
1059 port@1 {
1060 reg = <1>;
1061
1062 sdi_out: endpoint {
1063 remote-endpoint = <&lcd_in>;
1064 datapairs = <2>;
1065 };
1066 };
1067 };
1068};
1069
1070&venc {
1071 status = "ok";
1072
1073 vdda-supply = <&vdac>;
1074
1075 port {
1076 venc_out: endpoint {
1077 remote-endpoint = <&tv_connector_in>;
1078 ti,channels = <1>;
1079 };
1080 };
1081};
f7d0f2a0
SR		 1082
1083&mcbsp2 {
1084 status = "ok";
1085};
782e25a4
SR		 1086
1087&ssi_port1 {
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&ssi_pins>;
1090
1091 ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
76ad4ac1
SR		 1092
1093 modem: hsi-client {
1094 compatible = "nokia,n900-modem";
1095
1096 pinctrl-names = "default";
1097 pinctrl-0 = <&modem_pins>;
1098
1099 hsi-channel-ids = <0>, <1>, <2>, <3>;
1100 hsi-channel-names = "mcsaab-control",
1101 "speech-control",
1102 "speech-data",
1103 "mcsaab-data";
1104 hsi-speed-kbps = <55000>;
1105 hsi-mode = "frame";
1106 hsi-flow = "synchronized";
1107 hsi-arb-mode = "round-robin";
1108
1109 interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
1110
1111 gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */
1112 <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */
1113 <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
1114 <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
1115 <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
1116 gpio-names = "cmt_apeslpx",
1117 "cmt_rst_rq",
1118 "cmt_en",
1119 "cmt_rst",
1120 "cmt_bsi";
1121 };
782e25a4
SR		 1122};
1123
1124&ssi_port2 {
1125 status = "disabled";
76ad4ac1 1126};
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