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a4d4b153
PM
1/*
2 * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
c3580bc1 3 * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
a4d4b153
PM
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 (or later) as
7 * published by the Free Software Foundation.
8 */
9
10/dts-v1/;
11
f2e2c9d9 12#include "omap34xx-hs.dtsi"
3fdb7717 13#include <dt-bindings/input/input.h>
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14
15/ {
16 model = "Nokia N900";
c3580bc1 17 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
a4d4b153
PM
18
19 cpus {
20 cpu@0 {
21 cpu0-supply = <&vcc>;
22 };
23 };
24
c1be2032
TL
25 leds {
26 compatible = "gpio-leds";
27 heartbeat {
28 label = "debug::sleep";
29 gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio162 */
30 linux,default-trigger = "default-on";
31 pinctrl-names = "default";
32 pinctrl-0 = <&debug_leds>;
33 };
34 };
35
a4d4b153
PM
36 memory {
37 device_type = "memory";
38 reg = <0x80000000 0x10000000>; /* 256 MB */
39 };
40
3931c839
SR
41 gpio_keys {
42 compatible = "gpio-keys";
43
44 camera_lens_cover {
45 label = "Camera Lens Cover";
46 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */
47 linux,input-type = <5>; /* EV_SW */
48 linux,code = <0x09>; /* SW_CAMERA_LENS_COVER */
49 gpio-key,wakeup;
50 };
51
52 camera_focus {
53 label = "Camera Focus";
54 gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */
55 linux,code = <0x210>; /* KEY_CAMERA_FOCUS */
56 gpio-key,wakeup;
57 };
58
59 camera_capture {
60 label = "Camera Capture";
61 gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */
62 linux,code = <0xd4>; /* KEY_CAMERA */
63 gpio-key,wakeup;
64 };
65
66 lock_button {
67 label = "Lock Button";
68 gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */
69 linux,code = <0x98>; /* KEY_SCREENLOCK */
70 gpio-key,wakeup;
71 };
72
73 keypad_slide {
74 label = "Keypad Slide";
75 gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */
76 linux,input-type = <5>; /* EV_SW */
77 linux,code = <0x0a>; /* SW_KEYPAD_SLIDE */
78 gpio-key,wakeup;
79 };
80
81 proximity_sensor {
82 label = "Proximity Sensor";
83 gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */
84 linux,input-type = <5>; /* EV_SW */
85 linux,code = <0x0b>; /* SW_FRONT_PROXIMITY */
86 };
87 };
88
e17337a2
SR
89 isp1704: isp1704 {
90 compatible = "nxp,isp1704";
91 nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
92 usb-phy = <&usb2_phy>;
93 };
1133420f
TV
94
95 tv: connector {
32797b3e 96 compatible = "composite-video-connector";
1133420f
TV
97 label = "tv";
98
99 port {
100 tv_connector_in: endpoint {
101 remote-endpoint = <&venc_out>;
102 };
103 };
104 };
f7d0f2a0
SR
105
106 sound: n900-audio {
107 compatible = "nokia,n900-audio";
108
109 nokia,cpu-dai = <&mcbsp2>;
110 nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>;
111 nokia,headphone-amplifier = <&tpa6130a2>;
112
113 tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */
114 jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */
115 eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
116 speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
117 };
28398c69
SR
118
119 battery: n900-battery {
120 compatible = "nokia,n900-battery";
121 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
122 io-channel-names = "temp", "bsi", "vbat";
123 };
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124};
125
ac888a88
SR
126&omap3_pmx_core {
127 pinctrl-names = "default";
128
7a89eecf
SR
129 uart2_pins: pinmux_uart2_pins {
130 pinctrl-single,pins = <
131 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx */
132 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
133 >;
134 };
135
136 uart3_pins: pinmux_uart3_pins {
137 pinctrl-single,pins = <
138 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx */
139 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx */
140 >;
141 };
142
271d4c6b
TL
143 ethernet_pins: pinmux_ethernet_pins {
144 pinctrl-single,pins = <
145 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
146 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
147 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
148 >;
149 };
150
9a894953
TL
151 gpmc_pins: pinmux_gpmc_pins {
152 pinctrl-single,pins = <
153
154 /* address lines */
155 OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
156 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
157 OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
158
159 /* data lines, gpmc_d0..d7 not muxable according to TRM */
160 OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
161 OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
162 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
163 OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
164 OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
165 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
166 OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
167 OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
168
169 /*
170 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
171 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
172 */
173 OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
174 OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
175 >;
176 };
177
ac888a88
SR
178 i2c1_pins: pinmux_i2c1_pins {
179 pinctrl-single,pins = <
a4ff93c1
TL
180 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
181 0x18c (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
ac888a88
SR
182 >;
183 };
184
185 i2c2_pins: pinmux_i2c2_pins {
186 pinctrl-single,pins = <
a4ff93c1
TL
187 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
188 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
ac888a88
SR
189 >;
190 };
191
192 i2c3_pins: pinmux_i2c3_pins {
193 pinctrl-single,pins = <
a4ff93c1
TL
194 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
195 0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
ac888a88
SR
196 >;
197 };
f1751cff 198
c1be2032
TL
199 debug_leds: pinmux_debug_led_pins {
200 pinctrl-single,pins = <
201 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */
202 >;
203 };
204
c1ad2206
SR
205 mcspi4_pins: pinmux_mcspi4_pins {
206 pinctrl-single,pins = <
207 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
208 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
209 0x160 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
210 0x166 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
211 >;
212 };
213
f1751cff
SR
214 mmc1_pins: pinmux_mmc1_pins {
215 pinctrl-single,pins = <
216 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
217 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */
218 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */
219 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */
220 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */
221 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */
222 >;
223 };
d1e6f516 224
edd5eb4e
TL
225 mmc2_pins: pinmux_mmc2_pins {
226 pinctrl-single,pins = <
227 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
228 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
229 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
230 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
231 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
232 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
233 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
234 0x136 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
235 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
236 0x13a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
237 >;
238 };
239
1133420f 240 acx565akm_pins: pinmux_acx565akm_pins {
d1e6f516
SR
241 pinctrl-single,pins = <
242 0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
243 >;
244 };
1133420f
TV
245
246 dss_sdi_pins: pinmux_dss_sdi_pins {
247 pinctrl-single,pins = <
248 0x0c0 (PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */
249 0x0c2 (PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */
250 0x0c4 (PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */
251 0x0c6 (PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */
252
253 0x0d8 (PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */
254 0x0da (PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */
255 >;
256 };
c1ad2206
SR
257
258 wl1251_pins: pinmux_wl1251 {
259 pinctrl-single,pins = <
260 0x0ce (PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */
261 0x05a (PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */
262 >;
263 };
782e25a4
SR
264
265 ssi_pins: pinmux_ssi {
266 pinctrl-single,pins = <
267 0x150 (PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
268 0x14e (PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
269 0x152 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
270 0x14c (PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
271 0x154 (PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
272 0x156 (PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
273 0x158 (PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
274 0x15a (PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
275 >;
276 };
76ad4ac1
SR
277
278 modem_pins: pinmux_modem {
279 pinctrl-single,pins = <
280 0x0ac (PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
281 0x0b0 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */
282 0x0b2 (PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
283 0x0b4 (PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
284 0x0b6 (PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
285 0x15e (PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
286 >;
287 };
ac888a88
SR
288};
289
a4d4b153 290&i2c1 {
ac888a88
SR
291 pinctrl-names = "default";
292 pinctrl-0 = <&i2c1_pins>;
293
a4d4b153
PM
294 clock-frequency = <2200000>;
295
296 twl: twl@48 {
297 reg = <0x48>;
298 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
299 interrupt-parent = <&intc>;
300 };
301};
302
303#include "twl4030.dtsi"
ac888a88 304#include "twl4030_omap3.dtsi"
a4d4b153 305
9cdbbadd
SR
306&vaux1 {
307 regulator-name = "V28";
308 regulator-min-microvolt = <2800000>;
309 regulator-max-microvolt = <2800000>;
310 regulator-always-on; /* due battery cover sensor */
311};
312
313&vaux2 {
314 regulator-name = "VCSI";
315 regulator-min-microvolt = <1800000>;
316 regulator-max-microvolt = <1800000>;
317};
318
319&vaux3 {
320 regulator-name = "VMMC2_30";
321 regulator-min-microvolt = <2800000>;
322 regulator-max-microvolt = <3000000>;
323};
324
325&vaux4 {
326 regulator-name = "VCAM_ANA_28";
327 regulator-min-microvolt = <2800000>;
328 regulator-max-microvolt = <2800000>;
329};
330
331&vmmc1 {
332 regulator-name = "VMMC1";
333 regulator-min-microvolt = <1850000>;
334 regulator-max-microvolt = <3150000>;
335};
336
337&vmmc2 {
338 regulator-name = "V28_A";
339 regulator-min-microvolt = <2800000>;
340 regulator-max-microvolt = <3000000>;
341 regulator-always-on; /* due VIO leak to AIC34 VDDs */
342};
343
344&vpll1 {
345 regulator-name = "VPLL";
346 regulator-min-microvolt = <1800000>;
347 regulator-max-microvolt = <1800000>;
348 regulator-always-on;
349};
350
351&vpll2 {
352 regulator-name = "VSDI_CSI";
353 regulator-min-microvolt = <1800000>;
354 regulator-max-microvolt = <1800000>;
355 regulator-always-on;
356};
357
358&vsim {
359 regulator-name = "VMMC2_IO_18";
360 regulator-min-microvolt = <1800000>;
361 regulator-max-microvolt = <1800000>;
362};
363
364&vio {
365 regulator-name = "VIO";
366 regulator-min-microvolt = <1800000>;
367 regulator-max-microvolt = <1800000>;
368
369};
370
371&vintana1 {
372 regulator-name = "VINTANA1";
373 /* fixed to 1500000 */
374 regulator-always-on;
375};
376
377&vintana2 {
378 regulator-name = "VINTANA2";
379 regulator-min-microvolt = <2750000>;
380 regulator-max-microvolt = <2750000>;
381 regulator-always-on;
382};
383
384&vintdig {
385 regulator-name = "VINTDIG";
386 /* fixed to 1500000 */
387 regulator-always-on;
388};
389
06ba7a61
SR
390&twl {
391 twl_audio: audio {
392 compatible = "ti,twl4030-audio";
393 ti,enable-vibra = <1>;
394 };
9188883f
TL
395
396 twl_power: power {
daebabd5 397 compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
9188883f
TL
398 ti,use_poweroff;
399 };
06ba7a61
SR
400};
401
85c215f3 402&twl_keypad {
3fdb7717
SR
403 linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q)
404 MATRIX_KEY(0x00, 0x01, KEY_O)
405 MATRIX_KEY(0x00, 0x02, KEY_P)
406 MATRIX_KEY(0x00, 0x03, KEY_COMMA)
407 MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE)
408 MATRIX_KEY(0x00, 0x06, KEY_A)
409 MATRIX_KEY(0x00, 0x07, KEY_S)
410
411 MATRIX_KEY(0x01, 0x00, KEY_W)
412 MATRIX_KEY(0x01, 0x01, KEY_D)
413 MATRIX_KEY(0x01, 0x02, KEY_F)
414 MATRIX_KEY(0x01, 0x03, KEY_G)
415 MATRIX_KEY(0x01, 0x04, KEY_H)
416 MATRIX_KEY(0x01, 0x05, KEY_J)
417 MATRIX_KEY(0x01, 0x06, KEY_K)
418 MATRIX_KEY(0x01, 0x07, KEY_L)
419
420 MATRIX_KEY(0x02, 0x00, KEY_E)
421 MATRIX_KEY(0x02, 0x01, KEY_DOT)
422 MATRIX_KEY(0x02, 0x02, KEY_UP)
423 MATRIX_KEY(0x02, 0x03, KEY_ENTER)
424 MATRIX_KEY(0x02, 0x05, KEY_Z)
425 MATRIX_KEY(0x02, 0x06, KEY_X)
426 MATRIX_KEY(0x02, 0x07, KEY_C)
427 MATRIX_KEY(0x02, 0x08, KEY_F9)
428
429 MATRIX_KEY(0x03, 0x00, KEY_R)
430 MATRIX_KEY(0x03, 0x01, KEY_V)
431 MATRIX_KEY(0x03, 0x02, KEY_B)
432 MATRIX_KEY(0x03, 0x03, KEY_N)
433 MATRIX_KEY(0x03, 0x04, KEY_M)
434 MATRIX_KEY(0x03, 0x05, KEY_SPACE)
435 MATRIX_KEY(0x03, 0x06, KEY_SPACE)
436 MATRIX_KEY(0x03, 0x07, KEY_LEFT)
437
438 MATRIX_KEY(0x04, 0x00, KEY_T)
439 MATRIX_KEY(0x04, 0x01, KEY_DOWN)
440 MATRIX_KEY(0x04, 0x02, KEY_RIGHT)
441 MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL)
442 MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT)
443 MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT)
444 MATRIX_KEY(0x04, 0x08, KEY_F10)
445
446 MATRIX_KEY(0x05, 0x00, KEY_Y)
447 MATRIX_KEY(0x05, 0x08, KEY_F11)
448
449 MATRIX_KEY(0x06, 0x00, KEY_U)
450
451 MATRIX_KEY(0x07, 0x00, KEY_I)
452 MATRIX_KEY(0x07, 0x01, KEY_F7)
453 MATRIX_KEY(0x07, 0x02, KEY_F8)
85c215f3
SR
454 >;
455};
456
a4d4b153
PM
457&twl_gpio {
458 ti,pullups = <0x0>;
459 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
460};
461
462&i2c2 {
ac888a88
SR
463 pinctrl-names = "default";
464 pinctrl-0 = <&i2c2_pins>;
465
48fc9864 466 clock-frequency = <100000>;
b2b9b258 467
14e3e295
SR
468 tlv320aic3x: tlv320aic3x@18 {
469 compatible = "ti,tlv320aic3x";
470 reg = <0x18>;
471 gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
472 ai3x-gpio-func = <
473 0 /* AIC3X_GPIO1_FUNC_DISABLED */
474 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
475 >;
476
477 AVDD-supply = <&vmmc2>;
478 DRVDD-supply = <&vmmc2>;
479 IOVDD-supply = <&vio>;
480 DVDD-supply = <&vio>;
481 };
482
483 tlv320aic3x_aux: tlv320aic3x@19 {
484 compatible = "ti,tlv320aic3x";
485 reg = <0x19>;
486 gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
487
488 AVDD-supply = <&vmmc2>;
489 DRVDD-supply = <&vmmc2>;
490 IOVDD-supply = <&vio>;
491 DVDD-supply = <&vio>;
492 };
493
12f2f873
SR
494 tsl2563: tsl2563@29 {
495 compatible = "amstaos,tsl2563";
496 reg = <0x29>;
497
498 amstaos,cover-comp-gain = <16>;
499 };
500
a0bf1f3e
SR
501 lp5523: lp5523@32 {
502 compatible = "national,lp5523";
503 reg = <0x32>;
504 clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
505 enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */
506
507 chan0 {
508 chan-name = "lp5523:kb1";
509 led-cur = /bits/ 8 <50>;
510 max-cur = /bits/ 8 <100>;
511 };
512
513 chan1 {
514 chan-name = "lp5523:kb2";
515 led-cur = /bits/ 8 <50>;
516 max-cur = /bits/ 8 <100>;
517 };
518
519 chan2 {
520 chan-name = "lp5523:kb3";
521 led-cur = /bits/ 8 <50>;
522 max-cur = /bits/ 8 <100>;
523 };
524
525 chan3 {
526 chan-name = "lp5523:kb4";
527 led-cur = /bits/ 8 <50>;
528 max-cur = /bits/ 8 <100>;
529 };
530
531 chan4 {
532 chan-name = "lp5523:b";
533 led-cur = /bits/ 8 <50>;
534 max-cur = /bits/ 8 <100>;
535 };
536
537 chan5 {
538 chan-name = "lp5523:g";
539 led-cur = /bits/ 8 <50>;
540 max-cur = /bits/ 8 <100>;
541 };
542
543 chan6 {
544 chan-name = "lp5523:r";
545 led-cur = /bits/ 8 <50>;
546 max-cur = /bits/ 8 <100>;
547 };
548
549 chan7 {
550 chan-name = "lp5523:kb5";
551 led-cur = /bits/ 8 <50>;
552 max-cur = /bits/ 8 <100>;
553 };
554
555 chan8 {
556 chan-name = "lp5523:kb6";
557 led-cur = /bits/ 8 <50>;
558 max-cur = /bits/ 8 <100>;
559 };
560 };
561
b2b9b258
SR
562 bq27200: bq27200@55 {
563 compatible = "ti,bq27200";
564 reg = <0x55>;
565 };
9e2367c8
SR
566
567 tpa6130a2: tpa6130a2@60 {
568 compatible = "ti,tpa6130a2";
569 reg = <0x60>;
570
571 Vdd-supply = <&vmmc2>;
572
573 power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
574 };
334a09c8 575
406c07e7
SR
576 si4713: si4713@63 {
577 compatible = "silabs,si4713";
578 reg = <0x63>;
579
580 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
581 reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
582 vio-supply = <&vio>;
583 vdd-supply = <&vaux1>;
584 };
585
334a09c8
SR
586 bq24150a: bq24150a@6b {
587 compatible = "ti,bq24150a";
588 reg = <0x6b>;
589
590 ti,current-limit = <100>;
591 ti,weak-battery-voltage = <3400>;
592 ti,battery-regulation-voltage = <4200>;
593 ti,charge-current = <650>;
594 ti,termination-current = <100>;
595 ti,resistor-sense = <68>;
596
597 ti,usb-charger-detection = <&isp1704>;
598 };
a4d4b153
PM
599};
600
601&i2c3 {
ac888a88
SR
602 pinctrl-names = "default";
603 pinctrl-0 = <&i2c3_pins>;
604
48fc9864 605 clock-frequency = <400000>;
a4d4b153
PM
606};
607
608&mmc1 {
f1751cff
SR
609 pinctrl-names = "default";
610 pinctrl-0 = <&mmc1_pins>;
611 vmmc-supply = <&vmmc1>;
612 bus-width = <4>;
613 cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
a4d4b153
PM
614};
615
edd5eb4e 616/* most boards use vaux3, only some old versions use vmmc2 instead */
a4d4b153 617&mmc2 {
edd5eb4e
TL
618 pinctrl-names = "default";
619 pinctrl-0 = <&mmc2_pins>;
620 vmmc-supply = <&vaux3>;
621 vmmc_aux-supply = <&vsim>;
622 bus-width = <8>;
623 non-removable;
a4d4b153
PM
624};
625
626&mmc3 {
627 status = "disabled";
628};
629
8699d2dd 630&gpmc {
271d4c6b
TL
631 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
632 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
9a894953
TL
633 pinctrl-names = "default";
634 pinctrl-0 = <&gpmc_pins>;
8699d2dd 635
e2c5eb78 636 /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
8699d2dd
SR
637 onenand@0,0 {
638 #address-cells = <1>;
639 #size-cells = <1>;
e2c5eb78 640 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
8699d2dd
SR
641
642 gpmc,sync-read;
643 gpmc,sync-write;
644 gpmc,burst-length = <16>;
645 gpmc,burst-read;
646 gpmc,burst-wrap;
647 gpmc,burst-write;
648 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
649 gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
650 gpmc,cs-on-ns = <0>;
651 gpmc,cs-rd-off-ns = <87>;
652 gpmc,cs-wr-off-ns = <87>;
653 gpmc,adv-on-ns = <0>;
654 gpmc,adv-rd-off-ns = <10>;
655 gpmc,adv-wr-off-ns = <10>;
656 gpmc,oe-on-ns = <15>;
657 gpmc,oe-off-ns = <87>;
658 gpmc,we-on-ns = <0>;
659 gpmc,we-off-ns = <87>;
660 gpmc,rd-cycle-ns = <112>;
661 gpmc,wr-cycle-ns = <112>;
662 gpmc,access-ns = <81>;
663 gpmc,page-burst-access-ns = <15>;
664 gpmc,bus-turnaround-ns = <0>;
665 gpmc,cycle2cycle-delay-ns = <0>;
666 gpmc,wait-monitoring-ns = <0>;
667 gpmc,clk-activation-ns = <5>;
668 gpmc,wr-data-mux-bus-ns = <30>;
669 gpmc,wr-access-ns = <81>;
670 gpmc,sync-clk-ps = <15000>;
671
672 /*
673 * MTD partition table corresponding to Nokia's
674 * Maemo 5 (Fremantle) release.
675 */
676 partition@0 {
677 label = "bootloader";
678 reg = <0x00000000 0x00020000>;
679 read-only;
680 };
681 partition@1 {
682 label = "config";
683 reg = <0x00020000 0x00060000>;
684 };
685 partition@2 {
686 label = "log";
687 reg = <0x00080000 0x00040000>;
688 };
689 partition@3 {
690 label = "kernel";
691 reg = <0x000c0000 0x00200000>;
692 };
693 partition@4 {
694 label = "initfs";
695 reg = <0x002c0000 0x00200000>;
696 };
697 partition@5 {
698 label = "rootfs";
699 reg = <0x004c0000 0x0fb40000>;
700 };
701 };
271d4c6b
TL
702
703 ethernet@gpmc {
704 compatible = "smsc,lan91c94";
b16ccfe0
TL
705
706 status = "disabled";
707
271d4c6b
TL
708 interrupt-parent = <&gpio2>;
709 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
710 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
711 bank-width = <2>;
712 pinctrl-names = "default";
713 pinctrl-0 = <&ethernet_pins>;
7d2911c4
TL
714 power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */
715 reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */
271d4c6b
TL
716 gpmc,device-width = <2>;
717 gpmc,sync-clk-ps = <0>;
718 gpmc,cs-on-ns = <0>;
719 gpmc,cs-rd-off-ns = <48>;
720 gpmc,cs-wr-off-ns = <24>;
721 gpmc,adv-on-ns = <0>;
722 gpmc,adv-rd-off-ns = <0>;
723 gpmc,adv-wr-off-ns = <0>;
724 gpmc,we-on-ns = <12>;
725 gpmc,we-off-ns = <18>;
726 gpmc,oe-on-ns = <12>;
727 gpmc,oe-off-ns = <48>;
728 gpmc,page-burst-access-ns = <0>;
729 gpmc,access-ns = <42>;
730 gpmc,rd-cycle-ns = <180>;
731 gpmc,wr-cycle-ns = <180>;
732 gpmc,bus-turnaround-ns = <0>;
733 gpmc,cycle2cycle-delay-ns = <0>;
734 gpmc,wait-monitoring-ns = <0>;
735 gpmc,clk-activation-ns = <0>;
736 gpmc,wr-access-ns = <0>;
737 gpmc,wr-data-mux-bus-ns = <12>;
738 };
8699d2dd
SR
739};
740
a4d4b153
PM
741&mcspi1 {
742 /*
743 * For some reason, touchscreen is necessary for screen to work at
744 * all on real hw. It works well without it on emulator.
745 *
746 * Also... order in the device tree actually matters here.
747 */
748 tsc2005@0 {
50525891 749 compatible = "ti,tsc2005";
a4d4b153
PM
750 spi-max-frequency = <6000000>;
751 reg = <0>;
50525891
SR
752
753 vio-supply = <&vio>;
754
755 reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
756 interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */
757
758 touchscreen-fuzz-x = <4>;
759 touchscreen-fuzz-y = <7>;
760 touchscreen-fuzz-pressure = <2>;
761 touchscreen-max-x = <4096>;
762 touchscreen-max-y = <4096>;
763 touchscreen-max-pressure = <2048>;
764
765 ti,x-plate-ohms = <280>;
766 ti,esd-recovery-timeout-ms = <8000>;
a4d4b153 767 };
1133420f
TV
768
769 acx565akm@2 {
770 compatible = "sony,acx565akm";
a4d4b153
PM
771 spi-max-frequency = <6000000>;
772 reg = <2>;
d1e6f516
SR
773
774 pinctrl-names = "default";
1133420f
TV
775 pinctrl-0 = <&acx565akm_pins>;
776
777 label = "lcd";
778 reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */
779
780 port {
781 lcd_in: endpoint {
782 remote-endpoint = <&sdi_out>;
783 };
784 };
a4d4b153
PM
785 };
786};
787
c1ad2206
SR
788&mcspi4 {
789 pinctrl-names = "default";
790 pinctrl-0 = <&mcspi4_pins>;
791
792 wl1251@0 {
793 pinctrl-names = "default";
794 pinctrl-0 = <&wl1251_pins>;
795
796 vio-supply = <&vio>;
797
798 compatible = "ti,wl1251";
799 reg = <0>;
800 spi-max-frequency = <48000000>;
801
802 spi-cpol;
803 spi-cpha;
804
805 ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
806
807 interrupt-parent = <&gpio2>;
808 interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */
809 };
810};
811
a4d4b153
PM
812&usb_otg_hs {
813 interface-type = <0>;
814 usb-phy = <&usb2_phy>;
d2afcf09
RQ
815 phys = <&usb2_phy>;
816 phy-names = "usb2-phy";
a4d4b153
PM
817 mode = <2>;
818 power = <50>;
819};
7a89eecf
SR
820
821&uart1 {
822 status = "disabled";
823};
824
825&uart2 {
31f0820a 826 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
7a89eecf
SR
827 pinctrl-names = "default";
828 pinctrl-0 = <&uart2_pins>;
829};
830
831&uart3 {
31f0820a 832 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
7a89eecf
SR
833 pinctrl-names = "default";
834 pinctrl-0 = <&uart3_pins>;
835};
1133420f
TV
836
837&dss {
838 status = "ok";
839
840 pinctrl-names = "default";
841 pinctrl-0 = <&dss_sdi_pins>;
842
843 vdds_sdi-supply = <&vaux1>;
844
845 ports {
846 #address-cells = <1>;
847 #size-cells = <0>;
848
849 port@1 {
850 reg = <1>;
851
852 sdi_out: endpoint {
853 remote-endpoint = <&lcd_in>;
854 datapairs = <2>;
855 };
856 };
857 };
858};
859
860&venc {
861 status = "ok";
862
863 vdda-supply = <&vdac>;
864
865 port {
866 venc_out: endpoint {
867 remote-endpoint = <&tv_connector_in>;
868 ti,channels = <1>;
869 };
870 };
871};
f7d0f2a0
SR
872
873&mcbsp2 {
874 status = "ok";
875};
782e25a4
SR
876
877&ssi_port1 {
878 pinctrl-names = "default";
879 pinctrl-0 = <&ssi_pins>;
880
881 ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
76ad4ac1
SR
882
883 modem: hsi-client {
884 compatible = "nokia,n900-modem";
885
886 pinctrl-names = "default";
887 pinctrl-0 = <&modem_pins>;
888
889 hsi-channel-ids = <0>, <1>, <2>, <3>;
890 hsi-channel-names = "mcsaab-control",
891 "speech-control",
892 "speech-data",
893 "mcsaab-data";
894 hsi-speed-kbps = <55000>;
895 hsi-mode = "frame";
896 hsi-flow = "synchronized";
897 hsi-arb-mode = "round-robin";
898
899 interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
900
901 gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */
902 <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */
903 <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
904 <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
905 <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
906 gpio-names = "cmt_apeslpx",
907 "cmt_rst_rq",
908 "cmt_en",
909 "cmt_rst",
910 "cmt_bsi";
911 };
782e25a4
SR
912};
913
914&ssi_port2 {
915 status = "disabled";
76ad4ac1 916};