]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - arch/arm/boot/dts/omap3-n900.dts
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
UBUNTU: Ubuntu-5.3.0-29.31
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / omap3-n900.dts
CommitLineData
3a63cbb8 1// SPDX-License-Identifier: GPL-2.0-or-later
a4d4b153
PM		 2/*
3 * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
c3580bc1 4 * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
a4d4b153
PM		 5 */
6
7/dts-v1/;
8
69540a7c 9#include "omap34xx.dtsi"
3fdb7717 10#include <dt-bindings/input/input.h>
a4d4b153 11
69540a7c
PR		 12/*
13 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
14 * for omap AES HW crypto support. When linux kernel try to access memory of AES
15 * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
16 * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
17 * crash anymore) omap AES support will be disabled for all Nokia N900 devices.
18 * There is "unofficial" version of bootloader which enables AES in L3 firewall
19 * but it is not widely used and to prevent kernel crash rather AES is disabled.
20 * There is also no runtime detection code if AES is disabled in L3 firewall...
21 */
22&aes {
23 status = "disabled";
24};
25
a4d4b153
PM		 26/ {
27 model = "Nokia N900";
c3580bc1 28 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
a4d4b153 29
1861cda0
ID		 30 aliases {
31 i2c0;
32 i2c1 = &i2c1;
33 i2c2 = &i2c2;
34 i2c3 = &i2c3;
cbe92b02
ID		 35 display0 = &lcd;
36 display1 = &tv;
1861cda0
ID		 37 };
38
a4d4b153
PM		 39 cpus {
40 cpu@0 {
41 cpu0-supply = <&vcc>;
42 };
43 };
44
c1be2032
TL		 45 leds {
46 compatible = "gpio-leds";
47 heartbeat {
48 label = "debug::sleep";
f585a15c 49 gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */
c1be2032
TL		 50 linux,default-trigger = "default-on";
51 pinctrl-names = "default";
52 pinctrl-0 = <&debug_leds>;
53 };
54 };
55
81777ff9 56 memory@80000000 {
a4d4b153
PM		 57 device_type = "memory";
58 reg = <0x80000000 0x10000000>; /* 256 MB */
59 };
60
3931c839
SR		 61 gpio_keys {
62 compatible = "gpio-keys";
63
64 camera_lens_cover {
65 label = "Camera Lens Cover";
66 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */
97d7f2ff
PR		 67 linux,input-type = <EV_SW>;
68 linux,code = <SW_CAMERA_LENS_COVER>;
05cf1e03 69 linux,can-disable;
3931c839
SR		 70 };
71
72 camera_focus {
73 label = "Camera Focus";
74 gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */
97d7f2ff 75 linux,code = <KEY_CAMERA_FOCUS>;
05cf1e03 76 linux,can-disable;
3931c839
SR		 77 };
78
79 camera_capture {
80 label = "Camera Capture";
81 gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */
97d7f2ff 82 linux,code = <KEY_CAMERA>;
05cf1e03 83 linux,can-disable;
3931c839
SR		 84 };
85
86 lock_button {
87 label = "Lock Button";
88 gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */
97d7f2ff 89 linux,code = <KEY_SCREENLOCK>;
05cf1e03 90 linux,can-disable;
3931c839
SR		 91 };
92
93 keypad_slide {
94 label = "Keypad Slide";
95 gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */
97d7f2ff
PR		 96 linux,input-type = <EV_SW>;
97 linux,code = <SW_KEYPAD_SLIDE>;
05cf1e03 98 linux,can-disable;
3931c839
SR		 99 };
100
101 proximity_sensor {
102 label = "Proximity Sensor";
103 gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */
97d7f2ff
PR		 104 linux,input-type = <EV_SW>;
105 linux,code = <SW_FRONT_PROXIMITY>;
05cf1e03 106 linux,can-disable;
3931c839
SR		 107 };
108 };
109
b950762c
PR		 110 isp1707: isp1707 {
111 compatible = "nxp,isp1707";
e17337a2
SR		 112 nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
113 usb-phy = <&usb2_phy>;
114 };
1133420f
TV		 115
116 tv: connector {
32797b3e 117 compatible = "composite-video-connector";
1133420f
TV		 118 label = "tv";
119
120 port {
121 tv_connector_in: endpoint {
122 remote-endpoint = <&venc_out>;
123 };
124 };
125 };
f7d0f2a0
SR		 126
127 sound: n900-audio {
128 compatible = "nokia,n900-audio";
129
130 nokia,cpu-dai = <&mcbsp2>;
131 nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>;
132 nokia,headphone-amplifier = <&tpa6130a2>;
133
134 tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */
135 jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */
136 eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
137 speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
138 };
28398c69
SR		 139
140 battery: n900-battery {
141 compatible = "nokia,n900-battery";
142 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
143 io-channel-names = "temp", "bsi", "vbat";
144 };
e7c86821 145
cc9a4bda 146 pwm9: dmtimer-pwm {
e7c86821
ID		 147 compatible = "ti,omap-dmtimer-pwm";
148 #pwm-cells = <3>;
149 ti,timers = <&timer9>;
150 ti,clock-source = <0x00>; /* timer_sys_ck */
151 };
152
153 ir: n900-ir {
154 compatible = "nokia,n900-ir";
155 pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
156 };
3d5c6568
SR		 157
158 /* controlled (enabled/disabled) directly by bcm2048 and wl1251 */
159 vctcxo: vctcxo {
160 compatible = "fixed-clock";
161 #clock-cells = <0>;
162 clock-frequency = <38400000>;
163 };
a4d4b153
PM		 164};
165
d510d12f
PM		 166&isp {
167 vdds_csib-supply = <&vaux2>;
168
169 pinctrl-names = "default";
170 pinctrl-0 = <&camera_pins>;
171
172 ports {
173 port@1 {
174 reg = <1>;
175
176 csi_isp: endpoint {
177 remote-endpoint = <&csi_cam1>;
178 bus-type = <3>; /* CCP2 */
179 clock-lanes = <1>;
180 data-lanes = <0>;
181 lane-polarity = <0 0>;
d510d12f
PM		 182 /* Select strobe = <1> for back camera, <0> for front camera */
183 strobe = <1>;
d510d12f
PM		 184 };
185 };
186 };
187};
188
ac888a88
SR		 189&omap3_pmx_core {
190 pinctrl-names = "default";
191
7a89eecf
SR		 192 uart2_pins: pinmux_uart2_pins {
193 pinctrl-single,pins = <
3d5c6568
SR		 194 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
195 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */
675e457c 196 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
3d5c6568 197 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
7a89eecf
SR		 198 >;
199 };
200
201 uart3_pins: pinmux_uart3_pins {
202 pinctrl-single,pins = <
675e457c
JMC		 203 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */
204 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */
7a89eecf
SR		 205 >;
206 };
207
271d4c6b
TL		 208 ethernet_pins: pinmux_ethernet_pins {
209 pinctrl-single,pins = <
210 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
211 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
212 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
213 >;
214 };
215
9a894953
TL		 216 gpmc_pins: pinmux_gpmc_pins {
217 pinctrl-single,pins = <
218
219 /* address lines */
220 OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
221 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
222 OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
223
224 /* data lines, gpmc_d0..d7 not muxable according to TRM */
225 OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
226 OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
227 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
228 OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
229 OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
230 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
231 OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
232 OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
233
234 /*
235 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
236 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
237 */
238 OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
239 OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
240 >;
241 };
242
ac888a88
SR		 243 i2c1_pins: pinmux_i2c1_pins {
244 pinctrl-single,pins = <
675e457c
JMC		 245 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
246 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
ac888a88
SR		 247 >;
248 };
249
250 i2c2_pins: pinmux_i2c2_pins {
251 pinctrl-single,pins = <
675e457c
JMC		 252 OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
253 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
ac888a88
SR		 254 >;
255 };
256
257 i2c3_pins: pinmux_i2c3_pins {
258 pinctrl-single,pins = <
675e457c
JMC		 259 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
260 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
ac888a88
SR		 261 >;
262 };
f1751cff 263
c1be2032
TL		 264 debug_leds: pinmux_debug_led_pins {
265 pinctrl-single,pins = <
266 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */
267 >;
268 };
269
c1ad2206
SR		 270 mcspi4_pins: pinmux_mcspi4_pins {
271 pinctrl-single,pins = <
675e457c
JMC		 272 OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
273 OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
274 OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
275 OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
c1ad2206
SR		 276 >;
277 };
278
f1751cff
SR		 279 mmc1_pins: pinmux_mmc1_pins {
280 pinctrl-single,pins = <
675e457c
JMC		 281 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
282 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */
283 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */
284 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */
285 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */
286 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */
f1751cff
SR		 287 >;
288 };
d1e6f516 289
edd5eb4e
TL		 290 mmc2_pins: pinmux_mmc2_pins {
291 pinctrl-single,pins = <
675e457c
JMC		 292 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
293 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
294 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
295 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
296 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
297 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
298 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
299 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
300 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
301 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
edd5eb4e
TL		 302 >;
303 };
304
1133420f 305 acx565akm_pins: pinmux_acx565akm_pins {
d1e6f516 306 pinctrl-single,pins = <
675e457c 307 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
d1e6f516
SR		 308 >;
309 };
1133420f
TV		 310
311 dss_sdi_pins: pinmux_dss_sdi_pins {
312 pinctrl-single,pins = <
675e457c
JMC		 313 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */
314 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */
315 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */
316 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */
1133420f 317
675e457c
JMC		 318 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */
319 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */
1133420f
TV		 320 >;
321 };
c1ad2206
SR		 322
323 wl1251_pins: pinmux_wl1251 {
324 pinctrl-single,pins = <
675e457c
JMC		 325 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */
326 OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */
c1ad2206
SR		 327 >;
328 };
782e25a4
SR		 329
330 ssi_pins: pinmux_ssi {
331 pinctrl-single,pins = <
675e457c
JMC		 332 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
333 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
e0e80d43 334 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
675e457c
JMC		 335 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
336 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
337 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
338 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
339 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
782e25a4
SR		 340 >;
341 };
76ad4ac1
SR		 342
343 modem_pins: pinmux_modem {
344 pinctrl-single,pins = <
675e457c 345 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
e0e80d43 346 OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */
675e457c
JMC		 347 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
348 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
349 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
350 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
76ad4ac1
SR		 351 >;
352 };
d510d12f
PM		 353
354 camera_pins: pinmux_camera {
355 pinctrl-single,pins = <
356 OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */
357 OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */
358 OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */
359 OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */
360 OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */
361 OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */
362 OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */
363 OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */
364 OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */
365 OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */
366 OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */
367 >;
368 };
ac888a88
SR		 369};
370
a4d4b153 371&i2c1 {
ac888a88
SR		 372 pinctrl-names = "default";
373 pinctrl-0 = <&i2c1_pins>;
374
a4d4b153
PM		 375 clock-frequency = <2200000>;
376
377 twl: twl@48 {
378 reg = <0x48>;
379 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
380 interrupt-parent = <&intc>;
381 };
382};
383
384#include "twl4030.dtsi"
ac888a88 385#include "twl4030_omap3.dtsi"
a4d4b153 386
9cdbbadd
SR		 387&vaux1 {
388 regulator-name = "V28";
389 regulator-min-microvolt = <2800000>;
390 regulator-max-microvolt = <2800000>;
0698178c 391 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
14fd7330 392 regulator-always-on; /* due to battery cover sensor */
9cdbbadd
SR		 393};
394
395&vaux2 {
396 regulator-name = "VCSI";
397 regulator-min-microvolt = <1800000>;
398 regulator-max-microvolt = <1800000>;
0698178c 399 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 400};
401
402&vaux3 {
403 regulator-name = "VMMC2_30";
404 regulator-min-microvolt = <2800000>;
405 regulator-max-microvolt = <3000000>;
0698178c 406 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 407};
408
409&vaux4 {
410 regulator-name = "VCAM_ANA_28";
411 regulator-min-microvolt = <2800000>;
412 regulator-max-microvolt = <2800000>;
0698178c 413 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 414};
415
416&vmmc1 {
417 regulator-name = "VMMC1";
418 regulator-min-microvolt = <1850000>;
419 regulator-max-microvolt = <3150000>;
0698178c 420 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 421};
422
423&vmmc2 {
424 regulator-name = "V28_A";
425 regulator-min-microvolt = <2800000>;
426 regulator-max-microvolt = <3000000>;
0698178c 427 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 428 regulator-always-on; /* due VIO leak to AIC34 VDDs */
429};
430
431&vpll1 {
432 regulator-name = "VPLL";
433 regulator-min-microvolt = <1800000>;
434 regulator-max-microvolt = <1800000>;
0698178c 435 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 436 regulator-always-on;
437};
438
439&vpll2 {
440 regulator-name = "VSDI_CSI";
441 regulator-min-microvolt = <1800000>;
442 regulator-max-microvolt = <1800000>;
0698178c 443 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 444 regulator-always-on;
445};
446
447&vsim {
448 regulator-name = "VMMC2_IO_18";
449 regulator-min-microvolt = <1800000>;
450 regulator-max-microvolt = <1800000>;
0698178c 451 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
9cdbbadd
SR		 452};
453
454&vio {
455 regulator-name = "VIO";
456 regulator-min-microvolt = <1800000>;
457 regulator-max-microvolt = <1800000>;
9cdbbadd
SR		 458};
459
460&vintana1 {
461 regulator-name = "VINTANA1";
462 /* fixed to 1500000 */
463 regulator-always-on;
464};
465
466&vintana2 {
467 regulator-name = "VINTANA2";
468 regulator-min-microvolt = <2750000>;
469 regulator-max-microvolt = <2750000>;
470 regulator-always-on;
471};
472
473&vintdig {
474 regulator-name = "VINTDIG";
475 /* fixed to 1500000 */
476 regulator-always-on;
477};
478
06ba7a61
SR		 479&twl {
480 twl_audio: audio {
481 compatible = "ti,twl4030-audio";
482 ti,enable-vibra = <1>;
483 };
9188883f
TL		 484
485 twl_power: power {
daebabd5 486 compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
9188883f
TL		 487 ti,use_poweroff;
488 };
06ba7a61
SR		 489};
490
85c215f3 491&twl_keypad {
3fdb7717
SR		 492 linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q)
493 MATRIX_KEY(0x00, 0x01, KEY_O)
494 MATRIX_KEY(0x00, 0x02, KEY_P)
495 MATRIX_KEY(0x00, 0x03, KEY_COMMA)
496 MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE)
497 MATRIX_KEY(0x00, 0x06, KEY_A)
498 MATRIX_KEY(0x00, 0x07, KEY_S)
499
500 MATRIX_KEY(0x01, 0x00, KEY_W)
501 MATRIX_KEY(0x01, 0x01, KEY_D)
502 MATRIX_KEY(0x01, 0x02, KEY_F)
503 MATRIX_KEY(0x01, 0x03, KEY_G)
504 MATRIX_KEY(0x01, 0x04, KEY_H)
505 MATRIX_KEY(0x01, 0x05, KEY_J)
506 MATRIX_KEY(0x01, 0x06, KEY_K)
507 MATRIX_KEY(0x01, 0x07, KEY_L)
508
509 MATRIX_KEY(0x02, 0x00, KEY_E)
510 MATRIX_KEY(0x02, 0x01, KEY_DOT)
511 MATRIX_KEY(0x02, 0x02, KEY_UP)
512 MATRIX_KEY(0x02, 0x03, KEY_ENTER)
513 MATRIX_KEY(0x02, 0x05, KEY_Z)
514 MATRIX_KEY(0x02, 0x06, KEY_X)
515 MATRIX_KEY(0x02, 0x07, KEY_C)
516 MATRIX_KEY(0x02, 0x08, KEY_F9)
517
518 MATRIX_KEY(0x03, 0x00, KEY_R)
519 MATRIX_KEY(0x03, 0x01, KEY_V)
520 MATRIX_KEY(0x03, 0x02, KEY_B)
521 MATRIX_KEY(0x03, 0x03, KEY_N)
522 MATRIX_KEY(0x03, 0x04, KEY_M)
523 MATRIX_KEY(0x03, 0x05, KEY_SPACE)
524 MATRIX_KEY(0x03, 0x06, KEY_SPACE)
525 MATRIX_KEY(0x03, 0x07, KEY_LEFT)
526
527 MATRIX_KEY(0x04, 0x00, KEY_T)
528 MATRIX_KEY(0x04, 0x01, KEY_DOWN)
529 MATRIX_KEY(0x04, 0x02, KEY_RIGHT)
530 MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL)
531 MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT)
532 MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT)
533 MATRIX_KEY(0x04, 0x08, KEY_F10)
534
535 MATRIX_KEY(0x05, 0x00, KEY_Y)
536 MATRIX_KEY(0x05, 0x08, KEY_F11)
537
538 MATRIX_KEY(0x06, 0x00, KEY_U)
539
540 MATRIX_KEY(0x07, 0x00, KEY_I)
541 MATRIX_KEY(0x07, 0x01, KEY_F7)
542 MATRIX_KEY(0x07, 0x02, KEY_F8)
85c215f3
SR		 543 >;
544};
545
a4d4b153
PM		 546&twl_gpio {
547 ti,pullups = <0x0>;
548 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
549};
550
551&i2c2 {
ac888a88
SR		 552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c2_pins>;
554
48fc9864 555 clock-frequency = <100000>;
b2b9b258 556
14e3e295
SR		 557 tlv320aic3x: tlv320aic3x@18 {
558 compatible = "ti,tlv320aic3x";
559 reg = <0x18>;
7be4b5dc 560 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */
14e3e295
SR		 561 ai3x-gpio-func = <
562 0 /* AIC3X_GPIO1_FUNC_DISABLED */
563 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
564 >;
565
566 AVDD-supply = <&vmmc2>;
567 DRVDD-supply = <&vmmc2>;
568 IOVDD-supply = <&vio>;
569 DVDD-supply = <&vio>;
1819e303
PM		 570
571 ai3x-micbias-vg = <1>;
14e3e295
SR		 572 };
573
574 tlv320aic3x_aux: tlv320aic3x@19 {
575 compatible = "ti,tlv320aic3x";
576 reg = <0x19>;
7be4b5dc 577 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */
14e3e295
SR		 578
579 AVDD-supply = <&vmmc2>;
580 DRVDD-supply = <&vmmc2>;
581 IOVDD-supply = <&vio>;
582 DVDD-supply = <&vio>;
1819e303
PM		 583
584 ai3x-micbias-vg = <2>;
14e3e295
SR		 585 };
586
12f2f873
SR		 587 tsl2563: tsl2563@29 {
588 compatible = "amstaos,tsl2563";
589 reg = <0x29>;
590
591 amstaos,cover-comp-gain = <16>;
592 };
593
14628e44
PR		 594 adp1653: led-controller@30 {
595 compatible = "adi,adp1653";
596 reg = <0x30>;
597 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */
598
599 flash {
600 flash-timeout-us = <500000>;
601 flash-max-microamp = <320000>;
602 led-max-microamp = <50000>;
603 };
604 indicator {
605 led-max-microamp = <17500>;
606 };
607 };
608
a0bf1f3e
SR		 609 lp5523: lp5523@32 {
610 compatible = "national,lp5523";
611 reg = <0x32>;
612 clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
613 enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */
614
615 chan0 {
616 chan-name = "lp5523:kb1";
617 led-cur = /bits/ 8 <50>;
618 max-cur = /bits/ 8 <100>;
619 };
620
621 chan1 {
622 chan-name = "lp5523:kb2";
623 led-cur = /bits/ 8 <50>;
624 max-cur = /bits/ 8 <100>;
625 };
626
627 chan2 {
628 chan-name = "lp5523:kb3";
629 led-cur = /bits/ 8 <50>;
630 max-cur = /bits/ 8 <100>;
631 };
632
633 chan3 {
634 chan-name = "lp5523:kb4";
635 led-cur = /bits/ 8 <50>;
636 max-cur = /bits/ 8 <100>;
637 };
638
639 chan4 {
640 chan-name = "lp5523:b";
641 led-cur = /bits/ 8 <50>;
642 max-cur = /bits/ 8 <100>;
643 };
644
645 chan5 {
646 chan-name = "lp5523:g";
647 led-cur = /bits/ 8 <50>;
648 max-cur = /bits/ 8 <100>;
649 };
650
651 chan6 {
652 chan-name = "lp5523:r";
653 led-cur = /bits/ 8 <50>;
654 max-cur = /bits/ 8 <100>;
655 };
656
657 chan7 {
658 chan-name = "lp5523:kb5";
659 led-cur = /bits/ 8 <50>;
660 max-cur = /bits/ 8 <100>;
661 };
662
663 chan8 {
664 chan-name = "lp5523:kb6";
665 led-cur = /bits/ 8 <50>;
666 max-cur = /bits/ 8 <100>;
667 };
668 };
669
b2b9b258
SR		 670 bq27200: bq27200@55 {
671 compatible = "ti,bq27200";
672 reg = <0x55>;
3c6b4f46 673 power-supplies = <&bq24150a>;
b2b9b258 674 };
9e2367c8 675
f585a15c 676 /* Stereo headphone amplifier */
9e2367c8
SR		 677 tpa6130a2: tpa6130a2@60 {
678 compatible = "ti,tpa6130a2";
679 reg = <0x60>;
680
681 Vdd-supply = <&vmmc2>;
682
683 power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
684 };
334a09c8 685
406c07e7
SR		 686 si4713: si4713@63 {
687 compatible = "silabs,si4713";
688 reg = <0x63>;
689
690 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
691 reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
692 vio-supply = <&vio>;
693 vdd-supply = <&vaux1>;
694 };
695
334a09c8
SR		 696 bq24150a: bq24150a@6b {
697 compatible = "ti,bq24150a";
698 reg = <0x6b>;
699
700 ti,current-limit = <100>;
701 ti,weak-battery-voltage = <3400>;
702 ti,battery-regulation-voltage = <4200>;
703 ti,charge-current = <650>;
704 ti,termination-current = <100>;
705 ti,resistor-sense = <68>;
706
b950762c 707 ti,usb-charger-detection = <&isp1707>;
334a09c8 708 };
a4d4b153
PM		 709};
710
711&i2c3 {
ac888a88
SR		 712 pinctrl-names = "default";
713 pinctrl-0 = <&i2c3_pins>;
714
48fc9864 715 clock-frequency = <400000>;
1ac4e6fe
SR		 716
717 lis302dl: lis3lv02d@1d {
718 compatible = "st,lis3lv02d";
719 reg = <0x1d>;
720
721 Vdd-supply = <&vaux1>;
722 Vdd_IO-supply = <&vio>;
723
724 interrupt-parent = <&gpio6>;
725 interrupts = <21 20>; /* 181 and 180 */
726
727 /* click flags */
728 st,click-single-x;
729 st,click-single-y;
730 st,click-single-z;
731
732 /* Limits are 0.5g * value */
733 st,click-threshold-x = <8>;
734 st,click-threshold-y = <8>;
735 st,click-threshold-z = <10>;
736
737 /* Click must be longer than time limit */
738 st,click-time-limit = <9>;
739
740 /* Kind of debounce filter */
741 st,click-latency = <50>;
742
743 /* Interrupt line 2 for click detection */
744 st,irq2-click;
745
746 st,wakeup-x-hi;
747 st,wakeup-y-hi;
748 st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
749
750 st,wakeup2-z-hi;
751 st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */
752
753 st,hipass1-disable;
754 st,hipass2-disable;
755
756 st,axis-x = <1>; /* LIS3_DEV_X */
757 st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
758 st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
759
760 st,min-limit-x = <(-32)>;
761 st,min-limit-y = <3>;
762 st,min-limit-z = <3>;
763
764 st,max-limit-x = <(-3)>;
765 st,max-limit-y = <32>;
766 st,max-limit-z = <32>;
767 };
d510d12f
PM		 768
769 cam1: camera@3e {
770 compatible = "toshiba,et8ek8";
771 reg = <0x3e>;
772
773 vana-supply = <&vaux4>;
774
775 clocks = <&isp 0>;
776 clock-names = "extclk";
777 clock-frequency = <9600000>;
778
779 reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
780
4884c506
PM		 781 lens-focus = <&ad5820>;
782
d510d12f
PM		 783 port {
784 csi_cam1: endpoint {
785 bus-type = <3>; /* CCP2 */
786 strobe = <1>;
787 clock-inv = <0>;
788 crc = <1>;
789
790 remote-endpoint = <&csi_isp>;
791 };
792 };
793 };
794
795 /* D/A converter for auto-focus */
8dccafaa 796 ad5820: dac@c {
d510d12f
PM		 797 compatible = "adi,ad5820";
798 reg = <0x0c>;
799
800 VANA-supply = <&vaux4>;
801
802 #io-channel-cells = <0>;
803 };
a4d4b153
PM		 804};
805
806&mmc1 {
f1751cff
SR		 807 pinctrl-names = "default";
808 pinctrl-0 = <&mmc1_pins>;
809 vmmc-supply = <&vmmc1>;
810 bus-width = <4>;
d510d12f
PM		 811 /* For debugging, it is often good idea to remove this GPIO.
812 It means you can remove back cover (to reboot by removing
813 battery) and still use the MMC card. */
ac9c908e 814 cd-gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */
a4d4b153
PM		 815};
816
edd5eb4e 817/* most boards use vaux3, only some old versions use vmmc2 instead */
a4d4b153 818&mmc2 {
edd5eb4e
TL		 819 pinctrl-names = "default";
820 pinctrl-0 = <&mmc2_pins>;
821 vmmc-supply = <&vaux3>;
45ea75eb 822 vqmmc-supply = <&vsim>;
edd5eb4e
TL		 823 bus-width = <8>;
824 non-removable;
4cf48f1d
PR		 825 no-sdio;
826 no-sd;
a4d4b153
PM		 827};
828
829&mmc3 {
830 status = "disabled";
831};
832
8699d2dd 833&gpmc {
271d4c6b
TL		 834 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
835 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
9a894953
TL		 836 pinctrl-names = "default";
837 pinctrl-0 = <&gpmc_pins>;
8699d2dd 838
e2c5eb78 839 /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
8699d2dd
SR		 840 onenand@0,0 {
841 #address-cells = <1>;
842 #size-cells = <1>;
396744b7 843 compatible = "ti,omap2-onenand";
e2c5eb78 844 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
8699d2dd
SR		 845
846 gpmc,sync-read;
847 gpmc,sync-write;
848 gpmc,burst-length = <16>;
849 gpmc,burst-read;
850 gpmc,burst-wrap;
851 gpmc,burst-write;
852 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
853 gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
854 gpmc,cs-on-ns = <0>;
855 gpmc,cs-rd-off-ns = <87>;
856 gpmc,cs-wr-off-ns = <87>;
857 gpmc,adv-on-ns = <0>;
858 gpmc,adv-rd-off-ns = <10>;
859 gpmc,adv-wr-off-ns = <10>;
860 gpmc,oe-on-ns = <15>;
861 gpmc,oe-off-ns = <87>;
862 gpmc,we-on-ns = <0>;
863 gpmc,we-off-ns = <87>;
864 gpmc,rd-cycle-ns = <112>;
865 gpmc,wr-cycle-ns = <112>;
866 gpmc,access-ns = <81>;
867 gpmc,page-burst-access-ns = <15>;
868 gpmc,bus-turnaround-ns = <0>;
869 gpmc,cycle2cycle-delay-ns = <0>;
870 gpmc,wait-monitoring-ns = <0>;
871 gpmc,clk-activation-ns = <5>;
872 gpmc,wr-data-mux-bus-ns = <30>;
873 gpmc,wr-access-ns = <81>;
874 gpmc,sync-clk-ps = <15000>;
875
876 /*
877 * MTD partition table corresponding to Nokia's
878 * Maemo 5 (Fremantle) release.
879 */
880 partition@0 {
881 label = "bootloader";
882 reg = <0x00000000 0x00020000>;
883 read-only;
884 };
885 partition@1 {
886 label = "config";
887 reg = <0x00020000 0x00060000>;
888 };
889 partition@2 {
890 label = "log";
891 reg = <0x00080000 0x00040000>;
892 };
893 partition@3 {
894 label = "kernel";
895 reg = <0x000c0000 0x00200000>;
896 };
897 partition@4 {
898 label = "initfs";
899 reg = <0x002c0000 0x00200000>;
900 };
901 partition@5 {
902 label = "rootfs";
903 reg = <0x004c0000 0x0fb40000>;
904 };
905 };
271d4c6b 906
7ac72746 907 /* Ethernet is on some early development boards and qemu */
271d4c6b
TL		 908 ethernet@gpmc {
909 compatible = "smsc,lan91c94";
910 interrupt-parent = <&gpio2>;
911 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
cb9071d4 912 reg = <1 0 0xf>; /* 16 byte IO range */
271d4c6b
TL		 913 bank-width = <2>;
914 pinctrl-names = "default";
915 pinctrl-0 = <&ethernet_pins>;
7d2911c4
TL		 916 power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */
917 reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */
271d4c6b
TL		 918 gpmc,device-width = <2>;
919 gpmc,sync-clk-ps = <0>;
920 gpmc,cs-on-ns = <0>;
921 gpmc,cs-rd-off-ns = <48>;
922 gpmc,cs-wr-off-ns = <24>;
923 gpmc,adv-on-ns = <0>;
924 gpmc,adv-rd-off-ns = <0>;
925 gpmc,adv-wr-off-ns = <0>;
926 gpmc,we-on-ns = <12>;
927 gpmc,we-off-ns = <18>;
928 gpmc,oe-on-ns = <12>;
929 gpmc,oe-off-ns = <48>;
930 gpmc,page-burst-access-ns = <0>;
931 gpmc,access-ns = <42>;
932 gpmc,rd-cycle-ns = <180>;
933 gpmc,wr-cycle-ns = <180>;
934 gpmc,bus-turnaround-ns = <0>;
935 gpmc,cycle2cycle-delay-ns = <0>;
936 gpmc,wait-monitoring-ns = <0>;
937 gpmc,clk-activation-ns = <0>;
938 gpmc,wr-access-ns = <0>;
939 gpmc,wr-data-mux-bus-ns = <12>;
940 };
8699d2dd
SR		 941};
942
a4d4b153
PM		 943&mcspi1 {
944 /*
945 * For some reason, touchscreen is necessary for screen to work at
946 * all on real hw. It works well without it on emulator.
947 *
948 * Also... order in the device tree actually matters here.
949 */
950 tsc2005@0 {
50525891 951 compatible = "ti,tsc2005";
a4d4b153
PM		 952 spi-max-frequency = <6000000>;
953 reg = <0>;
50525891
SR		 954
955 vio-supply = <&vio>;
956
957 reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
958 interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */
959
960 touchscreen-fuzz-x = <4>;
961 touchscreen-fuzz-y = <7>;
962 touchscreen-fuzz-pressure = <2>;
8770d089
PM		 963 touchscreen-size-x = <4096>;
964 touchscreen-size-y = <4096>;
50525891
SR		 965 touchscreen-max-pressure = <2048>;
966
967 ti,x-plate-ohms = <280>;
968 ti,esd-recovery-timeout-ms = <8000>;
a4d4b153 969 };
1133420f 970
cbe92b02 971 lcd: acx565akm@2 {
1133420f 972 compatible = "sony,acx565akm";
a4d4b153
PM		 973 spi-max-frequency = <6000000>;
974 reg = <2>;
d1e6f516
SR		 975
976 pinctrl-names = "default";
1133420f
TV		 977 pinctrl-0 = <&acx565akm_pins>;
978
979 label = "lcd";
980 reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */
981
982 port {
983 lcd_in: endpoint {
984 remote-endpoint = <&sdi_out>;
985 };
986 };
a4d4b153
PM		 987 };
988};
989
c1ad2206
SR		 990&mcspi4 {
991 pinctrl-names = "default";
992 pinctrl-0 = <&mcspi4_pins>;
993
994 wl1251@0 {
995 pinctrl-names = "default";
996 pinctrl-0 = <&wl1251_pins>;
997
998 vio-supply = <&vio>;
999
1000 compatible = "ti,wl1251";
1001 reg = <0>;
1002 spi-max-frequency = <48000000>;
1003
1004 spi-cpol;
1005 spi-cpha;
1006
1007 ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
1008
1009 interrupt-parent = <&gpio2>;
1010 interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */
3d5c6568
SR		 1011
1012 clocks = <&vctcxo>;
c1ad2206
SR		 1013 };
1014};
1015
a4d4b153
PM		 1016&usb_otg_hs {
1017 interface-type = <0>;
1018 usb-phy = <&usb2_phy>;
d2afcf09
RQ		 1019 phys = <&usb2_phy>;
1020 phy-names = "usb2-phy";
a4d4b153
PM		 1021 mode = <2>;
1022 power = <50>;
1023};
7a89eecf
SR		 1024
1025&uart1 {
1026 status = "disabled";
1027};
1028
1029&uart2 {
1030 pinctrl-names = "default";
1031 pinctrl-0 = <&uart2_pins>;
3d5c6568
SR		 1032
1033 bcm2048: bluetooth {
1034 compatible = "brcm,bcm2048-nokia", "nokia,h4p-bluetooth";
1035 reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; /* 91 */
1036 host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */
1037 bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */
1038 clocks = <&vctcxo>;
1039 clock-names = "sysclk";
1040 };
7a89eecf
SR		 1041};
1042
1043&uart3 {
31f0820a 1044 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
7a89eecf
SR		 1045 pinctrl-names = "default";
1046 pinctrl-0 = <&uart3_pins>;
1047};
1133420f
TV		 1048
1049&dss {
1050 status = "ok";
1051
1052 pinctrl-names = "default";
1053 pinctrl-0 = <&dss_sdi_pins>;
1054
1055 vdds_sdi-supply = <&vaux1>;
1056
1057 ports {
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060
1061 port@1 {
1062 reg = <1>;
1063
1064 sdi_out: endpoint {
1065 remote-endpoint = <&lcd_in>;
1066 datapairs = <2>;
1067 };
1068 };
1069 };
1070};
1071
1072&venc {
1073 status = "ok";
1074
1075 vdda-supply = <&vdac>;
1076
1077 port {
1078 venc_out: endpoint {
1079 remote-endpoint = <&tv_connector_in>;
1080 ti,channels = <1>;
1081 };
1082 };
1083};
f7d0f2a0
SR		 1084
1085&mcbsp2 {
1086 status = "ok";
1087};
782e25a4
SR		 1088
1089&ssi_port1 {
1090 pinctrl-names = "default";
1091 pinctrl-0 = <&ssi_pins>;
1092
1093 ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
76ad4ac1
SR		 1094
1095 modem: hsi-client {
1096 compatible = "nokia,n900-modem";
1097
1098 pinctrl-names = "default";
1099 pinctrl-0 = <&modem_pins>;
1100
1101 hsi-channel-ids = <0>, <1>, <2>, <3>;
1102 hsi-channel-names = "mcsaab-control",
1103 "speech-control",
1104 "speech-data",
1105 "mcsaab-data";
1106 hsi-speed-kbps = <55000>;
1107 hsi-mode = "frame";
1108 hsi-flow = "synchronized";
1109 hsi-arb-mode = "round-robin";
1110
1111 interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
1112
1113 gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */
1114 <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */
1115 <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
1116 <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
1117 <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
1118 gpio-names = "cmt_apeslpx",
1119 "cmt_rst_rq",
1120 "cmt_en",
1121 "cmt_rst",
1122 "cmt_bsi";
1123 };
782e25a4
SR		 1124};
1125
1126&ssi_port2 {
1127 status = "disabled";
76ad4ac1 1128};
Ubuntu Eoan Linux kernel mirror