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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / omap3-n950-n9.dtsi
CommitLineData
df013188
AK		 1/*
2 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
3 *
4 * Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
a494e32d 11#include "omap36xx.dtsi"
df013188
AK		 12
13/ {
14 cpus {
15 cpu@0 {
16 cpu0-supply = <&vcc>;
0f4f1542
FM		 17 operating-points = <
18 /* kHz uV */
19 300000 1012500
20 600000 1200000
21 800000 1325000
22 1000000 1375000
23 >;
df013188
AK		 24 };
25 };
26
81777ff9 27 memory@80000000 {
df013188
AK		 28 device_type = "memory";
29 reg = <0x80000000 0x40000000>; /* 1 GB */
30 };
31
909b0ebd 32 vemmc: fixedregulator0 {
df013188
AK		 33 compatible = "regulator-fixed";
34 regulator-name = "VEMMC";
35 regulator-min-microvolt = <2900000>;
36 regulator-max-microvolt = <2900000>;
3a637e00 37 gpio = <&gpio5 29 GPIO_ACTIVE_HIGH>; /* gpio line 157 */
df013188
AK		 38 startup-delay-us = <150>;
39 enable-active-high;
40 };
96d3bb1a 41
909b0ebd 42 vwlan_fixed: fixedregulator2 {
96d3bb1a
SR		 43 compatible = "regulator-fixed";
44 regulator-name = "VWLAN";
45 gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */
46 enable-active-high;
47 regulator-boot-off;
48 };
d5b0eab7
SR		 49
50 leds {
51 compatible = "gpio-leds";
52
53 heartbeat {
54 label = "debug::sleep";
55 gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; /* gpio92 */
56 linux,default-trigger = "default-on";
57 pinctrl-names = "default";
58 pinctrl-0 = <&debug_leds>;
59 };
60 };
53cee931
SR		 61
62 /* controlled (enabled/disabled) directly by wl1271 */
63 vctcxo: vctcxo {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <38400000>;
67 };
df013188
AK		 68};
69
70&omap3_pmx_core {
83faf920
FM		 71 accelerator_pins: pinmux_accelerator_pins {
72 pinctrl-single,pins = <
73 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */
74 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */
75 >;
76 };
77
d5b0eab7
SR		 78 debug_leds: pinmux_debug_led_pins {
79 pinctrl-single,pins = <
80 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */
81 >;
82 };
83
df013188
AK		 84 mmc2_pins: pinmux_mmc2_pins {
85 pinctrl-single,pins = <
53ccdd4b
JMC		 86 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
87 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
88 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
89 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
90 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
91 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
df013188
AK		 92 >;
93 };
96d3bb1a
SR		 94
95 wlan_pins: pinmux_wlan_pins {
96 pinctrl-single,pins = <
97 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */
98 OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */
99 >;
100 };
3bec8c81
SR		 101
102 ssi_pins: pinmux_ssi_pins {
103 pinctrl-single,pins = <
104 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
105 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
106 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
e0e80d43 107 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
3bec8c81
SR		 108 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
109 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
110 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
111 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
112 >;
113 };
f21b9873 114
60fca6b2
SR		 115 ssi_pins_idle: pinmux_ssi_pins_idle {
116 pinctrl-single,pins = <
117 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */
118 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */
119 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */
e0e80d43 120 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
60fca6b2
SR		 121 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */
122 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */
123 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */
124 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7) /* ssi1_wake */
125 >;
126 };
127
f21b9873
SR		 128 modem_pins1: pinmux_modem_core1_pins {
129 pinctrl-single,pins = <
e0e80d43 130 OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */
f21b9873
SR		 131 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */
132 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */
133 >;
134 };
53cee931
SR		 135
136 uart2_pins: pinmux_uart2_pins {
137 pinctrl-single,pins = <
138 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
139 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */
140 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
141 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
142 >;
143 };
f21b9873
SR		 144};
145
146&omap3_pmx_core2 {
147 modem_pins2: pinmux_modem_core2_pins {
148 pinctrl-single,pins = <
149 OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* gpio_23 (cmt_en) */
150 >;
151 };
df013188
AK		 152};
153
154&i2c1 {
155 clock-frequency = <2900000>;
156
157 twl: twl@48 {
158 reg = <0x48>;
159 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
160 interrupt-parent = <&intc>;
161 };
162};
163
164/include/ "twl4030.dtsi"
165
166&twl {
167 compatible = "ti,twl5031";
f4b36909
AK		 168
169 twl_power: power {
170 compatible = "ti,twl4030-power";
171 ti,use_poweroff;
172 };
df013188
AK		 173};
174
175&twl_gpio {
176 ti,pullups = <0x000001>; /* BIT(0) */
177 ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */
178};
179
50413b9d
SR		 180&vdac {
181 regulator-name = "vdac";
182 regulator-min-microvolt = <1800000>;
183 regulator-max-microvolt = <1800000>;
184};
185
186&vpll1 {
187 regulator-name = "vpll1";
188 regulator-min-microvolt = <1800000>;
189 regulator-max-microvolt = <1800000>;
190};
191
192&vpll2 {
193 regulator-name = "vpll2";
194 regulator-min-microvolt = <1800000>;
195 regulator-max-microvolt = <1800000>;
196};
197
198&vaux1 {
199 regulator-name = "vaux1";
200 regulator-min-microvolt = <2800000>;
201 regulator-max-microvolt = <2800000>;
202};
203
79f7f37a
SA		 204/* CSI-2 receiver */
205&vaux2 {
206 regulator-name = "vaux2";
207 regulator-min-microvolt = <1800000>;
208 regulator-max-microvolt = <1800000>;
209};
210
211/* Cameras */
212&vaux3 {
213 regulator-name = "vaux3";
214 regulator-min-microvolt = <2800000>;
215 regulator-max-microvolt = <2800000>;
216};
217
50413b9d
SR		 218&vaux4 {
219 regulator-name = "vaux4";
220 regulator-min-microvolt = <2800000>;
221 regulator-max-microvolt = <2800000>;
222};
223
224&vmmc1 {
225 regulator-name = "vmmc1";
226 regulator-min-microvolt = <1850000>;
227 regulator-max-microvolt = <3150000>;
228};
229
230&vmmc2 {
231 regulator-name = "vmmc2";
232 regulator-min-microvolt = <3000000>;
233 regulator-max-microvolt = <3000000>;
234};
235
236&vintana1 {
237 regulator-name = "vintana1";
238 regulator-min-microvolt = <1500000>;
239 regulator-max-microvolt = <1500000>;
240};
241
242&vintana2 {
243 regulator-name = "vintana2";
244 regulator-min-microvolt = <2750000>;
245 regulator-max-microvolt = <2750000>;
246};
247
248&vintdig {
249 regulator-name = "vintdig";
250 regulator-min-microvolt = <1500000>;
251 regulator-max-microvolt = <1500000>;
252};
253
254&vsim {
255 regulator-name = "vsim";
256 regulator-min-microvolt = <1800000>;
257 regulator-max-microvolt = <1800000>;
258};
259
260&vio {
261 regulator-name = "vio";
262 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <1800000>;
264};
265
df013188
AK		 266&i2c2 {
267 clock-frequency = <400000>;
d726a0dc
SA		 268
269 as3645a@30 {
e626c325
SA		 270 #address-cells = <1>;
271 #size-cells = <0>;
d726a0dc
SA		 272 reg = <0x30>;
273 compatible = "ams,as3645a";
ceb3c45b 274 as3645a_flash: flash@0 {
e626c325 275 reg = <0x0>;
d726a0dc
SA		 276 flash-timeout-us = <150000>;
277 flash-max-microamp = <320000>;
278 led-max-microamp = <60000>;
af2e658f 279 ams,input-max-microamp = <1750000>;
d726a0dc 280 };
ceb3c45b 281 as3645a_indicator: indicator@1 {
e626c325 282 reg = <0x1>;
d726a0dc
SA		 283 led-max-microamp = <10000>;
284 };
285 };
df013188
AK		 286};
287
288&i2c3 {
289 clock-frequency = <400000>;
83faf920
FM		 290
291 lis302: lis302@1d {
292 compatible = "st,lis3lv02d";
293 reg = <0x1d>;
294
295 Vdd-supply = <&vaux1>;
296 Vdd_IO-supply = <&vio>;
297
298 pinctrl-names = "default";
299 pinctrl-0 = <&accelerator_pins>;
300
301 interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */
302
303 /* click flags */
304 st,click-single-x;
305 st,click-single-y;
306 st,click-single-z;
307
308 /* Limits are 0.5g * value */
309 st,click-threshold-x = <8>;
310 st,click-threshold-y = <8>;
311 st,click-threshold-z = <10>;
312
313 /* Click must be longer than time limit */
314 st,click-time-limit = <9>;
315
316 /* Kind of debounce filter */
317 st,click-latency = <50>;
318
319 st,wakeup-x-hi;
320 st,wakeup-y-hi;
321 st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
322
323 st,wakeup2-z-hi;
324 st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */
325
326 st,highpass-cutoff-hz = <2>;
327
328 /* Interrupt line 1 for thresholds */
329 st,irq1-ff-wu-1;
330 st,irq1-ff-wu-2;
331 /* Interrupt line 2 for click detection */
332 st,irq2-click;
333
334 st,wu-duration-1 = <8>;
335 st,wu-duration-2 = <8>;
336 };
df013188
AK		 337};
338
339&mmc1 {
340 status = "disabled";
341};
342
343&mmc2 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&mmc2_pins>;
346 vmmc-supply = <&vemmc>;
347 bus-width = <4>;
348 ti,non-removable;
349};
350
351&mmc3 {
352 status = "disabled";
353};
354
355&usb_otg_hs {
356 interface-type = <0>;
357 usb-phy = <&usb2_phy>;
358 phys = <&usb2_phy>;
359 phy-names = "usb2-phy";
360 mode = <3>;
361 power = <50>;
362};
363
364&gpmc {
e2c5eb78 365 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
df013188
AK		 366
367 onenand@0,0 {
368 #address-cells = <1>;
369 #size-cells = <1>;
e2c5eb78 370 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
df013188 371
4ca2311c
AK		 372 /*
373 * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported
374 * bootloader set values when booted with v4.19 using both N950
375 * and N9 devices (OneNAND Manufacturer: Samsung):
376 *
377 * gpmc cs0 before gpmc_cs_program_settings:
378 * cs0 GPMC_CS_CONFIG1: 0xfd001202
379 * cs0 GPMC_CS_CONFIG2: 0x00181800
380 * cs0 GPMC_CS_CONFIG3: 0x00030300
381 * cs0 GPMC_CS_CONFIG4: 0x18001804
382 * cs0 GPMC_CS_CONFIG5: 0x03171d1d
383 * cs0 GPMC_CS_CONFIG6: 0x97080000
384 */
df013188
AK		 385 gpmc,sync-read;
386 gpmc,sync-write;
387 gpmc,burst-length = <16>;
388 gpmc,burst-read;
389 gpmc,burst-wrap;
390 gpmc,burst-write;
391 gpmc,device-width = <2>;
392 gpmc,mux-add-data = <2>;
393 gpmc,cs-on-ns = <0>;
4ca2311c
AK		 394 gpmc,cs-rd-off-ns = <122>;
395 gpmc,cs-wr-off-ns = <122>;
df013188 396 gpmc,adv-on-ns = <0>;
4ca2311c
AK		 397 gpmc,adv-rd-off-ns = <15>;
398 gpmc,adv-wr-off-ns = <15>;
399 gpmc,oe-on-ns = <20>;
400 gpmc,oe-off-ns = <122>;
df013188 401 gpmc,we-on-ns = <0>;
4ca2311c
AK		 402 gpmc,we-off-ns = <122>;
403 gpmc,rd-cycle-ns = <148>;
404 gpmc,wr-cycle-ns = <148>;
405 gpmc,access-ns = <117>;
df013188
AK		 406 gpmc,page-burst-access-ns = <15>;
407 gpmc,bus-turnaround-ns = <0>;
408 gpmc,cycle2cycle-delay-ns = <0>;
409 gpmc,wait-monitoring-ns = <0>;
4ca2311c
AK		 410 gpmc,clk-activation-ns = <10>;
411 gpmc,wr-data-mux-bus-ns = <40>;
412 gpmc,wr-access-ns = <117>;
413
414 gpmc,sync-clk-ps = <15000>; /* TBC; Where this value came? */
df013188
AK		 415
416 /*
417 * MTD partition table corresponding to Nokia's MeeGo 1.2
418 * Harmattan release.
419 */
420 partition@0 {
421 label = "bootloader";
422 reg = <0x00000000 0x00100000>;
423 };
424 partition@1 {
425 label = "config";
426 reg = <0x00100000 0x002c0000>;
427 };
428 partition@2 {
429 label = "kernel";
430 reg = <0x003c0000 0x01000000>;
431 };
432 partition@3 {
433 label = "log";
434 reg = <0x013c0000 0x00200000>;
435 };
436 partition@4 {
437 label = "var";
438 reg = <0x015c0000 0x1ca40000>;
439 };
440 partition@5 {
441 label = "moslo";
442 reg = <0x1e000000 0x02000000>;
443 };
444 partition@6 {
445 label = "omap2-onenand";
446 reg = <0x00000000 0x20000000>;
447 };
448 };
449};
3bec8c81
SR		 450
451&ssi_port1 {
60fca6b2 452 pinctrl-names = "default", "idle";
3bec8c81 453 pinctrl-0 = <&ssi_pins>;
60fca6b2 454 pinctrl-1 = <&ssi_pins_idle>;
3bec8c81
SR		 455
456 ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
f21b9873
SR		 457
458 modem: hsi-client {
459 pinctrl-names = "default";
460 pinctrl-0 = <&modem_pins1 &modem_pins2>;
461
462 hsi-channel-ids = <0>, <1>, <2>, <3>;
463 hsi-channel-names = "mcsaab-control",
464 "speech-control",
465 "speech-data",
466 "mcsaab-data";
467 hsi-speed-kbps = <96000>;
468 hsi-mode = "frame";
469 hsi-flow = "synchronized";
470 hsi-arb-mode = "round-robin";
471
472 interrupts-extended = <&gpio2 2 IRQ_TYPE_EDGE_RISING>; /* gpio 34 */
473
474 gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>, /* gpio 93 */
475 <&gpio3 24 GPIO_ACTIVE_HIGH>, /* gpio 88 */
476 <&gpio1 23 GPIO_ACTIVE_HIGH>; /* gpio 23 */
477 gpio-names = "cmt_apeslpx",
478 "cmt_rst_rq",
479 "cmt_en";
480 };
3bec8c81
SR		 481};
482
483&ssi_port2 {
484 status = "disabled";
485};
53cee931
SR		 486
487&uart2 {
488 pinctrl-names = "default";
489 pinctrl-0 = <&uart2_pins>;
490
491 bluetooth {
492 compatible = "ti,wl1271-bluetooth-nokia", "nokia,h4p-bluetooth";
493
494 reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; /* 26 */
495 host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */
496 bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */
497
498 clocks = <&vctcxo>;
499 clock-names = "sysclk";
500 };
501};
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