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Commit | Line | Data |
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189892f4 BC |
1 | /* |
2 | * Device Tree Source for OMAP3 SoC | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
6d624eab | 11 | #include <dt-bindings/gpio/gpio.h> |
71fdc6e4 | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
bcd3cca7 | 13 | #include <dt-bindings/pinctrl/omap.h> |
6d624eab | 14 | |
98ef7957 | 15 | #include "skeleton.dtsi" |
189892f4 BC |
16 | |
17 | / { | |
18 | compatible = "ti,omap3430", "ti,omap3"; | |
4c94ac29 | 19 | interrupt-parent = <&intc>; |
189892f4 | 20 | |
cf3c79de | 21 | aliases { |
20b80942 NM |
22 | i2c0 = &i2c1; |
23 | i2c1 = &i2c2; | |
24 | i2c2 = &i2c3; | |
cf3c79de RN |
25 | serial0 = &uart1; |
26 | serial1 = &uart2; | |
27 | serial2 = &uart3; | |
cf3c79de RN |
28 | }; |
29 | ||
476b679a | 30 | cpus { |
eeb25fd5 LP |
31 | #address-cells = <1>; |
32 | #size-cells = <0>; | |
33 | ||
476b679a BC |
34 | cpu@0 { |
35 | compatible = "arm,cortex-a8"; | |
eeb25fd5 LP |
36 | device_type = "cpu"; |
37 | reg = <0x0>; | |
8d766fa2 NM |
38 | |
39 | clocks = <&dpll1_ck>; | |
40 | clock-names = "cpu"; | |
41 | ||
42 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
476b679a BC |
43 | }; |
44 | }; | |
45 | ||
9b07b477 JH |
46 | pmu { |
47 | compatible = "arm,cortex-a8-pmu"; | |
d7c8f259 | 48 | reg = <0x54000000 0x800000>; |
9b07b477 JH |
49 | interrupts = <3>; |
50 | ti,hwmods = "debugss"; | |
51 | }; | |
52 | ||
189892f4 | 53 | /* |
161e89a6 | 54 | * The soc node represents the soc top level view. It is used for IPs |
189892f4 BC |
55 | * that are not memory mapped in the MPU view or for the MPU itself. |
56 | */ | |
57 | soc { | |
58 | compatible = "ti,omap-infra"; | |
476b679a BC |
59 | mpu { |
60 | compatible = "ti,omap3-mpu"; | |
61 | ti,hwmods = "mpu"; | |
62 | }; | |
63 | ||
64 | iva { | |
65 | compatible = "ti,iva2.2"; | |
66 | ti,hwmods = "iva"; | |
67 | ||
68 | dsp { | |
69 | compatible = "ti,omap3-c64"; | |
70 | }; | |
71 | }; | |
189892f4 BC |
72 | }; |
73 | ||
74 | /* | |
75 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
76 | * The real OMAP interconnect network is quite complex. | |
77 | * Since that will not bring real advantage to represent that in DT for | |
78 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
79 | * hierarchy. | |
80 | */ | |
81 | ocp { | |
82 | compatible = "simple-bus"; | |
d7c8f259 TL |
83 | reg = <0x68000000 0x10000>; |
84 | interrupts = <9 10>; | |
189892f4 BC |
85 | #address-cells = <1>; |
86 | #size-cells = <1>; | |
87 | ranges; | |
88 | ti,hwmods = "l3_main"; | |
89 | ||
7ce93f31 TL |
90 | aes: aes@480c5000 { |
91 | compatible = "ti,omap3-aes"; | |
92 | ti,hwmods = "aes"; | |
93 | reg = <0x480c5000 0x50>; | |
94 | interrupts = <0>; | |
95 | }; | |
96 | ||
657fc11c TK |
97 | prm: prm@48306000 { |
98 | compatible = "ti,omap3-prm"; | |
99 | reg = <0x48306000 0x4000>; | |
100 | ||
101 | prm_clocks: clocks { | |
102 | #address-cells = <1>; | |
103 | #size-cells = <0>; | |
104 | }; | |
105 | ||
106 | prm_clockdomains: clockdomains { | |
107 | }; | |
108 | }; | |
109 | ||
110 | cm: cm@48004000 { | |
111 | compatible = "ti,omap3-cm"; | |
112 | reg = <0x48004000 0x4000>; | |
113 | ||
114 | cm_clocks: clocks { | |
115 | #address-cells = <1>; | |
116 | #size-cells = <0>; | |
117 | }; | |
118 | ||
119 | cm_clockdomains: clockdomains { | |
120 | }; | |
121 | }; | |
122 | ||
123 | scrm: scrm@48002000 { | |
124 | compatible = "ti,omap3-scrm"; | |
125 | reg = <0x48002000 0x2000>; | |
126 | ||
127 | scrm_clocks: clocks { | |
128 | #address-cells = <1>; | |
129 | #size-cells = <0>; | |
130 | }; | |
131 | ||
132 | scrm_clockdomains: clockdomains { | |
133 | }; | |
134 | }; | |
135 | ||
510c0ffd JH |
136 | counter32k: counter@48320000 { |
137 | compatible = "ti,omap-counter32k"; | |
138 | reg = <0x48320000 0x20>; | |
139 | ti,hwmods = "counter_32k"; | |
140 | }; | |
141 | ||
d65c5423 BC |
142 | intc: interrupt-controller@48200000 { |
143 | compatible = "ti,omap2-intc"; | |
189892f4 BC |
144 | interrupt-controller; |
145 | #interrupt-cells = <1>; | |
d65c5423 BC |
146 | ti,intc-size = <96>; |
147 | reg = <0x48200000 0x1000>; | |
189892f4 | 148 | }; |
cf3c79de | 149 | |
2c2dc545 JH |
150 | sdma: dma-controller@48056000 { |
151 | compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; | |
152 | reg = <0x48056000 0x1000>; | |
153 | interrupts = <12>, | |
154 | <13>, | |
155 | <14>, | |
156 | <15>; | |
157 | #dma-cells = <1>; | |
158 | #dma-channels = <32>; | |
159 | #dma-requests = <96>; | |
160 | }; | |
161 | ||
679e3310 TL |
162 | omap3_pmx_core: pinmux@48002030 { |
163 | compatible = "ti,omap3-padconf", "pinctrl-single"; | |
3d495383 | 164 | reg = <0x48002030 0x0238>; |
679e3310 TL |
165 | #address-cells = <1>; |
166 | #size-cells = <0>; | |
30a69ef7 TL |
167 | #interrupt-cells = <1>; |
168 | interrupt-controller; | |
679e3310 | 169 | pinctrl-single,register-width = <16>; |
d623a0e1 | 170 | pinctrl-single,function-mask = <0xff1f>; |
679e3310 TL |
171 | }; |
172 | ||
b7317777 | 173 | omap3_pmx_wkup: pinmux@48002a00 { |
679e3310 | 174 | compatible = "ti,omap3-padconf", "pinctrl-single"; |
161e89a6 | 175 | reg = <0x48002a00 0x5c>; |
679e3310 TL |
176 | #address-cells = <1>; |
177 | #size-cells = <0>; | |
30a69ef7 TL |
178 | #interrupt-cells = <1>; |
179 | interrupt-controller; | |
679e3310 | 180 | pinctrl-single,register-width = <16>; |
d623a0e1 | 181 | pinctrl-single,function-mask = <0xff1f>; |
679e3310 TL |
182 | }; |
183 | ||
385a64bb BC |
184 | gpio1: gpio@48310000 { |
185 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
186 | reg = <0x48310000 0x200>; |
187 | interrupts = <29>; | |
385a64bb | 188 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 189 | ti,gpio-always-on; |
385a64bb BC |
190 | gpio-controller; |
191 | #gpio-cells = <2>; | |
192 | interrupt-controller; | |
ff5c9059 | 193 | #interrupt-cells = <2>; |
385a64bb BC |
194 | }; |
195 | ||
196 | gpio2: gpio@49050000 { | |
197 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
198 | reg = <0x49050000 0x200>; |
199 | interrupts = <30>; | |
385a64bb BC |
200 | ti,hwmods = "gpio2"; |
201 | gpio-controller; | |
202 | #gpio-cells = <2>; | |
203 | interrupt-controller; | |
ff5c9059 | 204 | #interrupt-cells = <2>; |
385a64bb BC |
205 | }; |
206 | ||
207 | gpio3: gpio@49052000 { | |
208 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
209 | reg = <0x49052000 0x200>; |
210 | interrupts = <31>; | |
385a64bb BC |
211 | ti,hwmods = "gpio3"; |
212 | gpio-controller; | |
213 | #gpio-cells = <2>; | |
214 | interrupt-controller; | |
ff5c9059 | 215 | #interrupt-cells = <2>; |
385a64bb BC |
216 | }; |
217 | ||
218 | gpio4: gpio@49054000 { | |
219 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
220 | reg = <0x49054000 0x200>; |
221 | interrupts = <32>; | |
385a64bb BC |
222 | ti,hwmods = "gpio4"; |
223 | gpio-controller; | |
224 | #gpio-cells = <2>; | |
225 | interrupt-controller; | |
ff5c9059 | 226 | #interrupt-cells = <2>; |
385a64bb BC |
227 | }; |
228 | ||
229 | gpio5: gpio@49056000 { | |
230 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
231 | reg = <0x49056000 0x200>; |
232 | interrupts = <33>; | |
385a64bb BC |
233 | ti,hwmods = "gpio5"; |
234 | gpio-controller; | |
235 | #gpio-cells = <2>; | |
236 | interrupt-controller; | |
ff5c9059 | 237 | #interrupt-cells = <2>; |
385a64bb BC |
238 | }; |
239 | ||
240 | gpio6: gpio@49058000 { | |
241 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
242 | reg = <0x49058000 0x200>; |
243 | interrupts = <34>; | |
385a64bb BC |
244 | ti,hwmods = "gpio6"; |
245 | gpio-controller; | |
246 | #gpio-cells = <2>; | |
247 | interrupt-controller; | |
ff5c9059 | 248 | #interrupt-cells = <2>; |
385a64bb BC |
249 | }; |
250 | ||
19bfb76c | 251 | uart1: serial@4806a000 { |
cf3c79de | 252 | compatible = "ti,omap3-uart"; |
d7c8f259 TL |
253 | reg = <0x4806a000 0x2000>; |
254 | interrupts = <72>; | |
255 | dmas = <&sdma 49 &sdma 50>; | |
256 | dma-names = "tx", "rx"; | |
cf3c79de RN |
257 | ti,hwmods = "uart1"; |
258 | clock-frequency = <48000000>; | |
259 | }; | |
260 | ||
19bfb76c | 261 | uart2: serial@4806c000 { |
cf3c79de | 262 | compatible = "ti,omap3-uart"; |
d7c8f259 TL |
263 | reg = <0x4806c000 0x400>; |
264 | interrupts = <73>; | |
265 | dmas = <&sdma 51 &sdma 52>; | |
266 | dma-names = "tx", "rx"; | |
cf3c79de RN |
267 | ti,hwmods = "uart2"; |
268 | clock-frequency = <48000000>; | |
269 | }; | |
270 | ||
19bfb76c | 271 | uart3: serial@49020000 { |
cf3c79de | 272 | compatible = "ti,omap3-uart"; |
d7c8f259 TL |
273 | reg = <0x49020000 0x400>; |
274 | interrupts = <74>; | |
275 | dmas = <&sdma 53 &sdma 54>; | |
276 | dma-names = "tx", "rx"; | |
cf3c79de RN |
277 | ti,hwmods = "uart3"; |
278 | clock-frequency = <48000000>; | |
279 | }; | |
280 | ||
ca59a5c1 BC |
281 | i2c1: i2c@48070000 { |
282 | compatible = "ti,omap3-i2c"; | |
d7c8f259 TL |
283 | reg = <0x48070000 0x80>; |
284 | interrupts = <56>; | |
285 | dmas = <&sdma 27 &sdma 28>; | |
286 | dma-names = "tx", "rx"; | |
ca59a5c1 BC |
287 | #address-cells = <1>; |
288 | #size-cells = <0>; | |
289 | ti,hwmods = "i2c1"; | |
290 | }; | |
291 | ||
292 | i2c2: i2c@48072000 { | |
293 | compatible = "ti,omap3-i2c"; | |
d7c8f259 TL |
294 | reg = <0x48072000 0x80>; |
295 | interrupts = <57>; | |
296 | dmas = <&sdma 29 &sdma 30>; | |
297 | dma-names = "tx", "rx"; | |
ca59a5c1 BC |
298 | #address-cells = <1>; |
299 | #size-cells = <0>; | |
300 | ti,hwmods = "i2c2"; | |
301 | }; | |
302 | ||
303 | i2c3: i2c@48060000 { | |
304 | compatible = "ti,omap3-i2c"; | |
d7c8f259 TL |
305 | reg = <0x48060000 0x80>; |
306 | interrupts = <61>; | |
307 | dmas = <&sdma 25 &sdma 26>; | |
308 | dma-names = "tx", "rx"; | |
ca59a5c1 BC |
309 | #address-cells = <1>; |
310 | #size-cells = <0>; | |
311 | ti,hwmods = "i2c3"; | |
312 | }; | |
fc72d248 | 313 | |
7ce93f31 TL |
314 | mailbox: mailbox@48094000 { |
315 | compatible = "ti,omap3-mailbox"; | |
316 | ti,hwmods = "mailbox"; | |
317 | reg = <0x48094000 0x200>; | |
318 | interrupts = <26>; | |
319 | }; | |
320 | ||
fc72d248 BC |
321 | mcspi1: spi@48098000 { |
322 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
323 | reg = <0x48098000 0x100>; |
324 | interrupts = <65>; | |
fc72d248 BC |
325 | #address-cells = <1>; |
326 | #size-cells = <0>; | |
327 | ti,hwmods = "mcspi1"; | |
328 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
329 | dmas = <&sdma 35>, |
330 | <&sdma 36>, | |
331 | <&sdma 37>, | |
332 | <&sdma 38>, | |
333 | <&sdma 39>, | |
334 | <&sdma 40>, | |
335 | <&sdma 41>, | |
336 | <&sdma 42>; | |
337 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
338 | "tx2", "rx2", "tx3", "rx3"; | |
fc72d248 BC |
339 | }; |
340 | ||
341 | mcspi2: spi@4809a000 { | |
342 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
343 | reg = <0x4809a000 0x100>; |
344 | interrupts = <66>; | |
fc72d248 BC |
345 | #address-cells = <1>; |
346 | #size-cells = <0>; | |
347 | ti,hwmods = "mcspi2"; | |
348 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
349 | dmas = <&sdma 43>, |
350 | <&sdma 44>, | |
351 | <&sdma 45>, | |
352 | <&sdma 46>; | |
353 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
fc72d248 BC |
354 | }; |
355 | ||
356 | mcspi3: spi@480b8000 { | |
357 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
358 | reg = <0x480b8000 0x100>; |
359 | interrupts = <91>; | |
fc72d248 BC |
360 | #address-cells = <1>; |
361 | #size-cells = <0>; | |
362 | ti,hwmods = "mcspi3"; | |
363 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
364 | dmas = <&sdma 15>, |
365 | <&sdma 16>, | |
366 | <&sdma 23>, | |
367 | <&sdma 24>; | |
368 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
fc72d248 BC |
369 | }; |
370 | ||
371 | mcspi4: spi@480ba000 { | |
372 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
373 | reg = <0x480ba000 0x100>; |
374 | interrupts = <48>; | |
fc72d248 BC |
375 | #address-cells = <1>; |
376 | #size-cells = <0>; | |
377 | ti,hwmods = "mcspi4"; | |
378 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
379 | dmas = <&sdma 70>, <&sdma 71>; |
380 | dma-names = "tx0", "rx0"; | |
fc72d248 | 381 | }; |
b3431f5b | 382 | |
d7c8f259 TL |
383 | hdqw1w: 1w@480b2000 { |
384 | compatible = "ti,omap3-1w"; | |
385 | reg = <0x480b2000 0x1000>; | |
386 | interrupts = <58>; | |
387 | ti,hwmods = "hdq1w"; | |
388 | }; | |
389 | ||
b3431f5b RN |
390 | mmc1: mmc@4809c000 { |
391 | compatible = "ti,omap3-hsmmc"; | |
d7c8f259 TL |
392 | reg = <0x4809c000 0x200>; |
393 | interrupts = <83>; | |
b3431f5b RN |
394 | ti,hwmods = "mmc1"; |
395 | ti,dual-volt; | |
2c2dc545 JH |
396 | dmas = <&sdma 61>, <&sdma 62>; |
397 | dma-names = "tx", "rx"; | |
b3431f5b RN |
398 | }; |
399 | ||
400 | mmc2: mmc@480b4000 { | |
401 | compatible = "ti,omap3-hsmmc"; | |
d7c8f259 TL |
402 | reg = <0x480b4000 0x200>; |
403 | interrupts = <86>; | |
b3431f5b | 404 | ti,hwmods = "mmc2"; |
2c2dc545 JH |
405 | dmas = <&sdma 47>, <&sdma 48>; |
406 | dma-names = "tx", "rx"; | |
b3431f5b RN |
407 | }; |
408 | ||
409 | mmc3: mmc@480ad000 { | |
410 | compatible = "ti,omap3-hsmmc"; | |
d7c8f259 TL |
411 | reg = <0x480ad000 0x200>; |
412 | interrupts = <94>; | |
b3431f5b | 413 | ti,hwmods = "mmc3"; |
2c2dc545 JH |
414 | dmas = <&sdma 77>, <&sdma 78>; |
415 | dma-names = "tx", "rx"; | |
b3431f5b | 416 | }; |
94c30732 | 417 | |
7ce93f31 TL |
418 | mmu_isp: mmu@480bd400 { |
419 | compatible = "ti,omap3-mmu-isp"; | |
420 | ti,hwmods = "mmu_isp"; | |
421 | reg = <0x480bd400 0x80>; | |
422 | interrupts = <8>; | |
423 | }; | |
424 | ||
94c30732 XJ |
425 | wdt2: wdt@48314000 { |
426 | compatible = "ti,omap3-wdt"; | |
d7c8f259 | 427 | reg = <0x48314000 0x80>; |
94c30732 XJ |
428 | ti,hwmods = "wd_timer2"; |
429 | }; | |
0be484bf PU |
430 | |
431 | mcbsp1: mcbsp@48074000 { | |
432 | compatible = "ti,omap3-mcbsp"; | |
433 | reg = <0x48074000 0xff>; | |
434 | reg-names = "mpu"; | |
435 | interrupts = <16>, /* OCP compliant interrupt */ | |
436 | <59>, /* TX interrupt */ | |
437 | <60>; /* RX interrupt */ | |
438 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
439 | ti,buffer-size = <128>; |
440 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
441 | dmas = <&sdma 31>, |
442 | <&sdma 32>; | |
443 | dma-names = "tx", "rx"; | |
726322ce | 444 | status = "disabled"; |
0be484bf PU |
445 | }; |
446 | ||
447 | mcbsp2: mcbsp@49022000 { | |
448 | compatible = "ti,omap3-mcbsp"; | |
449 | reg = <0x49022000 0xff>, | |
450 | <0x49028000 0xff>; | |
451 | reg-names = "mpu", "sidetone"; | |
452 | interrupts = <17>, /* OCP compliant interrupt */ | |
453 | <62>, /* TX interrupt */ | |
454 | <63>, /* RX interrupt */ | |
455 | <4>; /* Sidetone */ | |
456 | interrupt-names = "common", "tx", "rx", "sidetone"; | |
0be484bf | 457 | ti,buffer-size = <1280>; |
eef6fcaa | 458 | ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; |
4e4ead73 SG |
459 | dmas = <&sdma 33>, |
460 | <&sdma 34>; | |
461 | dma-names = "tx", "rx"; | |
726322ce | 462 | status = "disabled"; |
0be484bf PU |
463 | }; |
464 | ||
465 | mcbsp3: mcbsp@49024000 { | |
466 | compatible = "ti,omap3-mcbsp"; | |
467 | reg = <0x49024000 0xff>, | |
468 | <0x4902a000 0xff>; | |
469 | reg-names = "mpu", "sidetone"; | |
470 | interrupts = <22>, /* OCP compliant interrupt */ | |
471 | <89>, /* TX interrupt */ | |
472 | <90>, /* RX interrupt */ | |
473 | <5>; /* Sidetone */ | |
474 | interrupt-names = "common", "tx", "rx", "sidetone"; | |
0be484bf | 475 | ti,buffer-size = <128>; |
eef6fcaa | 476 | ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; |
4e4ead73 SG |
477 | dmas = <&sdma 17>, |
478 | <&sdma 18>; | |
479 | dma-names = "tx", "rx"; | |
726322ce | 480 | status = "disabled"; |
0be484bf PU |
481 | }; |
482 | ||
483 | mcbsp4: mcbsp@49026000 { | |
484 | compatible = "ti,omap3-mcbsp"; | |
485 | reg = <0x49026000 0xff>; | |
486 | reg-names = "mpu"; | |
487 | interrupts = <23>, /* OCP compliant interrupt */ | |
488 | <54>, /* TX interrupt */ | |
489 | <55>; /* RX interrupt */ | |
490 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
491 | ti,buffer-size = <128>; |
492 | ti,hwmods = "mcbsp4"; | |
4e4ead73 SG |
493 | dmas = <&sdma 19>, |
494 | <&sdma 20>; | |
495 | dma-names = "tx", "rx"; | |
726322ce | 496 | status = "disabled"; |
0be484bf PU |
497 | }; |
498 | ||
499 | mcbsp5: mcbsp@48096000 { | |
500 | compatible = "ti,omap3-mcbsp"; | |
501 | reg = <0x48096000 0xff>; | |
502 | reg-names = "mpu"; | |
503 | interrupts = <27>, /* OCP compliant interrupt */ | |
504 | <81>, /* TX interrupt */ | |
505 | <82>; /* RX interrupt */ | |
506 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
507 | ti,buffer-size = <128>; |
508 | ti,hwmods = "mcbsp5"; | |
4e4ead73 SG |
509 | dmas = <&sdma 21>, |
510 | <&sdma 22>; | |
511 | dma-names = "tx", "rx"; | |
726322ce | 512 | status = "disabled"; |
0be484bf | 513 | }; |
fab8ad0b | 514 | |
7ce93f31 TL |
515 | sham: sham@480c3000 { |
516 | compatible = "ti,omap3-sham"; | |
517 | ti,hwmods = "sham"; | |
518 | reg = <0x480c3000 0x64>; | |
519 | interrupts = <49>; | |
520 | }; | |
521 | ||
522 | smartreflex_core: smartreflex@480cb000 { | |
523 | compatible = "ti,omap3-smartreflex-core"; | |
524 | ti,hwmods = "smartreflex_core"; | |
525 | reg = <0x480cb000 0x400>; | |
526 | interrupts = <19>; | |
527 | }; | |
528 | ||
529 | smartreflex_mpu_iva: smartreflex@480c9000 { | |
530 | compatible = "ti,omap3-smartreflex-iva"; | |
531 | ti,hwmods = "smartreflex_mpu_iva"; | |
532 | reg = <0x480c9000 0x400>; | |
533 | interrupts = <18>; | |
534 | }; | |
535 | ||
fab8ad0b | 536 | timer1: timer@48318000 { |
002e1ec5 | 537 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
538 | reg = <0x48318000 0x400>; |
539 | interrupts = <37>; | |
540 | ti,hwmods = "timer1"; | |
541 | ti,timer-alwon; | |
542 | }; | |
543 | ||
544 | timer2: timer@49032000 { | |
002e1ec5 | 545 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
546 | reg = <0x49032000 0x400>; |
547 | interrupts = <38>; | |
548 | ti,hwmods = "timer2"; | |
549 | }; | |
550 | ||
551 | timer3: timer@49034000 { | |
002e1ec5 | 552 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
553 | reg = <0x49034000 0x400>; |
554 | interrupts = <39>; | |
555 | ti,hwmods = "timer3"; | |
556 | }; | |
557 | ||
558 | timer4: timer@49036000 { | |
002e1ec5 | 559 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
560 | reg = <0x49036000 0x400>; |
561 | interrupts = <40>; | |
562 | ti,hwmods = "timer4"; | |
563 | }; | |
564 | ||
565 | timer5: timer@49038000 { | |
002e1ec5 | 566 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
567 | reg = <0x49038000 0x400>; |
568 | interrupts = <41>; | |
569 | ti,hwmods = "timer5"; | |
570 | ti,timer-dsp; | |
571 | }; | |
572 | ||
573 | timer6: timer@4903a000 { | |
002e1ec5 | 574 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
575 | reg = <0x4903a000 0x400>; |
576 | interrupts = <42>; | |
577 | ti,hwmods = "timer6"; | |
578 | ti,timer-dsp; | |
579 | }; | |
580 | ||
581 | timer7: timer@4903c000 { | |
002e1ec5 | 582 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
583 | reg = <0x4903c000 0x400>; |
584 | interrupts = <43>; | |
585 | ti,hwmods = "timer7"; | |
586 | ti,timer-dsp; | |
587 | }; | |
588 | ||
589 | timer8: timer@4903e000 { | |
002e1ec5 | 590 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
591 | reg = <0x4903e000 0x400>; |
592 | interrupts = <44>; | |
593 | ti,hwmods = "timer8"; | |
594 | ti,timer-pwm; | |
595 | ti,timer-dsp; | |
596 | }; | |
597 | ||
598 | timer9: timer@49040000 { | |
002e1ec5 | 599 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
600 | reg = <0x49040000 0x400>; |
601 | interrupts = <45>; | |
602 | ti,hwmods = "timer9"; | |
603 | ti,timer-pwm; | |
604 | }; | |
605 | ||
606 | timer10: timer@48086000 { | |
002e1ec5 | 607 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
608 | reg = <0x48086000 0x400>; |
609 | interrupts = <46>; | |
610 | ti,hwmods = "timer10"; | |
611 | ti,timer-pwm; | |
612 | }; | |
613 | ||
614 | timer11: timer@48088000 { | |
002e1ec5 | 615 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
616 | reg = <0x48088000 0x400>; |
617 | interrupts = <47>; | |
618 | ti,hwmods = "timer11"; | |
619 | ti,timer-pwm; | |
620 | }; | |
621 | ||
622 | timer12: timer@48304000 { | |
002e1ec5 | 623 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
624 | reg = <0x48304000 0x400>; |
625 | interrupts = <95>; | |
626 | ti,hwmods = "timer12"; | |
627 | ti,timer-alwon; | |
628 | ti,timer-secure; | |
629 | }; | |
af3eb366 RQ |
630 | |
631 | usbhstll: usbhstll@48062000 { | |
632 | compatible = "ti,usbhs-tll"; | |
633 | reg = <0x48062000 0x1000>; | |
634 | interrupts = <78>; | |
635 | ti,hwmods = "usb_tll_hs"; | |
636 | }; | |
637 | ||
638 | usbhshost: usbhshost@48064000 { | |
639 | compatible = "ti,usbhs-host"; | |
640 | reg = <0x48064000 0x400>; | |
641 | ti,hwmods = "usb_host_hs"; | |
642 | #address-cells = <1>; | |
643 | #size-cells = <1>; | |
644 | ranges; | |
645 | ||
646 | usbhsohci: ohci@48064400 { | |
a2525e54 | 647 | compatible = "ti,ohci-omap3"; |
af3eb366 RQ |
648 | reg = <0x48064400 0x400>; |
649 | interrupt-parent = <&intc>; | |
650 | interrupts = <76>; | |
651 | }; | |
652 | ||
653 | usbhsehci: ehci@48064800 { | |
a2525e54 | 654 | compatible = "ti,ehci-omap"; |
af3eb366 RQ |
655 | reg = <0x48064800 0x400>; |
656 | interrupt-parent = <&intc>; | |
657 | interrupts = <77>; | |
658 | }; | |
659 | }; | |
660 | ||
6e8489df FV |
661 | gpmc: gpmc@6e000000 { |
662 | compatible = "ti,omap3430-gpmc"; | |
663 | ti,hwmods = "gpmc"; | |
41644e75 | 664 | reg = <0x6e000000 0x02d0>; |
6e8489df FV |
665 | interrupts = <20>; |
666 | gpmc,num-cs = <8>; | |
667 | gpmc,num-waitpins = <4>; | |
668 | #address-cells = <2>; | |
669 | #size-cells = <1>; | |
670 | }; | |
ad871c10 KVA |
671 | |
672 | usb_otg_hs: usb_otg_hs@480ab000 { | |
673 | compatible = "ti,omap3-musb"; | |
674 | reg = <0x480ab000 0x1000>; | |
304e71e0 | 675 | interrupts = <92>, <93>; |
ad871c10 KVA |
676 | interrupt-names = "mc", "dma"; |
677 | ti,hwmods = "usb_otg_hs"; | |
ad871c10 KVA |
678 | multipoint = <1>; |
679 | num-eps = <16>; | |
680 | ram-bits = <12>; | |
681 | }; | |
189892f4 BC |
682 | }; |
683 | }; | |
657fc11c TK |
684 | |
685 | /include/ "omap3xxx-clocks.dtsi" |