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642f12b4 TL |
1 | /* |
2 | * Device Tree Source for OMAP3 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
e14d7e53 | 11 | #include <dt-bindings/bus/ti-sysc.h> |
e5211763 SA |
12 | #include <dt-bindings/media/omap3-isp.h> |
13 | ||
98ef7957 | 14 | #include "omap3.dtsi" |
642f12b4 TL |
15 | |
16 | / { | |
17 | aliases { | |
18 | serial3 = &uart4; | |
19 | }; | |
20 | ||
3027e267 NM |
21 | cpus { |
22 | /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ | |
a761d517 | 23 | cpu: cpu@0 { |
3027e267 NM |
24 | operating-points = < |
25 | /* kHz uV */ | |
e011cf69 NM |
26 | 300000 1012500 |
27 | 600000 1200000 | |
28 | 800000 1325000 | |
3027e267 NM |
29 | >; |
30 | clock-latency = <300000>; /* From legacy driver */ | |
31 | }; | |
32 | }; | |
33 | ||
f515f814 | 34 | ocp@68000000 { |
642f12b4 TL |
35 | uart4: serial@49042000 { |
36 | compatible = "ti,omap3-uart"; | |
d7c8f259 TL |
37 | reg = <0x49042000 0x400>; |
38 | interrupts = <80>; | |
39 | dmas = <&sdma 81 &sdma 82>; | |
40 | dma-names = "tx", "rx"; | |
642f12b4 TL |
41 | ti,hwmods = "uart4"; |
42 | clock-frequency = <48000000>; | |
43 | }; | |
3d495383 | 44 | |
b391d387 AT |
45 | abb_mpu_iva: regulator-abb-mpu { |
46 | compatible = "ti,abb-v1"; | |
47 | regulator-name = "abb_mpu_iva"; | |
3023aa4a | 48 | #address-cells = <0>; |
b391d387 AT |
49 | #size-cells = <0>; |
50 | reg = <0x483072f0 0x8>, <0x48306818 0x4>; | |
51 | reg-names = "base-address", "int-address"; | |
52 | ti,tranxdone-status-mask = <0x4000000>; | |
53 | clocks = <&sys_ck>; | |
54 | ti,settling-time = <30>; | |
55 | ti,clock-cycles = <8>; | |
56 | ti,abb_info = < | |
57 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
58 | 1012500 0 0 0 0 0 | |
59 | 1200000 0 0 0 0 0 | |
60 | 1325000 0 0 0 0 0 | |
61 | 1375000 1 0 0 0 0 | |
62 | >; | |
63 | }; | |
64 | ||
3d495383 LP |
65 | omap3_pmx_core2: pinmux@480025a0 { |
66 | compatible = "ti,omap3-padconf", "pinctrl-single"; | |
67 | reg = <0x480025a0 0x5c>; | |
68 | #address-cells = <1>; | |
69 | #size-cells = <0>; | |
be76fd31 | 70 | #pinctrl-cells = <1>; |
3d495383 LP |
71 | #interrupt-cells = <1>; |
72 | interrupt-controller; | |
73 | pinctrl-single,register-width = <16>; | |
74 | pinctrl-single,function-mask = <0xff1f>; | |
75 | }; | |
e5211763 SA |
76 | |
77 | isp: isp@480bc000 { | |
78 | compatible = "ti,omap3-isp"; | |
79 | reg = <0x480bc000 0x12fc | |
80 | 0x480bd800 0x0600>; | |
81 | interrupts = <24>; | |
82 | iommus = <&mmu_isp>; | |
30ecc84e | 83 | syscon = <&scm_conf 0x2f0>; |
e5211763 SA |
84 | ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>; |
85 | #clock-cells = <1>; | |
86 | ports { | |
87 | #address-cells = <1>; | |
88 | #size-cells = <0>; | |
89 | }; | |
90 | }; | |
12e47442 | 91 | |
a761d517 | 92 | bandgap: bandgap@48002524 { |
12e47442 PR |
93 | reg = <0x48002524 0x4>; |
94 | compatible = "ti,omap36xx-bandgap"; | |
95 | #thermal-sensor-cells = <0>; | |
96 | }; | |
e14d7e53 TL |
97 | |
98 | target-module@480cb000 { | |
99 | compatible = "ti,sysc-omap3630-sr", "ti,sysc"; | |
100 | ti,hwmods = "smartreflex_core"; | |
101 | reg = <0x480cb038 0x4>; | |
102 | reg-names = "sysc"; | |
103 | ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; | |
104 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
105 | <SYSC_IDLE_NO>, | |
106 | <SYSC_IDLE_SMART>; | |
107 | clocks = <&sr2_fck>; | |
108 | clock-names = "fck"; | |
109 | #address-cells = <1>; | |
110 | #size-cells = <1>; | |
111 | ranges = <0 0x480cb000 0x001000>; | |
112 | ||
113 | smartreflex_core: smartreflex@0 { | |
114 | compatible = "ti,omap3-smartreflex-core"; | |
115 | reg = <0 0x400>; | |
116 | interrupts = <19>; | |
117 | }; | |
118 | }; | |
119 | ||
120 | target-module@480c9000 { | |
121 | compatible = "ti,sysc-omap3630-sr", "ti,sysc"; | |
122 | ti,hwmods = "smartreflex_mpu_iva"; | |
123 | reg = <0x480c9038 0x4>; | |
124 | reg-names = "sysc"; | |
125 | ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; | |
126 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
127 | <SYSC_IDLE_NO>, | |
128 | <SYSC_IDLE_SMART>; | |
129 | clocks = <&sr1_fck>; | |
130 | clock-names = "fck"; | |
131 | #address-cells = <1>; | |
132 | #size-cells = <1>; | |
133 | ranges = <0 0x480c9000 0x001000>; | |
134 | ||
135 | ||
136 | smartreflex_mpu_iva: smartreflex@480c9000 { | |
137 | compatible = "ti,omap3-smartreflex-mpu-iva"; | |
138 | reg = <0 0x400>; | |
139 | interrupts = <18>; | |
140 | }; | |
141 | }; | |
642f12b4 | 142 | }; |
a761d517 K |
143 | |
144 | thermal_zones: thermal-zones { | |
145 | #include "omap3-cpu-thermal.dtsi" | |
146 | }; | |
642f12b4 | 147 | }; |
657fc11c | 148 | |
b8a7e42b TV |
149 | /* OMAP3630 needs dss_96m_fck for VENC */ |
150 | &venc { | |
151 | clocks = <&dss_tv_fck>, <&dss_96m_fck>; | |
152 | clock-names = "fck", "tv_dac_clk"; | |
153 | }; | |
154 | ||
782e25a4 SR |
155 | &ssi { |
156 | status = "ok"; | |
157 | ||
158 | clocks = <&ssi_ssr_fck>, | |
159 | <&ssi_sst_fck>, | |
160 | <&ssi_ick>; | |
161 | clock-names = "ssi_ssr_fck", | |
162 | "ssi_sst_fck", | |
163 | "ssi_ick"; | |
164 | }; | |
165 | ||
657fc11c TK |
166 | /include/ "omap34xx-omap36xx-clocks.dtsi" |
167 | /include/ "omap36xx-omap3430es2plus-clocks.dtsi" | |
d30492ad | 168 | /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" |
64a900ff | 169 | /include/ "omap36xx-clocks.dtsi" |