projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 657fc11c TK |
1 | /* |
| 2 | * Device Tree Source for OMAP3 clock data | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | &prm_clocks { | |
| 11 | virt_16_8m_ck: virt_16_8m_ck { | |
| 12 | #clock-cells = <0>; | |
| 13 | compatible = "fixed-clock"; | |
| 14 | clock-frequency = <16800000>; | |
| 15 | }; | |
| 16 | ||
| 17 | osc_sys_ck: osc_sys_ck { | |
| 18 | #clock-cells = <0>; | |
| 19 | compatible = "ti,mux-clock"; | |
| 20 | clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; | |
| 21 | reg = <0x0d40>; | |
| 22 | }; | |
| 23 | ||
| 24 | sys_ck: sys_ck { | |
| 25 | #clock-cells = <0>; | |
| 26 | compatible = "ti,divider-clock"; | |
| 27 | clocks = <&osc_sys_ck>; | |
| 28 | ti,bit-shift = <6>; | |
| 29 | ti,max-div = <3>; | |
| 30 | reg = <0x1270>; | |
| 31 | ti,index-starts-at-one; | |
| 32 | }; | |
| 33 | ||
| 34 | sys_clkout1: sys_clkout1 { | |
| 35 | #clock-cells = <0>; | |
| 36 | compatible = "ti,gate-clock"; | |
| 37 | clocks = <&osc_sys_ck>; | |
| 38 | reg = <0x0d70>; | |
| 39 | ti,bit-shift = <7>; | |
| 40 | }; | |
| 41 | ||
| 42 | dpll3_x2_ck: dpll3_x2_ck { | |
| 43 | #clock-cells = <0>; | |
| 44 | compatible = "fixed-factor-clock"; | |
| 45 | clocks = <&dpll3_ck>; | |
| 46 | clock-mult = <2>; | |
| 47 | clock-div = <1>; | |
| 48 | }; | |
| 49 | ||
| 50 | dpll3_m2x2_ck: dpll3_m2x2_ck { | |
| 51 | #clock-cells = <0>; | |
| 52 | compatible = "fixed-factor-clock"; | |
| 53 | clocks = <&dpll3_m2_ck>; | |
| 54 | clock-mult = <2>; | |
| 55 | clock-div = <1>; | |
| 56 | }; | |
| 57 | ||
| 58 | dpll4_x2_ck: dpll4_x2_ck { | |
| 59 | #clock-cells = <0>; | |
| 60 | compatible = "fixed-factor-clock"; | |
| 61 | clocks = <&dpll4_ck>; | |
| 62 | clock-mult = <2>; | |
| 63 | clock-div = <1>; | |
| 64 | }; | |
| 65 | ||
| 66 | corex2_fck: corex2_fck { | |
| 67 | #clock-cells = <0>; | |
| 68 | compatible = "fixed-factor-clock"; | |
| 69 | clocks = <&dpll3_m2x2_ck>; | |
| 70 | clock-mult = <1>; | |
| 71 | clock-div = <1>; | |
| 72 | }; | |
| 73 | ||
| 74 | wkup_l4_ick: wkup_l4_ick { | |
| 75 | #clock-cells = <0>; | |
| 76 | compatible = "fixed-factor-clock"; | |
| 77 | clocks = <&sys_ck>; | |
| 78 | clock-mult = <1>; | |
| 79 | clock-div = <1>; | |
| 80 | }; | |
| 81 | }; | |
| b8845074 TK |
82 | |
| 83 | &scm_clocks { | |
| 657fc11c TK |
84 | mcbsp5_mux_fck: mcbsp5_mux_fck { |
| 85 | #clock-cells = <0>; | |
| 86 | compatible = "ti,composite-mux-clock"; | |
| 87 | clocks = <&core_96m_fck>, <&mcbsp_clks>; | |
| 88 | ti,bit-shift = <4>; | |
| b8845074 | 89 | reg = <0x68>; |
| 657fc11c TK |
90 | }; |
| 91 | ||
| 92 | mcbsp5_fck: mcbsp5_fck { | |
| 93 | #clock-cells = <0>; | |
| 94 | compatible = "ti,composite-clock"; | |
| 95 | clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; | |
| 96 | }; | |
| 97 | ||
| 98 | mcbsp1_mux_fck: mcbsp1_mux_fck { | |
| 99 | #clock-cells = <0>; | |
| 100 | compatible = "ti,composite-mux-clock"; | |
| 101 | clocks = <&core_96m_fck>, <&mcbsp_clks>; | |
| 102 | ti,bit-shift = <2>; | |
| b8845074 | 103 | reg = <0x04>; |
| 657fc11c TK |
104 | }; |
| 105 | ||
| 106 | mcbsp1_fck: mcbsp1_fck { | |
| 107 | #clock-cells = <0>; | |
| 108 | compatible = "ti,composite-clock"; | |
| 109 | clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; | |
| 110 | }; | |
| 111 | ||
| 112 | mcbsp2_mux_fck: mcbsp2_mux_fck { | |
| 113 | #clock-cells = <0>; | |
| 114 | compatible = "ti,composite-mux-clock"; | |
| 115 | clocks = <&per_96m_fck>, <&mcbsp_clks>; | |
| 116 | ti,bit-shift = <6>; | |
| b8845074 | 117 | reg = <0x04>; |
| 657fc11c TK |
118 | }; |
| 119 | ||
| 120 | mcbsp2_fck: mcbsp2_fck { | |
| 121 | #clock-cells = <0>; | |
| 122 | compatible = "ti,composite-clock"; | |
| 123 | clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; | |
| 124 | }; | |
| 125 | ||
| 126 | mcbsp3_mux_fck: mcbsp3_mux_fck { | |
| 127 | #clock-cells = <0>; | |
| 128 | compatible = "ti,composite-mux-clock"; | |
| 129 | clocks = <&per_96m_fck>, <&mcbsp_clks>; | |
| b8845074 | 130 | reg = <0x68>; |
| 657fc11c TK |
131 | }; |
| 132 | ||
| 133 | mcbsp3_fck: mcbsp3_fck { | |
| 134 | #clock-cells = <0>; | |
| 135 | compatible = "ti,composite-clock"; | |
| 136 | clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; | |
| 137 | }; | |
| 138 | ||
| 139 | mcbsp4_mux_fck: mcbsp4_mux_fck { | |
| 140 | #clock-cells = <0>; | |
| 141 | compatible = "ti,composite-mux-clock"; | |
| 142 | clocks = <&per_96m_fck>, <&mcbsp_clks>; | |
| 143 | ti,bit-shift = <2>; | |
| b8845074 | 144 | reg = <0x68>; |
| 657fc11c TK |
145 | }; |
| 146 | ||
| 147 | mcbsp4_fck: mcbsp4_fck { | |
| 148 | #clock-cells = <0>; | |
| 149 | compatible = "ti,composite-clock"; | |
| 150 | clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; | |
| 151 | }; | |
| 152 | }; | |
| 153 | &cm_clocks { | |
| 154 | dummy_apb_pclk: dummy_apb_pclk { | |
| 155 | #clock-cells = <0>; | |
| 156 | compatible = "fixed-clock"; | |
| 157 | clock-frequency = <0x0>; | |
| 158 | }; | |
| 159 | ||
| 160 | omap_32k_fck: omap_32k_fck { | |
| 161 | #clock-cells = <0>; | |
| 162 | compatible = "fixed-clock"; | |
| 163 | clock-frequency = <32768>; | |
| 164 | }; | |
| 165 | ||
| 166 | virt_12m_ck: virt_12m_ck { | |
| 167 | #clock-cells = <0>; | |
| 168 | compatible = "fixed-clock"; | |
| 169 | clock-frequency = <12000000>; | |
| 170 | }; | |
| 171 | ||
| 172 | virt_13m_ck: virt_13m_ck { | |
| 173 | #clock-cells = <0>; | |
| 174 | compatible = "fixed-clock"; | |
| 175 | clock-frequency = <13000000>; | |
| 176 | }; | |
| 177 | ||
| 178 | virt_19200000_ck: virt_19200000_ck { | |
| 179 | #clock-cells = <0>; | |
| 180 | compatible = "fixed-clock"; | |
| 181 | clock-frequency = <19200000>; | |
| 182 | }; | |
| 183 | ||
| 184 | virt_26000000_ck: virt_26000000_ck { | |
| 185 | #clock-cells = <0>; | |
| 186 | compatible = "fixed-clock"; | |
| 187 | clock-frequency = <26000000>; | |
| 188 | }; | |
| 189 | ||
| 190 | virt_38_4m_ck: virt_38_4m_ck { | |
| 191 | #clock-cells = <0>; | |
| 192 | compatible = "fixed-clock"; | |
| 193 | clock-frequency = <38400000>; | |
| 194 | }; | |
| 195 | ||
| 196 | dpll4_ck: dpll4_ck { | |
| 197 | #clock-cells = <0>; | |
| 198 | compatible = "ti,omap3-dpll-per-clock"; | |
| 199 | clocks = <&sys_ck>, <&sys_ck>; | |
| 200 | reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; | |
| 201 | }; | |
| 202 | ||
| 203 | dpll4_m2_ck: dpll4_m2_ck { | |
| 204 | #clock-cells = <0>; | |
| 205 | compatible = "ti,divider-clock"; | |
| 206 | clocks = <&dpll4_ck>; | |
| 207 | ti,max-div = <63>; | |
| 208 | reg = <0x0d48>; | |
| 209 | ti,index-starts-at-one; | |
| 210 | }; | |
| 211 | ||
| 212 | dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { | |
| 213 | #clock-cells = <0>; | |
| 214 | compatible = "fixed-factor-clock"; | |
| 215 | clocks = <&dpll4_m2_ck>; | |
| 216 | clock-mult = <2>; | |
| 217 | clock-div = <1>; | |
| 218 | }; | |
| 219 | ||
| 220 | dpll4_m2x2_ck: dpll4_m2x2_ck { | |
| 221 | #clock-cells = <0>; | |
| 222 | compatible = "ti,gate-clock"; | |
| 223 | clocks = <&dpll4_m2x2_mul_ck>; | |
| 224 | ti,bit-shift = <0x1b>; | |
| 225 | reg = <0x0d00>; | |
| 226 | ti,set-bit-to-disable; | |
| 227 | }; | |
| 228 | ||
| 229 | omap_96m_alwon_fck: omap_96m_alwon_fck { | |
| 230 | #clock-cells = <0>; | |
| 231 | compatible = "fixed-factor-clock"; | |
| 232 | clocks = <&dpll4_m2x2_ck>; | |
| 233 | clock-mult = <1>; | |
| 234 | clock-div = <1>; | |
| 235 | }; | |
| 236 | ||
| 237 | dpll3_ck: dpll3_ck { | |
| 238 | #clock-cells = <0>; | |
| 239 | compatible = "ti,omap3-dpll-core-clock"; | |
| 240 | clocks = <&sys_ck>, <&sys_ck>; | |
| 241 | reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; | |
| 242 | }; | |
| 243 | ||
| 244 | dpll3_m3_ck: dpll3_m3_ck { | |
| 245 | #clock-cells = <0>; | |
| 246 | compatible = "ti,divider-clock"; | |
| 247 | clocks = <&dpll3_ck>; | |
| 248 | ti,bit-shift = <16>; | |
| 249 | ti,max-div = <31>; | |
| 250 | reg = <0x1140>; | |
| 251 | ti,index-starts-at-one; | |
| 252 | }; | |
| 253 | ||
| 254 | dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { | |
| 255 | #clock-cells = <0>; | |
| 256 | compatible = "fixed-factor-clock"; | |
| 257 | clocks = <&dpll3_m3_ck>; | |
| 258 | clock-mult = <2>; | |
| 259 | clock-div = <1>; | |
| 260 | }; | |
| 261 | ||
| 262 | dpll3_m3x2_ck: dpll3_m3x2_ck { | |
| 263 | #clock-cells = <0>; | |
| 264 | compatible = "ti,gate-clock"; | |
| 265 | clocks = <&dpll3_m3x2_mul_ck>; | |
| 266 | ti,bit-shift = <0xc>; | |
| 267 | reg = <0x0d00>; | |
| 268 | ti,set-bit-to-disable; | |
| 269 | }; | |
| 270 | ||
| 271 | emu_core_alwon_ck: emu_core_alwon_ck { | |
| 272 | #clock-cells = <0>; | |
| 273 | compatible = "fixed-factor-clock"; | |
| 274 | clocks = <&dpll3_m3x2_ck>; | |
| 275 | clock-mult = <1>; | |
| 276 | clock-div = <1>; | |
| 277 | }; | |
| 278 | ||
| 279 | sys_altclk: sys_altclk { | |
| 280 | #clock-cells = <0>; | |
| 281 | compatible = "fixed-clock"; | |
| 282 | clock-frequency = <0x0>; | |
| 283 | }; | |
| 284 | ||
| 285 | mcbsp_clks: mcbsp_clks { | |
| 286 | #clock-cells = <0>; | |
| 287 | compatible = "fixed-clock"; | |
| 288 | clock-frequency = <0x0>; | |
| 289 | }; | |
| 290 | ||
| 291 | dpll3_m2_ck: dpll3_m2_ck { | |
| 292 | #clock-cells = <0>; | |
| 293 | compatible = "ti,divider-clock"; | |
| 294 | clocks = <&dpll3_ck>; | |
| 295 | ti,bit-shift = <27>; | |
| 296 | ti,max-div = <31>; | |
| 297 | reg = <0x0d40>; | |
| 298 | ti,index-starts-at-one; | |
| 299 | }; | |
| 300 | ||
| 301 | core_ck: core_ck { | |
| 302 | #clock-cells = <0>; | |
| 303 | compatible = "fixed-factor-clock"; | |
| 304 | clocks = <&dpll3_m2_ck>; | |
| 305 | clock-mult = <1>; | |
| 306 | clock-div = <1>; | |
| 307 | }; | |
| 308 | ||
| 309 | dpll1_fck: dpll1_fck { | |
| 310 | #clock-cells = <0>; | |
| 311 | compatible = "ti,divider-clock"; | |
| 312 | clocks = <&core_ck>; | |
| 313 | ti,bit-shift = <19>; | |
| 314 | ti,max-div = <7>; | |
| 315 | reg = <0x0940>; | |
| 316 | ti,index-starts-at-one; | |
| 317 | }; | |
| 318 | ||
| 319 | dpll1_ck: dpll1_ck { | |
| 320 | #clock-cells = <0>; | |
| 321 | compatible = "ti,omap3-dpll-clock"; | |
| 322 | clocks = <&sys_ck>, <&dpll1_fck>; | |
| 323 | reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>; | |
| 324 | }; | |
| 325 | ||
| 326 | dpll1_x2_ck: dpll1_x2_ck { | |
| 327 | #clock-cells = <0>; | |
| 328 | compatible = "fixed-factor-clock"; | |
| 329 | clocks = <&dpll1_ck>; | |
| 330 | clock-mult = <2>; | |
| 331 | clock-div = <1>; | |
| 332 | }; | |
| 333 | ||
| 334 | dpll1_x2m2_ck: dpll1_x2m2_ck { | |
| 335 | #clock-cells = <0>; | |
| 336 | compatible = "ti,divider-clock"; | |
| 337 | clocks = <&dpll1_x2_ck>; | |
| 338 | ti,max-div = <31>; | |
| 339 | reg = <0x0944>; | |
| 340 | ti,index-starts-at-one; | |
| 341 | }; | |
| 342 | ||
| 343 | cm_96m_fck: cm_96m_fck { | |
| 344 | #clock-cells = <0>; | |
| 345 | compatible = "fixed-factor-clock"; | |
| 346 | clocks = <&omap_96m_alwon_fck>; | |
| 347 | clock-mult = <1>; | |
| 348 | clock-div = <1>; | |
| 349 | }; | |
| 350 | ||
| 351 | omap_96m_fck: omap_96m_fck { | |
| 352 | #clock-cells = <0>; | |
| 353 | compatible = "ti,mux-clock"; | |
| 354 | clocks = <&cm_96m_fck>, <&sys_ck>; | |
| 355 | ti,bit-shift = <6>; | |
| 356 | reg = <0x0d40>; | |
| 357 | }; | |
| 358 | ||
| 359 | dpll4_m3_ck: dpll4_m3_ck { | |
| 360 | #clock-cells = <0>; | |
| 361 | compatible = "ti,divider-clock"; | |
| 362 | clocks = <&dpll4_ck>; | |
| 363 | ti,bit-shift = <8>; | |
| 364 | ti,max-div = <32>; | |
| 365 | reg = <0x0e40>; | |
| 366 | ti,index-starts-at-one; | |
| 367 | }; | |
| 368 | ||
| 369 | dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { | |
| 370 | #clock-cells = <0>; | |
| 371 | compatible = "fixed-factor-clock"; | |
| 372 | clocks = <&dpll4_m3_ck>; | |
| 373 | clock-mult = <2>; | |
| 374 | clock-div = <1>; | |
| 375 | }; | |
| 376 | ||
| 377 | dpll4_m3x2_ck: dpll4_m3x2_ck { | |
| 378 | #clock-cells = <0>; | |
| 379 | compatible = "ti,gate-clock"; | |
| 380 | clocks = <&dpll4_m3x2_mul_ck>; | |
| 381 | ti,bit-shift = <0x1c>; | |
| 382 | reg = <0x0d00>; | |
| 383 | ti,set-bit-to-disable; | |
| 384 | }; | |
| 385 | ||
| 386 | omap_54m_fck: omap_54m_fck { | |
| 387 | #clock-cells = <0>; | |
| 388 | compatible = "ti,mux-clock"; | |
| 389 | clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; | |
| 390 | ti,bit-shift = <5>; | |
| 391 | reg = <0x0d40>; | |
| 392 | }; | |
| 393 | ||
| 394 | cm_96m_d2_fck: cm_96m_d2_fck { | |
| 395 | #clock-cells = <0>; | |
| 396 | compatible = "fixed-factor-clock"; | |
| 397 | clocks = <&cm_96m_fck>; | |
| 398 | clock-mult = <1>; | |
| 399 | clock-div = <2>; | |
| 400 | }; | |
| 401 | ||
| 402 | omap_48m_fck: omap_48m_fck { | |
| 403 | #clock-cells = <0>; | |
| 404 | compatible = "ti,mux-clock"; | |
| 405 | clocks = <&cm_96m_d2_fck>, <&sys_altclk>; | |
| 406 | ti,bit-shift = <3>; | |
| 407 | reg = <0x0d40>; | |
| 408 | }; | |
| 409 | ||
| 410 | omap_12m_fck: omap_12m_fck { | |
| 411 | #clock-cells = <0>; | |
| 412 | compatible = "fixed-factor-clock"; | |
| 413 | clocks = <&omap_48m_fck>; | |
| 414 | clock-mult = <1>; | |
| 415 | clock-div = <4>; | |
| 416 | }; | |
| 417 | ||
| 418 | dpll4_m4_ck: dpll4_m4_ck { | |
| 419 | #clock-cells = <0>; | |
| 420 | compatible = "ti,divider-clock"; | |
| 421 | clocks = <&dpll4_ck>; | |
| 422 | ti,max-div = <32>; | |
| 423 | reg = <0x0e40>; | |
| 424 | ti,index-starts-at-one; | |
| 425 | }; | |
| 426 | ||
| 427 | dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { | |
| 428 | #clock-cells = <0>; | |
| c368dbe2 | 429 | compatible = "ti,fixed-factor-clock"; |
| 657fc11c | 430 | clocks = <&dpll4_m4_ck>; |
| c368dbe2 TV |
431 | ti,clock-mult = <2>; |
| 432 | ti,clock-div = <1>; | |
| 1d3361f6 | 433 | ti,set-rate-parent; |
| 657fc11c TK |
434 | }; |
| 435 | ||
| 436 | dpll4_m4x2_ck: dpll4_m4x2_ck { | |
| 437 | #clock-cells = <0>; | |
| 438 | compatible = "ti,gate-clock"; | |
| 439 | clocks = <&dpll4_m4x2_mul_ck>; | |
| 440 | ti,bit-shift = <0x1d>; | |
| 441 | reg = <0x0d00>; | |
| 442 | ti,set-bit-to-disable; | |
| 1d3361f6 | 443 | ti,set-rate-parent; |
| 657fc11c TK |
444 | }; |
| 445 | ||
| 446 | dpll4_m5_ck: dpll4_m5_ck { | |
| 447 | #clock-cells = <0>; | |
| 448 | compatible = "ti,divider-clock"; | |
| 449 | clocks = <&dpll4_ck>; | |
| 450 | ti,max-div = <63>; | |
| 451 | reg = <0x0f40>; | |
| 452 | ti,index-starts-at-one; | |
| 453 | }; | |
| 454 | ||
| 455 | dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { | |
| 456 | #clock-cells = <0>; | |
| e21a4ea3 | 457 | compatible = "ti,fixed-factor-clock"; |
| 657fc11c | 458 | clocks = <&dpll4_m5_ck>; |
| e21a4ea3 LP |
459 | ti,clock-mult = <2>; |
| 460 | ti,clock-div = <1>; | |
| 2febd999 | 461 | ti,set-rate-parent; |
| 657fc11c TK |
462 | }; |
| 463 | ||
| 464 | dpll4_m5x2_ck: dpll4_m5x2_ck { | |
| 465 | #clock-cells = <0>; | |
| 466 | compatible = "ti,gate-clock"; | |
| 467 | clocks = <&dpll4_m5x2_mul_ck>; | |
| 468 | ti,bit-shift = <0x1e>; | |
| 469 | reg = <0x0d00>; | |
| 470 | ti,set-bit-to-disable; | |
| adf5b4dc | 471 | ti,set-rate-parent; |
| 657fc11c TK |
472 | }; |
| 473 | ||
| 474 | dpll4_m6_ck: dpll4_m6_ck { | |
| 475 | #clock-cells = <0>; | |
| 476 | compatible = "ti,divider-clock"; | |
| 477 | clocks = <&dpll4_ck>; | |
| 478 | ti,bit-shift = <24>; | |
| 479 | ti,max-div = <63>; | |
| 480 | reg = <0x1140>; | |
| 481 | ti,index-starts-at-one; | |
| 482 | }; | |
| 483 | ||
| 484 | dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { | |
| 485 | #clock-cells = <0>; | |
| 486 | compatible = "fixed-factor-clock"; | |
| 487 | clocks = <&dpll4_m6_ck>; | |
| 488 | clock-mult = <2>; | |
| 489 | clock-div = <1>; | |
| 490 | }; | |
| 491 | ||
| 492 | dpll4_m6x2_ck: dpll4_m6x2_ck { | |
| 493 | #clock-cells = <0>; | |
| 494 | compatible = "ti,gate-clock"; | |
| 495 | clocks = <&dpll4_m6x2_mul_ck>; | |
| 496 | ti,bit-shift = <0x1f>; | |
| 497 | reg = <0x0d00>; | |
| 498 | ti,set-bit-to-disable; | |
| 499 | }; | |
| 500 | ||
| 501 | emu_per_alwon_ck: emu_per_alwon_ck { | |
| 502 | #clock-cells = <0>; | |
| 503 | compatible = "fixed-factor-clock"; | |
| 504 | clocks = <&dpll4_m6x2_ck>; | |
| 505 | clock-mult = <1>; | |
| 506 | clock-div = <1>; | |
| 507 | }; | |
| 508 | ||
| 509 | clkout2_src_gate_ck: clkout2_src_gate_ck { | |
| 510 | #clock-cells = <0>; | |
| 511 | compatible = "ti,composite-no-wait-gate-clock"; | |
| 512 | clocks = <&core_ck>; | |
| 513 | ti,bit-shift = <7>; | |
| 514 | reg = <0x0d70>; | |
| 515 | }; | |
| 516 | ||
| 517 | clkout2_src_mux_ck: clkout2_src_mux_ck { | |
| 518 | #clock-cells = <0>; | |
| 519 | compatible = "ti,composite-mux-clock"; | |
| 520 | clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; | |
| 521 | reg = <0x0d70>; | |
| 522 | }; | |
| 523 | ||
| 524 | clkout2_src_ck: clkout2_src_ck { | |
| 525 | #clock-cells = <0>; | |
| 526 | compatible = "ti,composite-clock"; | |
| 527 | clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; | |
| 528 | }; | |
| 529 | ||
| 530 | sys_clkout2: sys_clkout2 { | |
| 531 | #clock-cells = <0>; | |
| 532 | compatible = "ti,divider-clock"; | |
| 533 | clocks = <&clkout2_src_ck>; | |
| 534 | ti,bit-shift = <3>; | |
| 535 | ti,max-div = <64>; | |
| 536 | reg = <0x0d70>; | |
| 537 | ti,index-power-of-two; | |
| 538 | }; | |
| 539 | ||
| 540 | mpu_ck: mpu_ck { | |
| 541 | #clock-cells = <0>; | |
| 542 | compatible = "fixed-factor-clock"; | |
| 543 | clocks = <&dpll1_x2m2_ck>; | |
| 544 | clock-mult = <1>; | |
| 545 | clock-div = <1>; | |
| 546 | }; | |
| 547 | ||
| 548 | arm_fck: arm_fck { | |
| 549 | #clock-cells = <0>; | |
| 550 | compatible = "ti,divider-clock"; | |
| 551 | clocks = <&mpu_ck>; | |
| 552 | reg = <0x0924>; | |
| 553 | ti,max-div = <2>; | |
| 554 | }; | |
| 555 | ||
| 556 | emu_mpu_alwon_ck: emu_mpu_alwon_ck { | |
| 557 | #clock-cells = <0>; | |
| 558 | compatible = "fixed-factor-clock"; | |
| 559 | clocks = <&mpu_ck>; | |
| 560 | clock-mult = <1>; | |
| 561 | clock-div = <1>; | |
| 562 | }; | |
| 563 | ||
| 564 | l3_ick: l3_ick { | |
| 565 | #clock-cells = <0>; | |
| 566 | compatible = "ti,divider-clock"; | |
| 567 | clocks = <&core_ck>; | |
| 568 | ti,max-div = <3>; | |
| 569 | reg = <0x0a40>; | |
| 570 | ti,index-starts-at-one; | |
| 571 | }; | |
| 572 | ||
| 573 | l4_ick: l4_ick { | |
| 574 | #clock-cells = <0>; | |
| 575 | compatible = "ti,divider-clock"; | |
| 576 | clocks = <&l3_ick>; | |
| 577 | ti,bit-shift = <2>; | |
| 578 | ti,max-div = <3>; | |
| 579 | reg = <0x0a40>; | |
| 580 | ti,index-starts-at-one; | |
| 581 | }; | |
| 582 | ||
| 583 | rm_ick: rm_ick { | |
| 584 | #clock-cells = <0>; | |
| 585 | compatible = "ti,divider-clock"; | |
| 586 | clocks = <&l4_ick>; | |
| 587 | ti,bit-shift = <1>; | |
| 588 | ti,max-div = <3>; | |
| 589 | reg = <0x0c40>; | |
| 590 | ti,index-starts-at-one; | |
| 591 | }; | |
| 592 | ||
| 593 | gpt10_gate_fck: gpt10_gate_fck { | |
| 594 | #clock-cells = <0>; | |
| 595 | compatible = "ti,composite-gate-clock"; | |
| 596 | clocks = <&sys_ck>; | |
| 597 | ti,bit-shift = <11>; | |
| 598 | reg = <0x0a00>; | |
| 599 | }; | |
| 600 | ||
| 601 | gpt10_mux_fck: gpt10_mux_fck { | |
| 602 | #clock-cells = <0>; | |
| 603 | compatible = "ti,composite-mux-clock"; | |
| 604 | clocks = <&omap_32k_fck>, <&sys_ck>; | |
| 605 | ti,bit-shift = <6>; | |
| 606 | reg = <0x0a40>; | |
| 607 | }; | |
| 608 | ||
| 609 | gpt10_fck: gpt10_fck { | |
| 610 | #clock-cells = <0>; | |
| 611 | compatible = "ti,composite-clock"; | |
| 612 | clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; | |
| 613 | }; | |
| 614 | ||
| 615 | gpt11_gate_fck: gpt11_gate_fck { | |
| 616 | #clock-cells = <0>; | |
| 617 | compatible = "ti,composite-gate-clock"; | |
| 618 | clocks = <&sys_ck>; | |
| 619 | ti,bit-shift = <12>; | |
| 620 | reg = <0x0a00>; | |
| 621 | }; | |
| 622 | ||
| 623 | gpt11_mux_fck: gpt11_mux_fck { | |
| 624 | #clock-cells = <0>; | |
| 625 | compatible = "ti,composite-mux-clock"; | |
| 626 | clocks = <&omap_32k_fck>, <&sys_ck>; | |
| 627 | ti,bit-shift = <7>; | |
| 628 | reg = <0x0a40>; | |
| 629 | }; | |
| 630 | ||
| 631 | gpt11_fck: gpt11_fck { | |
| 632 | #clock-cells = <0>; | |
| 633 | compatible = "ti,composite-clock"; | |
| 634 | clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; | |
| 635 | }; | |
| 636 | ||
| 637 | core_96m_fck: core_96m_fck { | |
| 638 | #clock-cells = <0>; | |
| 639 | compatible = "fixed-factor-clock"; | |
| 640 | clocks = <&omap_96m_fck>; | |
| 641 | clock-mult = <1>; | |
| 642 | clock-div = <1>; | |
| 643 | }; | |
| 644 | ||
| 645 | mmchs2_fck: mmchs2_fck { | |
| 646 | #clock-cells = <0>; | |
| 647 | compatible = "ti,wait-gate-clock"; | |
| 648 | clocks = <&core_96m_fck>; | |
| 649 | reg = <0x0a00>; | |
| 650 | ti,bit-shift = <25>; | |
| 651 | }; | |
| 652 | ||
| 653 | mmchs1_fck: mmchs1_fck { | |
| 654 | #clock-cells = <0>; | |
| 655 | compatible = "ti,wait-gate-clock"; | |
| 656 | clocks = <&core_96m_fck>; | |
| 657 | reg = <0x0a00>; | |
| 658 | ti,bit-shift = <24>; | |
| 659 | }; | |
| 660 | ||
| 661 | i2c3_fck: i2c3_fck { | |
| 662 | #clock-cells = <0>; | |
| 663 | compatible = "ti,wait-gate-clock"; | |
| 664 | clocks = <&core_96m_fck>; | |
| 665 | reg = <0x0a00>; | |
| 666 | ti,bit-shift = <17>; | |
| 667 | }; | |
| 668 | ||
| 669 | i2c2_fck: i2c2_fck { | |
| 670 | #clock-cells = <0>; | |
| 671 | compatible = "ti,wait-gate-clock"; | |
| 672 | clocks = <&core_96m_fck>; | |
| 673 | reg = <0x0a00>; | |
| 674 | ti,bit-shift = <16>; | |
| 675 | }; | |
| 676 | ||
| 677 | i2c1_fck: i2c1_fck { | |
| 678 | #clock-cells = <0>; | |
| 679 | compatible = "ti,wait-gate-clock"; | |
| 680 | clocks = <&core_96m_fck>; | |
| 681 | reg = <0x0a00>; | |
| 682 | ti,bit-shift = <15>; | |
| 683 | }; | |
| 684 | ||
| 685 | mcbsp5_gate_fck: mcbsp5_gate_fck { | |
| 686 | #clock-cells = <0>; | |
| 687 | compatible = "ti,composite-gate-clock"; | |
| 688 | clocks = <&mcbsp_clks>; | |
| 689 | ti,bit-shift = <10>; | |
| 690 | reg = <0x0a00>; | |
| 691 | }; | |
| 692 | ||
| 693 | mcbsp1_gate_fck: mcbsp1_gate_fck { | |
| 694 | #clock-cells = <0>; | |
| 695 | compatible = "ti,composite-gate-clock"; | |
| 696 | clocks = <&mcbsp_clks>; | |
| 697 | ti,bit-shift = <9>; | |
| 698 | reg = <0x0a00>; | |
| 699 | }; | |
| 700 | ||
| 701 | core_48m_fck: core_48m_fck { | |
| 702 | #clock-cells = <0>; | |
| 703 | compatible = "fixed-factor-clock"; | |
| 704 | clocks = <&omap_48m_fck>; | |
| 705 | clock-mult = <1>; | |
| 706 | clock-div = <1>; | |
| 707 | }; | |
| 708 | ||
| 709 | mcspi4_fck: mcspi4_fck { | |
| 710 | #clock-cells = <0>; | |
| 711 | compatible = "ti,wait-gate-clock"; | |
| 712 | clocks = <&core_48m_fck>; | |
| 713 | reg = <0x0a00>; | |
| 714 | ti,bit-shift = <21>; | |
| 715 | }; | |
| 716 | ||
| 717 | mcspi3_fck: mcspi3_fck { | |
| 718 | #clock-cells = <0>; | |
| 719 | compatible = "ti,wait-gate-clock"; | |
| 720 | clocks = <&core_48m_fck>; | |
| 721 | reg = <0x0a00>; | |
| 722 | ti,bit-shift = <20>; | |
| 723 | }; | |
| 724 | ||
| 725 | mcspi2_fck: mcspi2_fck { | |
| 726 | #clock-cells = <0>; | |
| 727 | compatible = "ti,wait-gate-clock"; | |
| 728 | clocks = <&core_48m_fck>; | |
| 729 | reg = <0x0a00>; | |
| 730 | ti,bit-shift = <19>; | |
| 731 | }; | |
| 732 | ||
| 733 | mcspi1_fck: mcspi1_fck { | |
| 734 | #clock-cells = <0>; | |
| 735 | compatible = "ti,wait-gate-clock"; | |
| 736 | clocks = <&core_48m_fck>; | |
| 737 | reg = <0x0a00>; | |
| 738 | ti,bit-shift = <18>; | |
| 739 | }; | |
| 740 | ||
| 741 | uart2_fck: uart2_fck { | |
| 742 | #clock-cells = <0>; | |
| 743 | compatible = "ti,wait-gate-clock"; | |
| 744 | clocks = <&core_48m_fck>; | |
| 745 | reg = <0x0a00>; | |
| 746 | ti,bit-shift = <14>; | |
| 747 | }; | |
| 748 | ||
| 749 | uart1_fck: uart1_fck { | |
| 750 | #clock-cells = <0>; | |
| 751 | compatible = "ti,wait-gate-clock"; | |
| 752 | clocks = <&core_48m_fck>; | |
| 753 | reg = <0x0a00>; | |
| 754 | ti,bit-shift = <13>; | |
| 755 | }; | |
| 756 | ||
| 757 | core_12m_fck: core_12m_fck { | |
| 758 | #clock-cells = <0>; | |
| 759 | compatible = "fixed-factor-clock"; | |
| 760 | clocks = <&omap_12m_fck>; | |
| 761 | clock-mult = <1>; | |
| 762 | clock-div = <1>; | |
| 763 | }; | |
| 764 | ||
| 765 | hdq_fck: hdq_fck { | |
| 766 | #clock-cells = <0>; | |
| 767 | compatible = "ti,wait-gate-clock"; | |
| 768 | clocks = <&core_12m_fck>; | |
| 769 | reg = <0x0a00>; | |
| 770 | ti,bit-shift = <22>; | |
| 771 | }; | |
| 772 | ||
| 773 | core_l3_ick: core_l3_ick { | |
| 774 | #clock-cells = <0>; | |
| 775 | compatible = "fixed-factor-clock"; | |
| 776 | clocks = <&l3_ick>; | |
| 777 | clock-mult = <1>; | |
| 778 | clock-div = <1>; | |
| 779 | }; | |
| 780 | ||
| 781 | sdrc_ick: sdrc_ick { | |
| 782 | #clock-cells = <0>; | |
| 783 | compatible = "ti,wait-gate-clock"; | |
| 784 | clocks = <&core_l3_ick>; | |
| 785 | reg = <0x0a10>; | |
| 786 | ti,bit-shift = <1>; | |
| 787 | }; | |
| 788 | ||
| 789 | gpmc_fck: gpmc_fck { | |
| 790 | #clock-cells = <0>; | |
| 791 | compatible = "fixed-factor-clock"; | |
| 792 | clocks = <&core_l3_ick>; | |
| 793 | clock-mult = <1>; | |
| 794 | clock-div = <1>; | |
| 795 | }; | |
| 796 | ||
| 797 | core_l4_ick: core_l4_ick { | |
| 798 | #clock-cells = <0>; | |
| 799 | compatible = "fixed-factor-clock"; | |
| 800 | clocks = <&l4_ick>; | |
| 801 | clock-mult = <1>; | |
| 802 | clock-div = <1>; | |
| 803 | }; | |
| 804 | ||
| 805 | mmchs2_ick: mmchs2_ick { | |
| 806 | #clock-cells = <0>; | |
| 807 | compatible = "ti,omap3-interface-clock"; | |
| 808 | clocks = <&core_l4_ick>; | |
| 809 | reg = <0x0a10>; | |
| 810 | ti,bit-shift = <25>; | |
| 811 | }; | |
| 812 | ||
| 813 | mmchs1_ick: mmchs1_ick { | |
| 814 | #clock-cells = <0>; | |
| 815 | compatible = "ti,omap3-interface-clock"; | |
| 816 | clocks = <&core_l4_ick>; | |
| 817 | reg = <0x0a10>; | |
| 818 | ti,bit-shift = <24>; | |
| 819 | }; | |
| 820 | ||
| 821 | hdq_ick: hdq_ick { | |
| 822 | #clock-cells = <0>; | |
| 823 | compatible = "ti,omap3-interface-clock"; | |
| 824 | clocks = <&core_l4_ick>; | |
| 825 | reg = <0x0a10>; | |
| 826 | ti,bit-shift = <22>; | |
| 827 | }; | |
| 828 | ||
| 829 | mcspi4_ick: mcspi4_ick { | |
| 830 | #clock-cells = <0>; | |
| 831 | compatible = "ti,omap3-interface-clock"; | |
| 832 | clocks = <&core_l4_ick>; | |
| 833 | reg = <0x0a10>; | |
| 834 | ti,bit-shift = <21>; | |
| 835 | }; | |
| 836 | ||
| 837 | mcspi3_ick: mcspi3_ick { | |
| 838 | #clock-cells = <0>; | |
| 839 | compatible = "ti,omap3-interface-clock"; | |
| 840 | clocks = <&core_l4_ick>; | |
| 841 | reg = <0x0a10>; | |
| 842 | ti,bit-shift = <20>; | |
| 843 | }; | |
| 844 | ||
| 845 | mcspi2_ick: mcspi2_ick { | |
| 846 | #clock-cells = <0>; | |
| 847 | compatible = "ti,omap3-interface-clock"; | |
| 848 | clocks = <&core_l4_ick>; | |
| 849 | reg = <0x0a10>; | |
| 850 | ti,bit-shift = <19>; | |
| 851 | }; | |
| 852 | ||
| 853 | mcspi1_ick: mcspi1_ick { | |
| 854 | #clock-cells = <0>; | |
| 855 | compatible = "ti,omap3-interface-clock"; | |
| 856 | clocks = <&core_l4_ick>; | |
| 857 | reg = <0x0a10>; | |
| 858 | ti,bit-shift = <18>; | |
| 859 | }; | |
| 860 | ||
| 861 | i2c3_ick: i2c3_ick { | |
| 862 | #clock-cells = <0>; | |
| 863 | compatible = "ti,omap3-interface-clock"; | |
| 864 | clocks = <&core_l4_ick>; | |
| 865 | reg = <0x0a10>; | |
| 866 | ti,bit-shift = <17>; | |
| 867 | }; | |
| 868 | ||
| 869 | i2c2_ick: i2c2_ick { | |
| 870 | #clock-cells = <0>; | |
| 871 | compatible = "ti,omap3-interface-clock"; | |
| 872 | clocks = <&core_l4_ick>; | |
| 873 | reg = <0x0a10>; | |
| 874 | ti,bit-shift = <16>; | |
| 875 | }; | |
| 876 | ||
| 877 | i2c1_ick: i2c1_ick { | |
| 878 | #clock-cells = <0>; | |
| 879 | compatible = "ti,omap3-interface-clock"; | |
| 880 | clocks = <&core_l4_ick>; | |
| 881 | reg = <0x0a10>; | |
| 882 | ti,bit-shift = <15>; | |
| 883 | }; | |
| 884 | ||
| 885 | uart2_ick: uart2_ick { | |
| 886 | #clock-cells = <0>; | |
| 887 | compatible = "ti,omap3-interface-clock"; | |
| 888 | clocks = <&core_l4_ick>; | |
| 889 | reg = <0x0a10>; | |
| 890 | ti,bit-shift = <14>; | |
| 891 | }; | |
| 892 | ||
| 893 | uart1_ick: uart1_ick { | |
| 894 | #clock-cells = <0>; | |
| 895 | compatible = "ti,omap3-interface-clock"; | |
| 896 | clocks = <&core_l4_ick>; | |
| 897 | reg = <0x0a10>; | |
| 898 | ti,bit-shift = <13>; | |
| 899 | }; | |
| 900 | ||
| 901 | gpt11_ick: gpt11_ick { | |
| 902 | #clock-cells = <0>; | |
| 903 | compatible = "ti,omap3-interface-clock"; | |
| 904 | clocks = <&core_l4_ick>; | |
| 905 | reg = <0x0a10>; | |
| 906 | ti,bit-shift = <12>; | |
| 907 | }; | |
| 908 | ||
| 909 | gpt10_ick: gpt10_ick { | |
| 910 | #clock-cells = <0>; | |
| 911 | compatible = "ti,omap3-interface-clock"; | |
| 912 | clocks = <&core_l4_ick>; | |
| 913 | reg = <0x0a10>; | |
| 914 | ti,bit-shift = <11>; | |
| 915 | }; | |
| 916 | ||
| 917 | mcbsp5_ick: mcbsp5_ick { | |
| 918 | #clock-cells = <0>; | |
| 919 | compatible = "ti,omap3-interface-clock"; | |
| 920 | clocks = <&core_l4_ick>; | |
| 921 | reg = <0x0a10>; | |
| 922 | ti,bit-shift = <10>; | |
| 923 | }; | |
| 924 | ||
| 925 | mcbsp1_ick: mcbsp1_ick { | |
| 926 | #clock-cells = <0>; | |
| 927 | compatible = "ti,omap3-interface-clock"; | |
| 928 | clocks = <&core_l4_ick>; | |
| 929 | reg = <0x0a10>; | |
| 930 | ti,bit-shift = <9>; | |
| 931 | }; | |
| 932 | ||
| 933 | omapctrl_ick: omapctrl_ick { | |
| 934 | #clock-cells = <0>; | |
| 935 | compatible = "ti,omap3-interface-clock"; | |
| 936 | clocks = <&core_l4_ick>; | |
| 937 | reg = <0x0a10>; | |
| 938 | ti,bit-shift = <6>; | |
| 939 | }; | |
| 940 | ||
| 941 | dss_tv_fck: dss_tv_fck { | |
| 942 | #clock-cells = <0>; | |
| 943 | compatible = "ti,gate-clock"; | |
| 944 | clocks = <&omap_54m_fck>; | |
| 945 | reg = <0x0e00>; | |
| 946 | ti,bit-shift = <2>; | |
| 947 | }; | |
| 948 | ||
| 949 | dss_96m_fck: dss_96m_fck { | |
| 950 | #clock-cells = <0>; | |
| 951 | compatible = "ti,gate-clock"; | |
| 952 | clocks = <&omap_96m_fck>; | |
| 953 | reg = <0x0e00>; | |
| 954 | ti,bit-shift = <2>; | |
| 955 | }; | |
| 956 | ||
| 957 | dss2_alwon_fck: dss2_alwon_fck { | |
| 958 | #clock-cells = <0>; | |
| 959 | compatible = "ti,gate-clock"; | |
| 960 | clocks = <&sys_ck>; | |
| 961 | reg = <0x0e00>; | |
| 962 | ti,bit-shift = <1>; | |
| 963 | }; | |
| 964 | ||
| 965 | dummy_ck: dummy_ck { | |
| 966 | #clock-cells = <0>; | |
| 967 | compatible = "fixed-clock"; | |
| 968 | clock-frequency = <0>; | |
| 969 | }; | |
| 970 | ||
| 971 | gpt1_gate_fck: gpt1_gate_fck { | |
| 972 | #clock-cells = <0>; | |
| 973 | compatible = "ti,composite-gate-clock"; | |
| 974 | clocks = <&sys_ck>; | |
| 975 | ti,bit-shift = <0>; | |
| 976 | reg = <0x0c00>; | |
| 977 | }; | |
| 978 | ||
| 979 | gpt1_mux_fck: gpt1_mux_fck { | |
| 980 | #clock-cells = <0>; | |
| 981 | compatible = "ti,composite-mux-clock"; | |
| 982 | clocks = <&omap_32k_fck>, <&sys_ck>; | |
| 983 | reg = <0x0c40>; | |
| 984 | }; | |
| 985 | ||
| 986 | gpt1_fck: gpt1_fck { | |
| 987 | #clock-cells = <0>; | |
| 988 | compatible = "ti,composite-clock"; | |
| 989 | clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; | |
| 990 | }; | |
| 991 | ||
| 992 | aes2_ick: aes2_ick { | |
| 993 | #clock-cells = <0>; | |
| 994 | compatible = "ti,omap3-interface-clock"; | |
| 995 | clocks = <&core_l4_ick>; | |
| 996 | ti,bit-shift = <28>; | |
| 997 | reg = <0x0a10>; | |
| 998 | }; | |
| 999 | ||
| 1000 | wkup_32k_fck: wkup_32k_fck { | |
| 1001 | #clock-cells = <0>; | |
| 1002 | compatible = "fixed-factor-clock"; | |
| 1003 | clocks = <&omap_32k_fck>; | |
| 1004 | clock-mult = <1>; | |
| 1005 | clock-div = <1>; | |
| 1006 | }; | |
| 1007 | ||
| 1008 | gpio1_dbck: gpio1_dbck { | |
| 1009 | #clock-cells = <0>; | |
| 1010 | compatible = "ti,gate-clock"; | |
| 1011 | clocks = <&wkup_32k_fck>; | |
| 1012 | reg = <0x0c00>; | |
| 1013 | ti,bit-shift = <3>; | |
| 1014 | }; | |
| 1015 | ||
| 1016 | sha12_ick: sha12_ick { | |
| 1017 | #clock-cells = <0>; | |
| 1018 | compatible = "ti,omap3-interface-clock"; | |
| 1019 | clocks = <&core_l4_ick>; | |
| 1020 | reg = <0x0a10>; | |
| 1021 | ti,bit-shift = <27>; | |
| 1022 | }; | |
| 1023 | ||
| 1024 | wdt2_fck: wdt2_fck { | |
| 1025 | #clock-cells = <0>; | |
| 1026 | compatible = "ti,wait-gate-clock"; | |
| 1027 | clocks = <&wkup_32k_fck>; | |
| 1028 | reg = <0x0c00>; | |
| 1029 | ti,bit-shift = <5>; | |
| 1030 | }; | |
| 1031 | ||
| 1032 | wdt2_ick: wdt2_ick { | |
| 1033 | #clock-cells = <0>; | |
| 1034 | compatible = "ti,omap3-interface-clock"; | |
| 1035 | clocks = <&wkup_l4_ick>; | |
| 1036 | reg = <0x0c10>; | |
| 1037 | ti,bit-shift = <5>; | |
| 1038 | }; | |
| 1039 | ||
| 1040 | wdt1_ick: wdt1_ick { | |
| 1041 | #clock-cells = <0>; | |
| 1042 | compatible = "ti,omap3-interface-clock"; | |
| 1043 | clocks = <&wkup_l4_ick>; | |
| 1044 | reg = <0x0c10>; | |
| 1045 | ti,bit-shift = <4>; | |
| 1046 | }; | |
| 1047 | ||
| 1048 | gpio1_ick: gpio1_ick { | |
| 1049 | #clock-cells = <0>; | |
| 1050 | compatible = "ti,omap3-interface-clock"; | |
| 1051 | clocks = <&wkup_l4_ick>; | |
| 1052 | reg = <0x0c10>; | |
| 1053 | ti,bit-shift = <3>; | |
| 1054 | }; | |
| 1055 | ||
| 1056 | omap_32ksync_ick: omap_32ksync_ick { | |
| 1057 | #clock-cells = <0>; | |
| 1058 | compatible = "ti,omap3-interface-clock"; | |
| 1059 | clocks = <&wkup_l4_ick>; | |
| 1060 | reg = <0x0c10>; | |
| 1061 | ti,bit-shift = <2>; | |
| 1062 | }; | |
| 1063 | ||
| 1064 | gpt12_ick: gpt12_ick { | |
| 1065 | #clock-cells = <0>; | |
| 1066 | compatible = "ti,omap3-interface-clock"; | |
| 1067 | clocks = <&wkup_l4_ick>; | |
| 1068 | reg = <0x0c10>; | |
| 1069 | ti,bit-shift = <1>; | |
| 1070 | }; | |
| 1071 | ||
| 1072 | gpt1_ick: gpt1_ick { | |
| 1073 | #clock-cells = <0>; | |
| 1074 | compatible = "ti,omap3-interface-clock"; | |
| 1075 | clocks = <&wkup_l4_ick>; | |
| 1076 | reg = <0x0c10>; | |
| 1077 | ti,bit-shift = <0>; | |
| 1078 | }; | |
| 1079 | ||
| 1080 | per_96m_fck: per_96m_fck { | |
| 1081 | #clock-cells = <0>; | |
| 1082 | compatible = "fixed-factor-clock"; | |
| 1083 | clocks = <&omap_96m_alwon_fck>; | |
| 1084 | clock-mult = <1>; | |
| 1085 | clock-div = <1>; | |
| 1086 | }; | |
| 1087 | ||
| 1088 | per_48m_fck: per_48m_fck { | |
| 1089 | #clock-cells = <0>; | |
| 1090 | compatible = "fixed-factor-clock"; | |
| 1091 | clocks = <&omap_48m_fck>; | |
| 1092 | clock-mult = <1>; | |
| 1093 | clock-div = <1>; | |
| 1094 | }; | |
| 1095 | ||
| 1096 | uart3_fck: uart3_fck { | |
| 1097 | #clock-cells = <0>; | |
| 1098 | compatible = "ti,wait-gate-clock"; | |
| 1099 | clocks = <&per_48m_fck>; | |
| 1100 | reg = <0x1000>; | |
| 1101 | ti,bit-shift = <11>; | |
| 1102 | }; | |
| 1103 | ||
| 1104 | gpt2_gate_fck: gpt2_gate_fck { | |
| 1105 | #clock-cells = <0>; | |
| 1106 | compatible = "ti,composite-gate-clock"; | |
| 1107 | clocks = <&sys_ck>; | |
| 1108 | ti,bit-shift = <3>; | |
| 1109 | reg = <0x1000>; | |
| 1110 | }; | |
| 1111 | ||
| 1112 | gpt2_mux_fck: gpt2_mux_fck { | |
| 1113 | #clock-cells = <0>; | |
| 1114 | compatible = "ti,composite-mux-clock"; | |
| 1115 | clocks = <&omap_32k_fck>, <&sys_ck>; | |
| 1116 | reg = <0x1040>; | |
| 1117 | }; | |
| 1118 | ||
| 1119 | gpt2_fck: gpt2_fck { | |
| 1120 | #clock-cells = <0>; | |
| 1121 | compatible = "ti,composite-clock"; | |
| 1122 | clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; | |
| 1123 | }; | |
| 1124 | ||
| 1125 | gpt3_gate_fck: gpt3_gate_fck { | |
| 1126 | #clock-cells = <0>; | |
| 1127 | compatible = "ti,composite-gate-clock"; | |
| 1128 | clocks = <&sys_ck>; | |
| 1129 | ti,bit-shift = <4>; | |
| 1130 | reg = <0x1000>; | |
| 1131 | }; | |
| 1132 | ||
| 1133 | gpt3_mux_fck: gpt3_mux_fck { | |
| 1134 | #clock-cells = <0>; | |
| 1135 | compatible = "ti,composite-mux-clock"; | |
| 1136 | clocks = <&omap_32k_fck>, <&sys_ck>; | |
| 1137 | ti,bit-shift = <1>; | |
| 1138 | reg = <0x1040>; | |
| 1139 | }; | |
| 1140 | ||
| 1141 | gpt3_fck: gpt3_fck { | |
| 1142 | #clock-cells = <0>; | |
| 1143 | compatible = "ti,composite-clock"; | |
| 1144 | clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; | |
| 1145 | }; | |
| 1146 | ||
| 1147 | gpt4_gate_fck: gpt4_gate_fck { | |
| 1148 | #clock-cells = <0>; | |
| 1149 | compatible = "ti,composite-gate-clock"; | |
| 1150 | clocks = <&sys_ck>; | |
| 1151 | ti,bit-shift = <5>; | |
| 1152 | reg = <0x1000>; | |
| 1153 | }; | |
| 1154 | ||
| 1155 | gpt4_mux_fck: gpt4_mux_fck { | |
| 1156 | #clock-cells = <0>; | |
| 1157 | compatible = "ti,composite-mux-clock"; | |
| 1158 | clocks = <&omap_32k_fck>, <&sys_ck>; | |
| 1159 | ti,bit-shift = <2>; | |
| 1160 | reg = <0x1040>; | |
| 1161 | }; | |
| 1162 | ||
| 1163 | gpt4_fck: gpt4_fck { | |
| 1164 | #clock-cells = <0>; | |
| 1165 | compatible = "ti,composite-clock"; | |
| 1166 | clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; | |
| 1167 | }; | |
| 1168 | ||
| 1169 | gpt5_gate_fck: gpt5_gate_fck { | |
| 1170 | #clock-cells = <0>; | |
| 1171 | compatible = "ti,composite-gate-clock"; | |
| 1172 | clocks = <&sys_ck>; | |
| 1173 | ti,bit-shift = <6>; | |
| 1174 | reg = <0x1000>; | |
| 1175 | }; | |
| 1176 | ||
| 1177 | gpt5_mux_fck: gpt5_mux_fck { | |
| 1178 | #clock-cells = <0>; | |
| 1179 | compatible = "ti,composite-mux-clock"; | |
| 1180 | clocks = <&omap_32k_fck>, <&sys_ck>; | |
| 1181 | ti,bit-shift = <3>; | |
| 1182 | reg = <0x1040>; | |
| 1183 | }; | |
| 1184 | ||
| 1185 | gpt5_fck: gpt5_fck { | |
| 1186 | #clock-cells = <0>; | |
| 1187 | compatible = "ti,composite-clock"; | |
| 1188 | clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; | |
| 1189 | }; | |
| 1190 | ||
| 1191 | gpt6_gate_fck: gpt6_gate_fck { | |
| 1192 | #clock-cells = <0>; | |
| 1193 | compatible = "ti,composite-gate-clock"; | |
| 1194 | clocks = <&sys_ck>; | |
| 1195 | ti,bit-shift = <7>; | |
| 1196 | reg = <0x1000>; | |
| 1197 | }; | |
| 1198 | ||
| 1199 | gpt6_mux_fck: gpt6_mux_fck { | |
| 1200 | #clock-cells = <0>; | |
| 1201 | compatible = "ti,composite-mux-clock"; | |
| 1202 | clocks = <&omap_32k_fck>, <&sys_ck>; | |
| 1203 | ti,bit-shift = <4>; | |
| 1204 | reg = <0x1040>; | |
| 1205 | }; | |
| 1206 | ||
| 1207 | gpt6_fck: gpt6_fck { | |
| 1208 | #clock-cells = <0>; | |
| 1209 | compatible = "ti,composite-clock"; | |
| 1210 | clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; | |
| 1211 | }; | |
| 1212 | ||
| 1213 | gpt7_gate_fck: gpt7_gate_fck { | |
| 1214 | #clock-cells = <0>; | |
| 1215 | compatible = "ti,composite-gate-clock"; | |
| 1216 | clocks = <&sys_ck>; | |
| 1217 | ti,bit-shift = <8>; | |
| 1218 | reg = <0x1000>; | |
| 1219 | }; | |
| 1220 | ||
| 1221 | gpt7_mux_fck: gpt7_mux_fck { | |
| 1222 | #clock-cells = <0>; | |
| 1223 | compatible = "ti,composite-mux-clock"; | |
| 1224 | clocks = <&omap_32k_fck>, <&sys_ck>; | |
| 1225 | ti,bit-shift = <5>; | |
| 1226 | reg = <0x1040>; | |
| 1227 | }; | |
| 1228 | ||
| 1229 | gpt7_fck: gpt7_fck { | |
| 1230 | #clock-cells = <0>; | |
| 1231 | compatible = "ti,composite-clock"; | |
| 1232 | clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; | |
| 1233 | }; | |
| 1234 | ||
| 1235 | gpt8_gate_fck: gpt8_gate_fck { | |
| 1236 | #clock-cells = <0>; | |
| 1237 | compatible = "ti,composite-gate-clock"; | |
| 1238 | clocks = <&sys_ck>; | |
| 1239 | ti,bit-shift = <9>; | |
| 1240 | reg = <0x1000>; | |
| 1241 | }; | |
| 1242 | ||
| 1243 | gpt8_mux_fck: gpt8_mux_fck { | |
| 1244 | #clock-cells = <0>; | |
| 1245 | compatible = "ti,composite-mux-clock"; | |
| 1246 | clocks = <&omap_32k_fck>, <&sys_ck>; | |
| 1247 | ti,bit-shift = <6>; | |
| 1248 | reg = <0x1040>; | |
| 1249 | }; | |
| 1250 | ||
| 1251 | gpt8_fck: gpt8_fck { | |
| 1252 | #clock-cells = <0>; | |
| 1253 | compatible = "ti,composite-clock"; | |
| 1254 | clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; | |
| 1255 | }; | |
| 1256 | ||
| 1257 | gpt9_gate_fck: gpt9_gate_fck { | |
| 1258 | #clock-cells = <0>; | |
| 1259 | compatible = "ti,composite-gate-clock"; | |
| 1260 | clocks = <&sys_ck>; | |
| 1261 | ti,bit-shift = <10>; | |
| 1262 | reg = <0x1000>; | |
| 1263 | }; | |
| 1264 | ||
| 1265 | gpt9_mux_fck: gpt9_mux_fck { | |
| 1266 | #clock-cells = <0>; | |
| 1267 | compatible = "ti,composite-mux-clock"; | |
| 1268 | clocks = <&omap_32k_fck>, <&sys_ck>; | |
| 1269 | ti,bit-shift = <7>; | |
| 1270 | reg = <0x1040>; | |
| 1271 | }; | |
| 1272 | ||
| 1273 | gpt9_fck: gpt9_fck { | |
| 1274 | #clock-cells = <0>; | |
| 1275 | compatible = "ti,composite-clock"; | |
| 1276 | clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; | |
| 1277 | }; | |
| 1278 | ||
| 1279 | per_32k_alwon_fck: per_32k_alwon_fck { | |
| 1280 | #clock-cells = <0>; | |
| 1281 | compatible = "fixed-factor-clock"; | |
| 1282 | clocks = <&omap_32k_fck>; | |
| 1283 | clock-mult = <1>; | |
| 1284 | clock-div = <1>; | |
| 1285 | }; | |
| 1286 | ||
| 1287 | gpio6_dbck: gpio6_dbck { | |
| 1288 | #clock-cells = <0>; | |
| 1289 | compatible = "ti,gate-clock"; | |
| 1290 | clocks = <&per_32k_alwon_fck>; | |
| 1291 | reg = <0x1000>; | |
| 1292 | ti,bit-shift = <17>; | |
| 1293 | }; | |
| 1294 | ||
| 1295 | gpio5_dbck: gpio5_dbck { | |
| 1296 | #clock-cells = <0>; | |
| 1297 | compatible = "ti,gate-clock"; | |
| 1298 | clocks = <&per_32k_alwon_fck>; | |
| 1299 | reg = <0x1000>; | |
| 1300 | ti,bit-shift = <16>; | |
| 1301 | }; | |
| 1302 | ||
| 1303 | gpio4_dbck: gpio4_dbck { | |
| 1304 | #clock-cells = <0>; | |
| 1305 | compatible = "ti,gate-clock"; | |
| 1306 | clocks = <&per_32k_alwon_fck>; | |
| 1307 | reg = <0x1000>; | |
| 1308 | ti,bit-shift = <15>; | |
| 1309 | }; | |
| 1310 | ||
| 1311 | gpio3_dbck: gpio3_dbck { | |
| 1312 | #clock-cells = <0>; | |
| 1313 | compatible = "ti,gate-clock"; | |
| 1314 | clocks = <&per_32k_alwon_fck>; | |
| 1315 | reg = <0x1000>; | |
| 1316 | ti,bit-shift = <14>; | |
| 1317 | }; | |
| 1318 | ||
| 1319 | gpio2_dbck: gpio2_dbck { | |
| 1320 | #clock-cells = <0>; | |
| 1321 | compatible = "ti,gate-clock"; | |
| 1322 | clocks = <&per_32k_alwon_fck>; | |
| 1323 | reg = <0x1000>; | |
| 1324 | ti,bit-shift = <13>; | |
| 1325 | }; | |
| 1326 | ||
| 1327 | wdt3_fck: wdt3_fck { | |
| 1328 | #clock-cells = <0>; | |
| 1329 | compatible = "ti,wait-gate-clock"; | |
| 1330 | clocks = <&per_32k_alwon_fck>; | |
| 1331 | reg = <0x1000>; | |
| 1332 | ti,bit-shift = <12>; | |
| 1333 | }; | |
| 1334 | ||
| 1335 | per_l4_ick: per_l4_ick { | |
| 1336 | #clock-cells = <0>; | |
| 1337 | compatible = "fixed-factor-clock"; | |
| 1338 | clocks = <&l4_ick>; | |
| 1339 | clock-mult = <1>; | |
| 1340 | clock-div = <1>; | |
| 1341 | }; | |
| 1342 | ||
| 1343 | gpio6_ick: gpio6_ick { | |
| 1344 | #clock-cells = <0>; | |
| 1345 | compatible = "ti,omap3-interface-clock"; | |
| 1346 | clocks = <&per_l4_ick>; | |
| 1347 | reg = <0x1010>; | |
| 1348 | ti,bit-shift = <17>; | |
| 1349 | }; | |
| 1350 | ||
| 1351 | gpio5_ick: gpio5_ick { | |
| 1352 | #clock-cells = <0>; | |
| 1353 | compatible = "ti,omap3-interface-clock"; | |
| 1354 | clocks = <&per_l4_ick>; | |
| 1355 | reg = <0x1010>; | |
| 1356 | ti,bit-shift = <16>; | |
| 1357 | }; | |
| 1358 | ||
| 1359 | gpio4_ick: gpio4_ick { | |
| 1360 | #clock-cells = <0>; | |
| 1361 | compatible = "ti,omap3-interface-clock"; | |
| 1362 | clocks = <&per_l4_ick>; | |
| 1363 | reg = <0x1010>; | |
| 1364 | ti,bit-shift = <15>; | |
| 1365 | }; | |
| 1366 | ||
| 1367 | gpio3_ick: gpio3_ick { | |
| 1368 | #clock-cells = <0>; | |
| 1369 | compatible = "ti,omap3-interface-clock"; | |
| 1370 | clocks = <&per_l4_ick>; | |
| 1371 | reg = <0x1010>; | |
| 1372 | ti,bit-shift = <14>; | |
| 1373 | }; | |
| 1374 | ||
| 1375 | gpio2_ick: gpio2_ick { | |
| 1376 | #clock-cells = <0>; | |
| 1377 | compatible = "ti,omap3-interface-clock"; | |
| 1378 | clocks = <&per_l4_ick>; | |
| 1379 | reg = <0x1010>; | |
| 1380 | ti,bit-shift = <13>; | |
| 1381 | }; | |
| 1382 | ||
| 1383 | wdt3_ick: wdt3_ick { | |
| 1384 | #clock-cells = <0>; | |
| 1385 | compatible = "ti,omap3-interface-clock"; | |
| 1386 | clocks = <&per_l4_ick>; | |
| 1387 | reg = <0x1010>; | |
| 1388 | ti,bit-shift = <12>; | |
| 1389 | }; | |
| 1390 | ||
| 1391 | uart3_ick: uart3_ick { | |
| 1392 | #clock-cells = <0>; | |
| 1393 | compatible = "ti,omap3-interface-clock"; | |
| 1394 | clocks = <&per_l4_ick>; | |
| 1395 | reg = <0x1010>; | |
| 1396 | ti,bit-shift = <11>; | |
| 1397 | }; | |
| 1398 | ||
| 1399 | uart4_ick: uart4_ick { | |
| 1400 | #clock-cells = <0>; | |
| 1401 | compatible = "ti,omap3-interface-clock"; | |
| 1402 | clocks = <&per_l4_ick>; | |
| 1403 | reg = <0x1010>; | |
| 1404 | ti,bit-shift = <18>; | |
| 1405 | }; | |
| 1406 | ||
| 1407 | gpt9_ick: gpt9_ick { | |
| 1408 | #clock-cells = <0>; | |
| 1409 | compatible = "ti,omap3-interface-clock"; | |
| 1410 | clocks = <&per_l4_ick>; | |
| 1411 | reg = <0x1010>; | |
| 1412 | ti,bit-shift = <10>; | |
| 1413 | }; | |
| 1414 | ||
| 1415 | gpt8_ick: gpt8_ick { | |
| 1416 | #clock-cells = <0>; | |
| 1417 | compatible = "ti,omap3-interface-clock"; | |
| 1418 | clocks = <&per_l4_ick>; | |
| 1419 | reg = <0x1010>; | |
| 1420 | ti,bit-shift = <9>; | |
| 1421 | }; | |
| 1422 | ||
| 1423 | gpt7_ick: gpt7_ick { | |
| 1424 | #clock-cells = <0>; | |
| 1425 | compatible = "ti,omap3-interface-clock"; | |
| 1426 | clocks = <&per_l4_ick>; | |
| 1427 | reg = <0x1010>; | |
| 1428 | ti,bit-shift = <8>; | |
| 1429 | }; | |
| 1430 | ||
| 1431 | gpt6_ick: gpt6_ick { | |
| 1432 | #clock-cells = <0>; | |
| 1433 | compatible = "ti,omap3-interface-clock"; | |
| 1434 | clocks = <&per_l4_ick>; | |
| 1435 | reg = <0x1010>; | |
| 1436 | ti,bit-shift = <7>; | |
| 1437 | }; | |
| 1438 | ||
| 1439 | gpt5_ick: gpt5_ick { | |
| 1440 | #clock-cells = <0>; | |
| 1441 | compatible = "ti,omap3-interface-clock"; | |
| 1442 | clocks = <&per_l4_ick>; | |
| 1443 | reg = <0x1010>; | |
| 1444 | ti,bit-shift = <6>; | |
| 1445 | }; | |
| 1446 | ||
| 1447 | gpt4_ick: gpt4_ick { | |
| 1448 | #clock-cells = <0>; | |
| 1449 | compatible = "ti,omap3-interface-clock"; | |
| 1450 | clocks = <&per_l4_ick>; | |
| 1451 | reg = <0x1010>; | |
| 1452 | ti,bit-shift = <5>; | |
| 1453 | }; | |
| 1454 | ||
| 1455 | gpt3_ick: gpt3_ick { | |
| 1456 | #clock-cells = <0>; | |
| 1457 | compatible = "ti,omap3-interface-clock"; | |
| 1458 | clocks = <&per_l4_ick>; | |
| 1459 | reg = <0x1010>; | |
| 1460 | ti,bit-shift = <4>; | |
| 1461 | }; | |
| 1462 | ||
| 1463 | gpt2_ick: gpt2_ick { | |
| 1464 | #clock-cells = <0>; | |
| 1465 | compatible = "ti,omap3-interface-clock"; | |
| 1466 | clocks = <&per_l4_ick>; | |
| 1467 | reg = <0x1010>; | |
| 1468 | ti,bit-shift = <3>; | |
| 1469 | }; | |
| 1470 | ||
| 1471 | mcbsp2_ick: mcbsp2_ick { | |
| 1472 | #clock-cells = <0>; | |
| 1473 | compatible = "ti,omap3-interface-clock"; | |
| 1474 | clocks = <&per_l4_ick>; | |
| 1475 | reg = <0x1010>; | |
| 1476 | ti,bit-shift = <0>; | |
| 1477 | }; | |
| 1478 | ||
| 1479 | mcbsp3_ick: mcbsp3_ick { | |
| 1480 | #clock-cells = <0>; | |
| 1481 | compatible = "ti,omap3-interface-clock"; | |
| 1482 | clocks = <&per_l4_ick>; | |
| 1483 | reg = <0x1010>; | |
| 1484 | ti,bit-shift = <1>; | |
| 1485 | }; | |
| 1486 | ||
| 1487 | mcbsp4_ick: mcbsp4_ick { | |
| 1488 | #clock-cells = <0>; | |
| 1489 | compatible = "ti,omap3-interface-clock"; | |
| 1490 | clocks = <&per_l4_ick>; | |
| 1491 | reg = <0x1010>; | |
| 1492 | ti,bit-shift = <2>; | |
| 1493 | }; | |
| 1494 | ||
| 1495 | mcbsp2_gate_fck: mcbsp2_gate_fck { | |
| 1496 | #clock-cells = <0>; | |
| 1497 | compatible = "ti,composite-gate-clock"; | |
| 1498 | clocks = <&mcbsp_clks>; | |
| 1499 | ti,bit-shift = <0>; | |
| 1500 | reg = <0x1000>; | |
| 1501 | }; | |
| 1502 | ||
| 1503 | mcbsp3_gate_fck: mcbsp3_gate_fck { | |
| 1504 | #clock-cells = <0>; | |
| 1505 | compatible = "ti,composite-gate-clock"; | |
| 1506 | clocks = <&mcbsp_clks>; | |
| 1507 | ti,bit-shift = <1>; | |
| 1508 | reg = <0x1000>; | |
| 1509 | }; | |
| 1510 | ||
| 1511 | mcbsp4_gate_fck: mcbsp4_gate_fck { | |
| 1512 | #clock-cells = <0>; | |
| 1513 | compatible = "ti,composite-gate-clock"; | |
| 1514 | clocks = <&mcbsp_clks>; | |
| 1515 | ti,bit-shift = <2>; | |
| 1516 | reg = <0x1000>; | |
| 1517 | }; | |
| 1518 | ||
| 1519 | emu_src_mux_ck: emu_src_mux_ck { | |
| 1520 | #clock-cells = <0>; | |
| 1521 | compatible = "ti,mux-clock"; | |
| 1522 | clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; | |
| 1523 | reg = <0x1140>; | |
| 1524 | }; | |
| 1525 | ||
| 1526 | emu_src_ck: emu_src_ck { | |
| 1527 | #clock-cells = <0>; | |
| 1528 | compatible = "ti,clkdm-gate-clock"; | |
| 1529 | clocks = <&emu_src_mux_ck>; | |
| 1530 | }; | |
| 1531 | ||
| 1532 | pclk_fck: pclk_fck { | |
| 1533 | #clock-cells = <0>; | |
| 1534 | compatible = "ti,divider-clock"; | |
| 1535 | clocks = <&emu_src_ck>; | |
| 1536 | ti,bit-shift = <8>; | |
| 1537 | ti,max-div = <7>; | |
| 1538 | reg = <0x1140>; | |
| 1539 | ti,index-starts-at-one; | |
| 1540 | }; | |
| 1541 | ||
| 1542 | pclkx2_fck: pclkx2_fck { | |
| 1543 | #clock-cells = <0>; | |
| 1544 | compatible = "ti,divider-clock"; | |
| 1545 | clocks = <&emu_src_ck>; | |
| 1546 | ti,bit-shift = <6>; | |
| 1547 | ti,max-div = <3>; | |
| 1548 | reg = <0x1140>; | |
| 1549 | ti,index-starts-at-one; | |
| 1550 | }; | |
| 1551 | ||
| 1552 | atclk_fck: atclk_fck { | |
| 1553 | #clock-cells = <0>; | |
| 1554 | compatible = "ti,divider-clock"; | |
| 1555 | clocks = <&emu_src_ck>; | |
| 1556 | ti,bit-shift = <4>; | |
| 1557 | ti,max-div = <3>; | |
| 1558 | reg = <0x1140>; | |
| 1559 | ti,index-starts-at-one; | |
| 1560 | }; | |
| 1561 | ||
| 1562 | traceclk_src_fck: traceclk_src_fck { | |
| 1563 | #clock-cells = <0>; | |
| 1564 | compatible = "ti,mux-clock"; | |
| 1565 | clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; | |
| 1566 | ti,bit-shift = <2>; | |
| 1567 | reg = <0x1140>; | |
| 1568 | }; | |
| 1569 | ||
| 1570 | traceclk_fck: traceclk_fck { | |
| 1571 | #clock-cells = <0>; | |
| 1572 | compatible = "ti,divider-clock"; | |
| 1573 | clocks = <&traceclk_src_fck>; | |
| 1574 | ti,bit-shift = <11>; | |
| 1575 | ti,max-div = <7>; | |
| 1576 | reg = <0x1140>; | |
| 1577 | ti,index-starts-at-one; | |
| 1578 | }; | |
| 1579 | ||
| 1580 | secure_32k_fck: secure_32k_fck { | |
| 1581 | #clock-cells = <0>; | |
| 1582 | compatible = "fixed-clock"; | |
| 1583 | clock-frequency = <32768>; | |
| 1584 | }; | |
| 1585 | ||
| 1586 | gpt12_fck: gpt12_fck { | |
| 1587 | #clock-cells = <0>; | |
| 1588 | compatible = "fixed-factor-clock"; | |
| 1589 | clocks = <&secure_32k_fck>; | |
| 1590 | clock-mult = <1>; | |
| 1591 | clock-div = <1>; | |
| 1592 | }; | |
| 1593 | ||
| 1594 | wdt1_fck: wdt1_fck { | |
| 1595 | #clock-cells = <0>; | |
| 1596 | compatible = "fixed-factor-clock"; | |
| 1597 | clocks = <&secure_32k_fck>; | |
| 1598 | clock-mult = <1>; | |
| 1599 | clock-div = <1>; | |
| 1600 | }; | |
| 1601 | }; | |
| 1602 | ||
| 1603 | &cm_clockdomains { | |
| 1604 | core_l3_clkdm: core_l3_clkdm { | |
| 1605 | compatible = "ti,clockdomain"; | |
| 1606 | clocks = <&sdrc_ick>; | |
| 1607 | }; | |
| 1608 | ||
| 1609 | dpll3_clkdm: dpll3_clkdm { | |
| 1610 | compatible = "ti,clockdomain"; | |
| 1611 | clocks = <&dpll3_ck>; | |
| 1612 | }; | |
| 1613 | ||
| 1614 | dpll1_clkdm: dpll1_clkdm { | |
| 1615 | compatible = "ti,clockdomain"; | |
| 1616 | clocks = <&dpll1_ck>; | |
| 1617 | }; | |
| 1618 | ||
| 1619 | per_clkdm: per_clkdm { | |
| 1620 | compatible = "ti,clockdomain"; | |
| 1621 | clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, | |
| 1622 | <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, | |
| 1623 | <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, | |
| 1624 | <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, | |
| 1625 | <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, | |
| 1626 | <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, | |
| 1627 | <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, | |
| 1628 | <&mcbsp4_ick>; | |
| 1629 | }; | |
| 1630 | ||
| 1631 | emu_clkdm: emu_clkdm { | |
| 1632 | compatible = "ti,clockdomain"; | |
| 1633 | clocks = <&emu_src_ck>; | |
| 1634 | }; | |
| 1635 | ||
| 1636 | dpll4_clkdm: dpll4_clkdm { | |
| 1637 | compatible = "ti,clockdomain"; | |
| 1638 | clocks = <&dpll4_ck>; | |
| 1639 | }; | |
| 1640 | ||
| 1641 | wkup_clkdm: wkup_clkdm { | |
| 1642 | compatible = "ti,clockdomain"; | |
| 1643 | clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, | |
| 1644 | <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, | |
| 1645 | <&gpt1_ick>; | |
| 1646 | }; | |
| 1647 | ||
| 1648 | dss_clkdm: dss_clkdm { | |
| 1649 | compatible = "ti,clockdomain"; | |
| 1650 | clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>; | |
| 1651 | }; | |
| 1652 | ||
| 1653 | core_l4_clkdm: core_l4_clkdm { | |
| 1654 | compatible = "ti,clockdomain"; | |
| 1655 | clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, | |
| 1656 | <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, | |
| 1657 | <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, | |
| 1658 | <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, | |
| 1659 | <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, | |
| 1660 | <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, | |
| 1661 | <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, | |
| 1662 | <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, | |
| 1663 | <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>; | |
| 1664 | }; | |
| 1665 | }; |