]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/arm/boot/dts/omap3xxx-clocks.dtsi
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'v3.17-rc3' into next
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / omap3xxx-clocks.dtsi
CommitLineData
657fc11c
TK		 1/*
2 * Device Tree Source for OMAP3 clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10&prm_clocks {
11 virt_16_8m_ck: virt_16_8m_ck {
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
15 };
16
17 osc_sys_ck: osc_sys_ck {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
21 reg = <0x0d40>;
22 };
23
24 sys_ck: sys_ck {
25 #clock-cells = <0>;
26 compatible = "ti,divider-clock";
27 clocks = <&osc_sys_ck>;
28 ti,bit-shift = <6>;
29 ti,max-div = <3>;
30 reg = <0x1270>;
31 ti,index-starts-at-one;
32 };
33
34 sys_clkout1: sys_clkout1 {
35 #clock-cells = <0>;
36 compatible = "ti,gate-clock";
37 clocks = <&osc_sys_ck>;
38 reg = <0x0d70>;
39 ti,bit-shift = <7>;
40 };
41
42 dpll3_x2_ck: dpll3_x2_ck {
43 #clock-cells = <0>;
44 compatible = "fixed-factor-clock";
45 clocks = <&dpll3_ck>;
46 clock-mult = <2>;
47 clock-div = <1>;
48 };
49
50 dpll3_m2x2_ck: dpll3_m2x2_ck {
51 #clock-cells = <0>;
52 compatible = "fixed-factor-clock";
53 clocks = <&dpll3_m2_ck>;
54 clock-mult = <2>;
55 clock-div = <1>;
56 };
57
58 dpll4_x2_ck: dpll4_x2_ck {
59 #clock-cells = <0>;
60 compatible = "fixed-factor-clock";
61 clocks = <&dpll4_ck>;
62 clock-mult = <2>;
63 clock-div = <1>;
64 };
65
66 corex2_fck: corex2_fck {
67 #clock-cells = <0>;
68 compatible = "fixed-factor-clock";
69 clocks = <&dpll3_m2x2_ck>;
70 clock-mult = <1>;
71 clock-div = <1>;
72 };
73
74 wkup_l4_ick: wkup_l4_ick {
75 #clock-cells = <0>;
76 compatible = "fixed-factor-clock";
77 clocks = <&sys_ck>;
78 clock-mult = <1>;
79 clock-div = <1>;
80 };
81};
82&scrm_clocks {
83 mcbsp5_mux_fck: mcbsp5_mux_fck {
84 #clock-cells = <0>;
85 compatible = "ti,composite-mux-clock";
86 clocks = <&core_96m_fck>, <&mcbsp_clks>;
87 ti,bit-shift = <4>;
88 reg = <0x02d8>;
89 };
90
91 mcbsp5_fck: mcbsp5_fck {
92 #clock-cells = <0>;
93 compatible = "ti,composite-clock";
94 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
95 };
96
97 mcbsp1_mux_fck: mcbsp1_mux_fck {
98 #clock-cells = <0>;
99 compatible = "ti,composite-mux-clock";
100 clocks = <&core_96m_fck>, <&mcbsp_clks>;
101 ti,bit-shift = <2>;
102 reg = <0x0274>;
103 };
104
105 mcbsp1_fck: mcbsp1_fck {
106 #clock-cells = <0>;
107 compatible = "ti,composite-clock";
108 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
109 };
110
111 mcbsp2_mux_fck: mcbsp2_mux_fck {
112 #clock-cells = <0>;
113 compatible = "ti,composite-mux-clock";
114 clocks = <&per_96m_fck>, <&mcbsp_clks>;
115 ti,bit-shift = <6>;
116 reg = <0x0274>;
117 };
118
119 mcbsp2_fck: mcbsp2_fck {
120 #clock-cells = <0>;
121 compatible = "ti,composite-clock";
122 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
123 };
124
125 mcbsp3_mux_fck: mcbsp3_mux_fck {
126 #clock-cells = <0>;
127 compatible = "ti,composite-mux-clock";
128 clocks = <&per_96m_fck>, <&mcbsp_clks>;
129 reg = <0x02d8>;
130 };
131
132 mcbsp3_fck: mcbsp3_fck {
133 #clock-cells = <0>;
134 compatible = "ti,composite-clock";
135 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
136 };
137
138 mcbsp4_mux_fck: mcbsp4_mux_fck {
139 #clock-cells = <0>;
140 compatible = "ti,composite-mux-clock";
141 clocks = <&per_96m_fck>, <&mcbsp_clks>;
142 ti,bit-shift = <2>;
143 reg = <0x02d8>;
144 };
145
146 mcbsp4_fck: mcbsp4_fck {
147 #clock-cells = <0>;
148 compatible = "ti,composite-clock";
149 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
150 };
151};
152&cm_clocks {
153 dummy_apb_pclk: dummy_apb_pclk {
154 #clock-cells = <0>;
155 compatible = "fixed-clock";
156 clock-frequency = <0x0>;
157 };
158
159 omap_32k_fck: omap_32k_fck {
160 #clock-cells = <0>;
161 compatible = "fixed-clock";
162 clock-frequency = <32768>;
163 };
164
165 virt_12m_ck: virt_12m_ck {
166 #clock-cells = <0>;
167 compatible = "fixed-clock";
168 clock-frequency = <12000000>;
169 };
170
171 virt_13m_ck: virt_13m_ck {
172 #clock-cells = <0>;
173 compatible = "fixed-clock";
174 clock-frequency = <13000000>;
175 };
176
177 virt_19200000_ck: virt_19200000_ck {
178 #clock-cells = <0>;
179 compatible = "fixed-clock";
180 clock-frequency = <19200000>;
181 };
182
183 virt_26000000_ck: virt_26000000_ck {
184 #clock-cells = <0>;
185 compatible = "fixed-clock";
186 clock-frequency = <26000000>;
187 };
188
189 virt_38_4m_ck: virt_38_4m_ck {
190 #clock-cells = <0>;
191 compatible = "fixed-clock";
192 clock-frequency = <38400000>;
193 };
194
195 dpll4_ck: dpll4_ck {
196 #clock-cells = <0>;
197 compatible = "ti,omap3-dpll-per-clock";
198 clocks = <&sys_ck>, <&sys_ck>;
199 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
200 };
201
202 dpll4_m2_ck: dpll4_m2_ck {
203 #clock-cells = <0>;
204 compatible = "ti,divider-clock";
205 clocks = <&dpll4_ck>;
206 ti,max-div = <63>;
207 reg = <0x0d48>;
208 ti,index-starts-at-one;
209 };
210
211 dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
212 #clock-cells = <0>;
213 compatible = "fixed-factor-clock";
214 clocks = <&dpll4_m2_ck>;
215 clock-mult = <2>;
216 clock-div = <1>;
217 };
218
219 dpll4_m2x2_ck: dpll4_m2x2_ck {
220 #clock-cells = <0>;
221 compatible = "ti,gate-clock";
222 clocks = <&dpll4_m2x2_mul_ck>;
223 ti,bit-shift = <0x1b>;
224 reg = <0x0d00>;
225 ti,set-bit-to-disable;
226 };
227
228 omap_96m_alwon_fck: omap_96m_alwon_fck {
229 #clock-cells = <0>;
230 compatible = "fixed-factor-clock";
231 clocks = <&dpll4_m2x2_ck>;
232 clock-mult = <1>;
233 clock-div = <1>;
234 };
235
236 dpll3_ck: dpll3_ck {
237 #clock-cells = <0>;
238 compatible = "ti,omap3-dpll-core-clock";
239 clocks = <&sys_ck>, <&sys_ck>;
240 reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
241 };
242
243 dpll3_m3_ck: dpll3_m3_ck {
244 #clock-cells = <0>;
245 compatible = "ti,divider-clock";
246 clocks = <&dpll3_ck>;
247 ti,bit-shift = <16>;
248 ti,max-div = <31>;
249 reg = <0x1140>;
250 ti,index-starts-at-one;
251 };
252
253 dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
254 #clock-cells = <0>;
255 compatible = "fixed-factor-clock";
256 clocks = <&dpll3_m3_ck>;
257 clock-mult = <2>;
258 clock-div = <1>;
259 };
260
261 dpll3_m3x2_ck: dpll3_m3x2_ck {
262 #clock-cells = <0>;
263 compatible = "ti,gate-clock";
264 clocks = <&dpll3_m3x2_mul_ck>;
265 ti,bit-shift = <0xc>;
266 reg = <0x0d00>;
267 ti,set-bit-to-disable;
268 };
269
270 emu_core_alwon_ck: emu_core_alwon_ck {
271 #clock-cells = <0>;
272 compatible = "fixed-factor-clock";
273 clocks = <&dpll3_m3x2_ck>;
274 clock-mult = <1>;
275 clock-div = <1>;
276 };
277
278 sys_altclk: sys_altclk {
279 #clock-cells = <0>;
280 compatible = "fixed-clock";
281 clock-frequency = <0x0>;
282 };
283
284 mcbsp_clks: mcbsp_clks {
285 #clock-cells = <0>;
286 compatible = "fixed-clock";
287 clock-frequency = <0x0>;
288 };
289
290 dpll3_m2_ck: dpll3_m2_ck {
291 #clock-cells = <0>;
292 compatible = "ti,divider-clock";
293 clocks = <&dpll3_ck>;
294 ti,bit-shift = <27>;
295 ti,max-div = <31>;
296 reg = <0x0d40>;
297 ti,index-starts-at-one;
298 };
299
300 core_ck: core_ck {
301 #clock-cells = <0>;
302 compatible = "fixed-factor-clock";
303 clocks = <&dpll3_m2_ck>;
304 clock-mult = <1>;
305 clock-div = <1>;
306 };
307
308 dpll1_fck: dpll1_fck {
309 #clock-cells = <0>;
310 compatible = "ti,divider-clock";
311 clocks = <&core_ck>;
312 ti,bit-shift = <19>;
313 ti,max-div = <7>;
314 reg = <0x0940>;
315 ti,index-starts-at-one;
316 };
317
318 dpll1_ck: dpll1_ck {
319 #clock-cells = <0>;
320 compatible = "ti,omap3-dpll-clock";
321 clocks = <&sys_ck>, <&dpll1_fck>;
322 reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
323 };
324
325 dpll1_x2_ck: dpll1_x2_ck {
326 #clock-cells = <0>;
327 compatible = "fixed-factor-clock";
328 clocks = <&dpll1_ck>;
329 clock-mult = <2>;
330 clock-div = <1>;
331 };
332
333 dpll1_x2m2_ck: dpll1_x2m2_ck {
334 #clock-cells = <0>;
335 compatible = "ti,divider-clock";
336 clocks = <&dpll1_x2_ck>;
337 ti,max-div = <31>;
338 reg = <0x0944>;
339 ti,index-starts-at-one;
340 };
341
342 cm_96m_fck: cm_96m_fck {
343 #clock-cells = <0>;
344 compatible = "fixed-factor-clock";
345 clocks = <&omap_96m_alwon_fck>;
346 clock-mult = <1>;
347 clock-div = <1>;
348 };
349
350 omap_96m_fck: omap_96m_fck {
351 #clock-cells = <0>;
352 compatible = "ti,mux-clock";
353 clocks = <&cm_96m_fck>, <&sys_ck>;
354 ti,bit-shift = <6>;
355 reg = <0x0d40>;
356 };
357
358 dpll4_m3_ck: dpll4_m3_ck {
359 #clock-cells = <0>;
360 compatible = "ti,divider-clock";
361 clocks = <&dpll4_ck>;
362 ti,bit-shift = <8>;
363 ti,max-div = <32>;
364 reg = <0x0e40>;
365 ti,index-starts-at-one;
366 };
367
368 dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
369 #clock-cells = <0>;
370 compatible = "fixed-factor-clock";
371 clocks = <&dpll4_m3_ck>;
372 clock-mult = <2>;
373 clock-div = <1>;
374 };
375
376 dpll4_m3x2_ck: dpll4_m3x2_ck {
377 #clock-cells = <0>;
378 compatible = "ti,gate-clock";
379 clocks = <&dpll4_m3x2_mul_ck>;
380 ti,bit-shift = <0x1c>;
381 reg = <0x0d00>;
382 ti,set-bit-to-disable;
383 };
384
385 omap_54m_fck: omap_54m_fck {
386 #clock-cells = <0>;
387 compatible = "ti,mux-clock";
388 clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
389 ti,bit-shift = <5>;
390 reg = <0x0d40>;
391 };
392
393 cm_96m_d2_fck: cm_96m_d2_fck {
394 #clock-cells = <0>;
395 compatible = "fixed-factor-clock";
396 clocks = <&cm_96m_fck>;
397 clock-mult = <1>;
398 clock-div = <2>;
399 };
400
401 omap_48m_fck: omap_48m_fck {
402 #clock-cells = <0>;
403 compatible = "ti,mux-clock";
404 clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
405 ti,bit-shift = <3>;
406 reg = <0x0d40>;
407 };
408
409 omap_12m_fck: omap_12m_fck {
410 #clock-cells = <0>;
411 compatible = "fixed-factor-clock";
412 clocks = <&omap_48m_fck>;
413 clock-mult = <1>;
414 clock-div = <4>;
415 };
416
417 dpll4_m4_ck: dpll4_m4_ck {
418 #clock-cells = <0>;
419 compatible = "ti,divider-clock";
420 clocks = <&dpll4_ck>;
421 ti,max-div = <32>;
422 reg = <0x0e40>;
423 ti,index-starts-at-one;
424 };
425
426 dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
427 #clock-cells = <0>;
c368dbe2 428 compatible = "ti,fixed-factor-clock";
657fc11c 429 clocks = <&dpll4_m4_ck>;
c368dbe2
TV		 430 ti,clock-mult = <2>;
431 ti,clock-div = <1>;
1d3361f6 432 ti,set-rate-parent;
657fc11c
TK		 433 };
434
435 dpll4_m4x2_ck: dpll4_m4x2_ck {
436 #clock-cells = <0>;
437 compatible = "ti,gate-clock";
438 clocks = <&dpll4_m4x2_mul_ck>;
439 ti,bit-shift = <0x1d>;
440 reg = <0x0d00>;
441 ti,set-bit-to-disable;
1d3361f6 442 ti,set-rate-parent;
657fc11c
TK		 443 };
444
445 dpll4_m5_ck: dpll4_m5_ck {
446 #clock-cells = <0>;
447 compatible = "ti,divider-clock";
448 clocks = <&dpll4_ck>;
449 ti,max-div = <63>;
450 reg = <0x0f40>;
451 ti,index-starts-at-one;
452 };
453
454 dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
455 #clock-cells = <0>;
e21a4ea3 456 compatible = "ti,fixed-factor-clock";
657fc11c 457 clocks = <&dpll4_m5_ck>;
e21a4ea3
LP		 458 ti,clock-mult = <2>;
459 ti,clock-div = <1>;
2febd999 460 ti,set-rate-parent;
657fc11c
TK		 461 };
462
463 dpll4_m5x2_ck: dpll4_m5x2_ck {
464 #clock-cells = <0>;
465 compatible = "ti,gate-clock";
466 clocks = <&dpll4_m5x2_mul_ck>;
467 ti,bit-shift = <0x1e>;
468 reg = <0x0d00>;
469 ti,set-bit-to-disable;
470 };
471
472 dpll4_m6_ck: dpll4_m6_ck {
473 #clock-cells = <0>;
474 compatible = "ti,divider-clock";
475 clocks = <&dpll4_ck>;
476 ti,bit-shift = <24>;
477 ti,max-div = <63>;
478 reg = <0x1140>;
479 ti,index-starts-at-one;
480 };
481
482 dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
483 #clock-cells = <0>;
484 compatible = "fixed-factor-clock";
485 clocks = <&dpll4_m6_ck>;
486 clock-mult = <2>;
487 clock-div = <1>;
488 };
489
490 dpll4_m6x2_ck: dpll4_m6x2_ck {
491 #clock-cells = <0>;
492 compatible = "ti,gate-clock";
493 clocks = <&dpll4_m6x2_mul_ck>;
494 ti,bit-shift = <0x1f>;
495 reg = <0x0d00>;
496 ti,set-bit-to-disable;
497 };
498
499 emu_per_alwon_ck: emu_per_alwon_ck {
500 #clock-cells = <0>;
501 compatible = "fixed-factor-clock";
502 clocks = <&dpll4_m6x2_ck>;
503 clock-mult = <1>;
504 clock-div = <1>;
505 };
506
507 clkout2_src_gate_ck: clkout2_src_gate_ck {
508 #clock-cells = <0>;
509 compatible = "ti,composite-no-wait-gate-clock";
510 clocks = <&core_ck>;
511 ti,bit-shift = <7>;
512 reg = <0x0d70>;
513 };
514
515 clkout2_src_mux_ck: clkout2_src_mux_ck {
516 #clock-cells = <0>;
517 compatible = "ti,composite-mux-clock";
518 clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
519 reg = <0x0d70>;
520 };
521
522 clkout2_src_ck: clkout2_src_ck {
523 #clock-cells = <0>;
524 compatible = "ti,composite-clock";
525 clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
526 };
527
528 sys_clkout2: sys_clkout2 {
529 #clock-cells = <0>;
530 compatible = "ti,divider-clock";
531 clocks = <&clkout2_src_ck>;
532 ti,bit-shift = <3>;
533 ti,max-div = <64>;
534 reg = <0x0d70>;
535 ti,index-power-of-two;
536 };
537
538 mpu_ck: mpu_ck {
539 #clock-cells = <0>;
540 compatible = "fixed-factor-clock";
541 clocks = <&dpll1_x2m2_ck>;
542 clock-mult = <1>;
543 clock-div = <1>;
544 };
545
546 arm_fck: arm_fck {
547 #clock-cells = <0>;
548 compatible = "ti,divider-clock";
549 clocks = <&mpu_ck>;
550 reg = <0x0924>;
551 ti,max-div = <2>;
552 };
553
554 emu_mpu_alwon_ck: emu_mpu_alwon_ck {
555 #clock-cells = <0>;
556 compatible = "fixed-factor-clock";
557 clocks = <&mpu_ck>;
558 clock-mult = <1>;
559 clock-div = <1>;
560 };
561
562 l3_ick: l3_ick {
563 #clock-cells = <0>;
564 compatible = "ti,divider-clock";
565 clocks = <&core_ck>;
566 ti,max-div = <3>;
567 reg = <0x0a40>;
568 ti,index-starts-at-one;
569 };
570
571 l4_ick: l4_ick {
572 #clock-cells = <0>;
573 compatible = "ti,divider-clock";
574 clocks = <&l3_ick>;
575 ti,bit-shift = <2>;
576 ti,max-div = <3>;
577 reg = <0x0a40>;
578 ti,index-starts-at-one;
579 };
580
581 rm_ick: rm_ick {
582 #clock-cells = <0>;
583 compatible = "ti,divider-clock";
584 clocks = <&l4_ick>;
585 ti,bit-shift = <1>;
586 ti,max-div = <3>;
587 reg = <0x0c40>;
588 ti,index-starts-at-one;
589 };
590
591 gpt10_gate_fck: gpt10_gate_fck {
592 #clock-cells = <0>;
593 compatible = "ti,composite-gate-clock";
594 clocks = <&sys_ck>;
595 ti,bit-shift = <11>;
596 reg = <0x0a00>;
597 };
598
599 gpt10_mux_fck: gpt10_mux_fck {
600 #clock-cells = <0>;
601 compatible = "ti,composite-mux-clock";
602 clocks = <&omap_32k_fck>, <&sys_ck>;
603 ti,bit-shift = <6>;
604 reg = <0x0a40>;
605 };
606
607 gpt10_fck: gpt10_fck {
608 #clock-cells = <0>;
609 compatible = "ti,composite-clock";
610 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
611 };
612
613 gpt11_gate_fck: gpt11_gate_fck {
614 #clock-cells = <0>;
615 compatible = "ti,composite-gate-clock";
616 clocks = <&sys_ck>;
617 ti,bit-shift = <12>;
618 reg = <0x0a00>;
619 };
620
621 gpt11_mux_fck: gpt11_mux_fck {
622 #clock-cells = <0>;
623 compatible = "ti,composite-mux-clock";
624 clocks = <&omap_32k_fck>, <&sys_ck>;
625 ti,bit-shift = <7>;
626 reg = <0x0a40>;
627 };
628
629 gpt11_fck: gpt11_fck {
630 #clock-cells = <0>;
631 compatible = "ti,composite-clock";
632 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
633 };
634
635 core_96m_fck: core_96m_fck {
636 #clock-cells = <0>;
637 compatible = "fixed-factor-clock";
638 clocks = <&omap_96m_fck>;
639 clock-mult = <1>;
640 clock-div = <1>;
641 };
642
643 mmchs2_fck: mmchs2_fck {
644 #clock-cells = <0>;
645 compatible = "ti,wait-gate-clock";
646 clocks = <&core_96m_fck>;
647 reg = <0x0a00>;
648 ti,bit-shift = <25>;
649 };
650
651 mmchs1_fck: mmchs1_fck {
652 #clock-cells = <0>;
653 compatible = "ti,wait-gate-clock";
654 clocks = <&core_96m_fck>;
655 reg = <0x0a00>;
656 ti,bit-shift = <24>;
657 };
658
659 i2c3_fck: i2c3_fck {
660 #clock-cells = <0>;
661 compatible = "ti,wait-gate-clock";
662 clocks = <&core_96m_fck>;
663 reg = <0x0a00>;
664 ti,bit-shift = <17>;
665 };
666
667 i2c2_fck: i2c2_fck {
668 #clock-cells = <0>;
669 compatible = "ti,wait-gate-clock";
670 clocks = <&core_96m_fck>;
671 reg = <0x0a00>;
672 ti,bit-shift = <16>;
673 };
674
675 i2c1_fck: i2c1_fck {
676 #clock-cells = <0>;
677 compatible = "ti,wait-gate-clock";
678 clocks = <&core_96m_fck>;
679 reg = <0x0a00>;
680 ti,bit-shift = <15>;
681 };
682
683 mcbsp5_gate_fck: mcbsp5_gate_fck {
684 #clock-cells = <0>;
685 compatible = "ti,composite-gate-clock";
686 clocks = <&mcbsp_clks>;
687 ti,bit-shift = <10>;
688 reg = <0x0a00>;
689 };
690
691 mcbsp1_gate_fck: mcbsp1_gate_fck {
692 #clock-cells = <0>;
693 compatible = "ti,composite-gate-clock";
694 clocks = <&mcbsp_clks>;
695 ti,bit-shift = <9>;
696 reg = <0x0a00>;
697 };
698
699 core_48m_fck: core_48m_fck {
700 #clock-cells = <0>;
701 compatible = "fixed-factor-clock";
702 clocks = <&omap_48m_fck>;
703 clock-mult = <1>;
704 clock-div = <1>;
705 };
706
707 mcspi4_fck: mcspi4_fck {
708 #clock-cells = <0>;
709 compatible = "ti,wait-gate-clock";
710 clocks = <&core_48m_fck>;
711 reg = <0x0a00>;
712 ti,bit-shift = <21>;
713 };
714
715 mcspi3_fck: mcspi3_fck {
716 #clock-cells = <0>;
717 compatible = "ti,wait-gate-clock";
718 clocks = <&core_48m_fck>;
719 reg = <0x0a00>;
720 ti,bit-shift = <20>;
721 };
722
723 mcspi2_fck: mcspi2_fck {
724 #clock-cells = <0>;
725 compatible = "ti,wait-gate-clock";
726 clocks = <&core_48m_fck>;
727 reg = <0x0a00>;
728 ti,bit-shift = <19>;
729 };
730
731 mcspi1_fck: mcspi1_fck {
732 #clock-cells = <0>;
733 compatible = "ti,wait-gate-clock";
734 clocks = <&core_48m_fck>;
735 reg = <0x0a00>;
736 ti,bit-shift = <18>;
737 };
738
739 uart2_fck: uart2_fck {
740 #clock-cells = <0>;
741 compatible = "ti,wait-gate-clock";
742 clocks = <&core_48m_fck>;
743 reg = <0x0a00>;
744 ti,bit-shift = <14>;
745 };
746
747 uart1_fck: uart1_fck {
748 #clock-cells = <0>;
749 compatible = "ti,wait-gate-clock";
750 clocks = <&core_48m_fck>;
751 reg = <0x0a00>;
752 ti,bit-shift = <13>;
753 };
754
755 core_12m_fck: core_12m_fck {
756 #clock-cells = <0>;
757 compatible = "fixed-factor-clock";
758 clocks = <&omap_12m_fck>;
759 clock-mult = <1>;
760 clock-div = <1>;
761 };
762
763 hdq_fck: hdq_fck {
764 #clock-cells = <0>;
765 compatible = "ti,wait-gate-clock";
766 clocks = <&core_12m_fck>;
767 reg = <0x0a00>;
768 ti,bit-shift = <22>;
769 };
770
771 core_l3_ick: core_l3_ick {
772 #clock-cells = <0>;
773 compatible = "fixed-factor-clock";
774 clocks = <&l3_ick>;
775 clock-mult = <1>;
776 clock-div = <1>;
777 };
778
779 sdrc_ick: sdrc_ick {
780 #clock-cells = <0>;
781 compatible = "ti,wait-gate-clock";
782 clocks = <&core_l3_ick>;
783 reg = <0x0a10>;
784 ti,bit-shift = <1>;
785 };
786
787 gpmc_fck: gpmc_fck {
788 #clock-cells = <0>;
789 compatible = "fixed-factor-clock";
790 clocks = <&core_l3_ick>;
791 clock-mult = <1>;
792 clock-div = <1>;
793 };
794
795 core_l4_ick: core_l4_ick {
796 #clock-cells = <0>;
797 compatible = "fixed-factor-clock";
798 clocks = <&l4_ick>;
799 clock-mult = <1>;
800 clock-div = <1>;
801 };
802
803 mmchs2_ick: mmchs2_ick {
804 #clock-cells = <0>;
805 compatible = "ti,omap3-interface-clock";
806 clocks = <&core_l4_ick>;
807 reg = <0x0a10>;
808 ti,bit-shift = <25>;
809 };
810
811 mmchs1_ick: mmchs1_ick {
812 #clock-cells = <0>;
813 compatible = "ti,omap3-interface-clock";
814 clocks = <&core_l4_ick>;
815 reg = <0x0a10>;
816 ti,bit-shift = <24>;
817 };
818
819 hdq_ick: hdq_ick {
820 #clock-cells = <0>;
821 compatible = "ti,omap3-interface-clock";
822 clocks = <&core_l4_ick>;
823 reg = <0x0a10>;
824 ti,bit-shift = <22>;
825 };
826
827 mcspi4_ick: mcspi4_ick {
828 #clock-cells = <0>;
829 compatible = "ti,omap3-interface-clock";
830 clocks = <&core_l4_ick>;
831 reg = <0x0a10>;
832 ti,bit-shift = <21>;
833 };
834
835 mcspi3_ick: mcspi3_ick {
836 #clock-cells = <0>;
837 compatible = "ti,omap3-interface-clock";
838 clocks = <&core_l4_ick>;
839 reg = <0x0a10>;
840 ti,bit-shift = <20>;
841 };
842
843 mcspi2_ick: mcspi2_ick {
844 #clock-cells = <0>;
845 compatible = "ti,omap3-interface-clock";
846 clocks = <&core_l4_ick>;
847 reg = <0x0a10>;
848 ti,bit-shift = <19>;
849 };
850
851 mcspi1_ick: mcspi1_ick {
852 #clock-cells = <0>;
853 compatible = "ti,omap3-interface-clock";
854 clocks = <&core_l4_ick>;
855 reg = <0x0a10>;
856 ti,bit-shift = <18>;
857 };
858
859 i2c3_ick: i2c3_ick {
860 #clock-cells = <0>;
861 compatible = "ti,omap3-interface-clock";
862 clocks = <&core_l4_ick>;
863 reg = <0x0a10>;
864 ti,bit-shift = <17>;
865 };
866
867 i2c2_ick: i2c2_ick {
868 #clock-cells = <0>;
869 compatible = "ti,omap3-interface-clock";
870 clocks = <&core_l4_ick>;
871 reg = <0x0a10>;
872 ti,bit-shift = <16>;
873 };
874
875 i2c1_ick: i2c1_ick {
876 #clock-cells = <0>;
877 compatible = "ti,omap3-interface-clock";
878 clocks = <&core_l4_ick>;
879 reg = <0x0a10>;
880 ti,bit-shift = <15>;
881 };
882
883 uart2_ick: uart2_ick {
884 #clock-cells = <0>;
885 compatible = "ti,omap3-interface-clock";
886 clocks = <&core_l4_ick>;
887 reg = <0x0a10>;
888 ti,bit-shift = <14>;
889 };
890
891 uart1_ick: uart1_ick {
892 #clock-cells = <0>;
893 compatible = "ti,omap3-interface-clock";
894 clocks = <&core_l4_ick>;
895 reg = <0x0a10>;
896 ti,bit-shift = <13>;
897 };
898
899 gpt11_ick: gpt11_ick {
900 #clock-cells = <0>;
901 compatible = "ti,omap3-interface-clock";
902 clocks = <&core_l4_ick>;
903 reg = <0x0a10>;
904 ti,bit-shift = <12>;
905 };
906
907 gpt10_ick: gpt10_ick {
908 #clock-cells = <0>;
909 compatible = "ti,omap3-interface-clock";
910 clocks = <&core_l4_ick>;
911 reg = <0x0a10>;
912 ti,bit-shift = <11>;
913 };
914
915 mcbsp5_ick: mcbsp5_ick {
916 #clock-cells = <0>;
917 compatible = "ti,omap3-interface-clock";
918 clocks = <&core_l4_ick>;
919 reg = <0x0a10>;
920 ti,bit-shift = <10>;
921 };
922
923 mcbsp1_ick: mcbsp1_ick {
924 #clock-cells = <0>;
925 compatible = "ti,omap3-interface-clock";
926 clocks = <&core_l4_ick>;
927 reg = <0x0a10>;
928 ti,bit-shift = <9>;
929 };
930
931 omapctrl_ick: omapctrl_ick {
932 #clock-cells = <0>;
933 compatible = "ti,omap3-interface-clock";
934 clocks = <&core_l4_ick>;
935 reg = <0x0a10>;
936 ti,bit-shift = <6>;
937 };
938
939 dss_tv_fck: dss_tv_fck {
940 #clock-cells = <0>;
941 compatible = "ti,gate-clock";
942 clocks = <&omap_54m_fck>;
943 reg = <0x0e00>;
944 ti,bit-shift = <2>;
945 };
946
947 dss_96m_fck: dss_96m_fck {
948 #clock-cells = <0>;
949 compatible = "ti,gate-clock";
950 clocks = <&omap_96m_fck>;
951 reg = <0x0e00>;
952 ti,bit-shift = <2>;
953 };
954
955 dss2_alwon_fck: dss2_alwon_fck {
956 #clock-cells = <0>;
957 compatible = "ti,gate-clock";
958 clocks = <&sys_ck>;
959 reg = <0x0e00>;
960 ti,bit-shift = <1>;
961 };
962
963 dummy_ck: dummy_ck {
964 #clock-cells = <0>;
965 compatible = "fixed-clock";
966 clock-frequency = <0>;
967 };
968
969 gpt1_gate_fck: gpt1_gate_fck {
970 #clock-cells = <0>;
971 compatible = "ti,composite-gate-clock";
972 clocks = <&sys_ck>;
973 ti,bit-shift = <0>;
974 reg = <0x0c00>;
975 };
976
977 gpt1_mux_fck: gpt1_mux_fck {
978 #clock-cells = <0>;
979 compatible = "ti,composite-mux-clock";
980 clocks = <&omap_32k_fck>, <&sys_ck>;
981 reg = <0x0c40>;
982 };
983
984 gpt1_fck: gpt1_fck {
985 #clock-cells = <0>;
986 compatible = "ti,composite-clock";
987 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
988 };
989
990 aes2_ick: aes2_ick {
991 #clock-cells = <0>;
992 compatible = "ti,omap3-interface-clock";
993 clocks = <&core_l4_ick>;
994 ti,bit-shift = <28>;
995 reg = <0x0a10>;
996 };
997
998 wkup_32k_fck: wkup_32k_fck {
999 #clock-cells = <0>;
1000 compatible = "fixed-factor-clock";
1001 clocks = <&omap_32k_fck>;
1002 clock-mult = <1>;
1003 clock-div = <1>;
1004 };
1005
1006 gpio1_dbck: gpio1_dbck {
1007 #clock-cells = <0>;
1008 compatible = "ti,gate-clock";
1009 clocks = <&wkup_32k_fck>;
1010 reg = <0x0c00>;
1011 ti,bit-shift = <3>;
1012 };
1013
1014 sha12_ick: sha12_ick {
1015 #clock-cells = <0>;
1016 compatible = "ti,omap3-interface-clock";
1017 clocks = <&core_l4_ick>;
1018 reg = <0x0a10>;
1019 ti,bit-shift = <27>;
1020 };
1021
1022 wdt2_fck: wdt2_fck {
1023 #clock-cells = <0>;
1024 compatible = "ti,wait-gate-clock";
1025 clocks = <&wkup_32k_fck>;
1026 reg = <0x0c00>;
1027 ti,bit-shift = <5>;
1028 };
1029
1030 wdt2_ick: wdt2_ick {
1031 #clock-cells = <0>;
1032 compatible = "ti,omap3-interface-clock";
1033 clocks = <&wkup_l4_ick>;
1034 reg = <0x0c10>;
1035 ti,bit-shift = <5>;
1036 };
1037
1038 wdt1_ick: wdt1_ick {
1039 #clock-cells = <0>;
1040 compatible = "ti,omap3-interface-clock";
1041 clocks = <&wkup_l4_ick>;
1042 reg = <0x0c10>;
1043 ti,bit-shift = <4>;
1044 };
1045
1046 gpio1_ick: gpio1_ick {
1047 #clock-cells = <0>;
1048 compatible = "ti,omap3-interface-clock";
1049 clocks = <&wkup_l4_ick>;
1050 reg = <0x0c10>;
1051 ti,bit-shift = <3>;
1052 };
1053
1054 omap_32ksync_ick: omap_32ksync_ick {
1055 #clock-cells = <0>;
1056 compatible = "ti,omap3-interface-clock";
1057 clocks = <&wkup_l4_ick>;
1058 reg = <0x0c10>;
1059 ti,bit-shift = <2>;
1060 };
1061
1062 gpt12_ick: gpt12_ick {
1063 #clock-cells = <0>;
1064 compatible = "ti,omap3-interface-clock";
1065 clocks = <&wkup_l4_ick>;
1066 reg = <0x0c10>;
1067 ti,bit-shift = <1>;
1068 };
1069
1070 gpt1_ick: gpt1_ick {
1071 #clock-cells = <0>;
1072 compatible = "ti,omap3-interface-clock";
1073 clocks = <&wkup_l4_ick>;
1074 reg = <0x0c10>;
1075 ti,bit-shift = <0>;
1076 };
1077
1078 per_96m_fck: per_96m_fck {
1079 #clock-cells = <0>;
1080 compatible = "fixed-factor-clock";
1081 clocks = <&omap_96m_alwon_fck>;
1082 clock-mult = <1>;
1083 clock-div = <1>;
1084 };
1085
1086 per_48m_fck: per_48m_fck {
1087 #clock-cells = <0>;
1088 compatible = "fixed-factor-clock";
1089 clocks = <&omap_48m_fck>;
1090 clock-mult = <1>;
1091 clock-div = <1>;
1092 };
1093
1094 uart3_fck: uart3_fck {
1095 #clock-cells = <0>;
1096 compatible = "ti,wait-gate-clock";
1097 clocks = <&per_48m_fck>;
1098 reg = <0x1000>;
1099 ti,bit-shift = <11>;
1100 };
1101
1102 gpt2_gate_fck: gpt2_gate_fck {
1103 #clock-cells = <0>;
1104 compatible = "ti,composite-gate-clock";
1105 clocks = <&sys_ck>;
1106 ti,bit-shift = <3>;
1107 reg = <0x1000>;
1108 };
1109
1110 gpt2_mux_fck: gpt2_mux_fck {
1111 #clock-cells = <0>;
1112 compatible = "ti,composite-mux-clock";
1113 clocks = <&omap_32k_fck>, <&sys_ck>;
1114 reg = <0x1040>;
1115 };
1116
1117 gpt2_fck: gpt2_fck {
1118 #clock-cells = <0>;
1119 compatible = "ti,composite-clock";
1120 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
1121 };
1122
1123 gpt3_gate_fck: gpt3_gate_fck {
1124 #clock-cells = <0>;
1125 compatible = "ti,composite-gate-clock";
1126 clocks = <&sys_ck>;
1127 ti,bit-shift = <4>;
1128 reg = <0x1000>;
1129 };
1130
1131 gpt3_mux_fck: gpt3_mux_fck {
1132 #clock-cells = <0>;
1133 compatible = "ti,composite-mux-clock";
1134 clocks = <&omap_32k_fck>, <&sys_ck>;
1135 ti,bit-shift = <1>;
1136 reg = <0x1040>;
1137 };
1138
1139 gpt3_fck: gpt3_fck {
1140 #clock-cells = <0>;
1141 compatible = "ti,composite-clock";
1142 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
1143 };
1144
1145 gpt4_gate_fck: gpt4_gate_fck {
1146 #clock-cells = <0>;
1147 compatible = "ti,composite-gate-clock";
1148 clocks = <&sys_ck>;
1149 ti,bit-shift = <5>;
1150 reg = <0x1000>;
1151 };
1152
1153 gpt4_mux_fck: gpt4_mux_fck {
1154 #clock-cells = <0>;
1155 compatible = "ti,composite-mux-clock";
1156 clocks = <&omap_32k_fck>, <&sys_ck>;
1157 ti,bit-shift = <2>;
1158 reg = <0x1040>;
1159 };
1160
1161 gpt4_fck: gpt4_fck {
1162 #clock-cells = <0>;
1163 compatible = "ti,composite-clock";
1164 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
1165 };
1166
1167 gpt5_gate_fck: gpt5_gate_fck {
1168 #clock-cells = <0>;
1169 compatible = "ti,composite-gate-clock";
1170 clocks = <&sys_ck>;
1171 ti,bit-shift = <6>;
1172 reg = <0x1000>;
1173 };
1174
1175 gpt5_mux_fck: gpt5_mux_fck {
1176 #clock-cells = <0>;
1177 compatible = "ti,composite-mux-clock";
1178 clocks = <&omap_32k_fck>, <&sys_ck>;
1179 ti,bit-shift = <3>;
1180 reg = <0x1040>;
1181 };
1182
1183 gpt5_fck: gpt5_fck {
1184 #clock-cells = <0>;
1185 compatible = "ti,composite-clock";
1186 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
1187 };
1188
1189 gpt6_gate_fck: gpt6_gate_fck {
1190 #clock-cells = <0>;
1191 compatible = "ti,composite-gate-clock";
1192 clocks = <&sys_ck>;
1193 ti,bit-shift = <7>;
1194 reg = <0x1000>;
1195 };
1196
1197 gpt6_mux_fck: gpt6_mux_fck {
1198 #clock-cells = <0>;
1199 compatible = "ti,composite-mux-clock";
1200 clocks = <&omap_32k_fck>, <&sys_ck>;
1201 ti,bit-shift = <4>;
1202 reg = <0x1040>;
1203 };
1204
1205 gpt6_fck: gpt6_fck {
1206 #clock-cells = <0>;
1207 compatible = "ti,composite-clock";
1208 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
1209 };
1210
1211 gpt7_gate_fck: gpt7_gate_fck {
1212 #clock-cells = <0>;
1213 compatible = "ti,composite-gate-clock";
1214 clocks = <&sys_ck>;
1215 ti,bit-shift = <8>;
1216 reg = <0x1000>;
1217 };
1218
1219 gpt7_mux_fck: gpt7_mux_fck {
1220 #clock-cells = <0>;
1221 compatible = "ti,composite-mux-clock";
1222 clocks = <&omap_32k_fck>, <&sys_ck>;
1223 ti,bit-shift = <5>;
1224 reg = <0x1040>;
1225 };
1226
1227 gpt7_fck: gpt7_fck {
1228 #clock-cells = <0>;
1229 compatible = "ti,composite-clock";
1230 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
1231 };
1232
1233 gpt8_gate_fck: gpt8_gate_fck {
1234 #clock-cells = <0>;
1235 compatible = "ti,composite-gate-clock";
1236 clocks = <&sys_ck>;
1237 ti,bit-shift = <9>;
1238 reg = <0x1000>;
1239 };
1240
1241 gpt8_mux_fck: gpt8_mux_fck {
1242 #clock-cells = <0>;
1243 compatible = "ti,composite-mux-clock";
1244 clocks = <&omap_32k_fck>, <&sys_ck>;
1245 ti,bit-shift = <6>;
1246 reg = <0x1040>;
1247 };
1248
1249 gpt8_fck: gpt8_fck {
1250 #clock-cells = <0>;
1251 compatible = "ti,composite-clock";
1252 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
1253 };
1254
1255 gpt9_gate_fck: gpt9_gate_fck {
1256 #clock-cells = <0>;
1257 compatible = "ti,composite-gate-clock";
1258 clocks = <&sys_ck>;
1259 ti,bit-shift = <10>;
1260 reg = <0x1000>;
1261 };
1262
1263 gpt9_mux_fck: gpt9_mux_fck {
1264 #clock-cells = <0>;
1265 compatible = "ti,composite-mux-clock";
1266 clocks = <&omap_32k_fck>, <&sys_ck>;
1267 ti,bit-shift = <7>;
1268 reg = <0x1040>;
1269 };
1270
1271 gpt9_fck: gpt9_fck {
1272 #clock-cells = <0>;
1273 compatible = "ti,composite-clock";
1274 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
1275 };
1276
1277 per_32k_alwon_fck: per_32k_alwon_fck {
1278 #clock-cells = <0>;
1279 compatible = "fixed-factor-clock";
1280 clocks = <&omap_32k_fck>;
1281 clock-mult = <1>;
1282 clock-div = <1>;
1283 };
1284
1285 gpio6_dbck: gpio6_dbck {
1286 #clock-cells = <0>;
1287 compatible = "ti,gate-clock";
1288 clocks = <&per_32k_alwon_fck>;
1289 reg = <0x1000>;
1290 ti,bit-shift = <17>;
1291 };
1292
1293 gpio5_dbck: gpio5_dbck {
1294 #clock-cells = <0>;
1295 compatible = "ti,gate-clock";
1296 clocks = <&per_32k_alwon_fck>;
1297 reg = <0x1000>;
1298 ti,bit-shift = <16>;
1299 };
1300
1301 gpio4_dbck: gpio4_dbck {
1302 #clock-cells = <0>;
1303 compatible = "ti,gate-clock";
1304 clocks = <&per_32k_alwon_fck>;
1305 reg = <0x1000>;
1306 ti,bit-shift = <15>;
1307 };
1308
1309 gpio3_dbck: gpio3_dbck {
1310 #clock-cells = <0>;
1311 compatible = "ti,gate-clock";
1312 clocks = <&per_32k_alwon_fck>;
1313 reg = <0x1000>;
1314 ti,bit-shift = <14>;
1315 };
1316
1317 gpio2_dbck: gpio2_dbck {
1318 #clock-cells = <0>;
1319 compatible = "ti,gate-clock";
1320 clocks = <&per_32k_alwon_fck>;
1321 reg = <0x1000>;
1322 ti,bit-shift = <13>;
1323 };
1324
1325 wdt3_fck: wdt3_fck {
1326 #clock-cells = <0>;
1327 compatible = "ti,wait-gate-clock";
1328 clocks = <&per_32k_alwon_fck>;
1329 reg = <0x1000>;
1330 ti,bit-shift = <12>;
1331 };
1332
1333 per_l4_ick: per_l4_ick {
1334 #clock-cells = <0>;
1335 compatible = "fixed-factor-clock";
1336 clocks = <&l4_ick>;
1337 clock-mult = <1>;
1338 clock-div = <1>;
1339 };
1340
1341 gpio6_ick: gpio6_ick {
1342 #clock-cells = <0>;
1343 compatible = "ti,omap3-interface-clock";
1344 clocks = <&per_l4_ick>;
1345 reg = <0x1010>;
1346 ti,bit-shift = <17>;
1347 };
1348
1349 gpio5_ick: gpio5_ick {
1350 #clock-cells = <0>;
1351 compatible = "ti,omap3-interface-clock";
1352 clocks = <&per_l4_ick>;
1353 reg = <0x1010>;
1354 ti,bit-shift = <16>;
1355 };
1356
1357 gpio4_ick: gpio4_ick {
1358 #clock-cells = <0>;
1359 compatible = "ti,omap3-interface-clock";
1360 clocks = <&per_l4_ick>;
1361 reg = <0x1010>;
1362 ti,bit-shift = <15>;
1363 };
1364
1365 gpio3_ick: gpio3_ick {
1366 #clock-cells = <0>;
1367 compatible = "ti,omap3-interface-clock";
1368 clocks = <&per_l4_ick>;
1369 reg = <0x1010>;
1370 ti,bit-shift = <14>;
1371 };
1372
1373 gpio2_ick: gpio2_ick {
1374 #clock-cells = <0>;
1375 compatible = "ti,omap3-interface-clock";
1376 clocks = <&per_l4_ick>;
1377 reg = <0x1010>;
1378 ti,bit-shift = <13>;
1379 };
1380
1381 wdt3_ick: wdt3_ick {
1382 #clock-cells = <0>;
1383 compatible = "ti,omap3-interface-clock";
1384 clocks = <&per_l4_ick>;
1385 reg = <0x1010>;
1386 ti,bit-shift = <12>;
1387 };
1388
1389 uart3_ick: uart3_ick {
1390 #clock-cells = <0>;
1391 compatible = "ti,omap3-interface-clock";
1392 clocks = <&per_l4_ick>;
1393 reg = <0x1010>;
1394 ti,bit-shift = <11>;
1395 };
1396
1397 uart4_ick: uart4_ick {
1398 #clock-cells = <0>;
1399 compatible = "ti,omap3-interface-clock";
1400 clocks = <&per_l4_ick>;
1401 reg = <0x1010>;
1402 ti,bit-shift = <18>;
1403 };
1404
1405 gpt9_ick: gpt9_ick {
1406 #clock-cells = <0>;
1407 compatible = "ti,omap3-interface-clock";
1408 clocks = <&per_l4_ick>;
1409 reg = <0x1010>;
1410 ti,bit-shift = <10>;
1411 };
1412
1413 gpt8_ick: gpt8_ick {
1414 #clock-cells = <0>;
1415 compatible = "ti,omap3-interface-clock";
1416 clocks = <&per_l4_ick>;
1417 reg = <0x1010>;
1418 ti,bit-shift = <9>;
1419 };
1420
1421 gpt7_ick: gpt7_ick {
1422 #clock-cells = <0>;
1423 compatible = "ti,omap3-interface-clock";
1424 clocks = <&per_l4_ick>;
1425 reg = <0x1010>;
1426 ti,bit-shift = <8>;
1427 };
1428
1429 gpt6_ick: gpt6_ick {
1430 #clock-cells = <0>;
1431 compatible = "ti,omap3-interface-clock";
1432 clocks = <&per_l4_ick>;
1433 reg = <0x1010>;
1434 ti,bit-shift = <7>;
1435 };
1436
1437 gpt5_ick: gpt5_ick {
1438 #clock-cells = <0>;
1439 compatible = "ti,omap3-interface-clock";
1440 clocks = <&per_l4_ick>;
1441 reg = <0x1010>;
1442 ti,bit-shift = <6>;
1443 };
1444
1445 gpt4_ick: gpt4_ick {
1446 #clock-cells = <0>;
1447 compatible = "ti,omap3-interface-clock";
1448 clocks = <&per_l4_ick>;
1449 reg = <0x1010>;
1450 ti,bit-shift = <5>;
1451 };
1452
1453 gpt3_ick: gpt3_ick {
1454 #clock-cells = <0>;
1455 compatible = "ti,omap3-interface-clock";
1456 clocks = <&per_l4_ick>;
1457 reg = <0x1010>;
1458 ti,bit-shift = <4>;
1459 };
1460
1461 gpt2_ick: gpt2_ick {
1462 #clock-cells = <0>;
1463 compatible = "ti,omap3-interface-clock";
1464 clocks = <&per_l4_ick>;
1465 reg = <0x1010>;
1466 ti,bit-shift = <3>;
1467 };
1468
1469 mcbsp2_ick: mcbsp2_ick {
1470 #clock-cells = <0>;
1471 compatible = "ti,omap3-interface-clock";
1472 clocks = <&per_l4_ick>;
1473 reg = <0x1010>;
1474 ti,bit-shift = <0>;
1475 };
1476
1477 mcbsp3_ick: mcbsp3_ick {
1478 #clock-cells = <0>;
1479 compatible = "ti,omap3-interface-clock";
1480 clocks = <&per_l4_ick>;
1481 reg = <0x1010>;
1482 ti,bit-shift = <1>;
1483 };
1484
1485 mcbsp4_ick: mcbsp4_ick {
1486 #clock-cells = <0>;
1487 compatible = "ti,omap3-interface-clock";
1488 clocks = <&per_l4_ick>;
1489 reg = <0x1010>;
1490 ti,bit-shift = <2>;
1491 };
1492
1493 mcbsp2_gate_fck: mcbsp2_gate_fck {
1494 #clock-cells = <0>;
1495 compatible = "ti,composite-gate-clock";
1496 clocks = <&mcbsp_clks>;
1497 ti,bit-shift = <0>;
1498 reg = <0x1000>;
1499 };
1500
1501 mcbsp3_gate_fck: mcbsp3_gate_fck {
1502 #clock-cells = <0>;
1503 compatible = "ti,composite-gate-clock";
1504 clocks = <&mcbsp_clks>;
1505 ti,bit-shift = <1>;
1506 reg = <0x1000>;
1507 };
1508
1509 mcbsp4_gate_fck: mcbsp4_gate_fck {
1510 #clock-cells = <0>;
1511 compatible = "ti,composite-gate-clock";
1512 clocks = <&mcbsp_clks>;
1513 ti,bit-shift = <2>;
1514 reg = <0x1000>;
1515 };
1516
1517 emu_src_mux_ck: emu_src_mux_ck {
1518 #clock-cells = <0>;
1519 compatible = "ti,mux-clock";
1520 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1521 reg = <0x1140>;
1522 };
1523
1524 emu_src_ck: emu_src_ck {
1525 #clock-cells = <0>;
1526 compatible = "ti,clkdm-gate-clock";
1527 clocks = <&emu_src_mux_ck>;
1528 };
1529
1530 pclk_fck: pclk_fck {
1531 #clock-cells = <0>;
1532 compatible = "ti,divider-clock";
1533 clocks = <&emu_src_ck>;
1534 ti,bit-shift = <8>;
1535 ti,max-div = <7>;
1536 reg = <0x1140>;
1537 ti,index-starts-at-one;
1538 };
1539
1540 pclkx2_fck: pclkx2_fck {
1541 #clock-cells = <0>;
1542 compatible = "ti,divider-clock";
1543 clocks = <&emu_src_ck>;
1544 ti,bit-shift = <6>;
1545 ti,max-div = <3>;
1546 reg = <0x1140>;
1547 ti,index-starts-at-one;
1548 };
1549
1550 atclk_fck: atclk_fck {
1551 #clock-cells = <0>;
1552 compatible = "ti,divider-clock";
1553 clocks = <&emu_src_ck>;
1554 ti,bit-shift = <4>;
1555 ti,max-div = <3>;
1556 reg = <0x1140>;
1557 ti,index-starts-at-one;
1558 };
1559
1560 traceclk_src_fck: traceclk_src_fck {
1561 #clock-cells = <0>;
1562 compatible = "ti,mux-clock";
1563 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
1564 ti,bit-shift = <2>;
1565 reg = <0x1140>;
1566 };
1567
1568 traceclk_fck: traceclk_fck {
1569 #clock-cells = <0>;
1570 compatible = "ti,divider-clock";
1571 clocks = <&traceclk_src_fck>;
1572 ti,bit-shift = <11>;
1573 ti,max-div = <7>;
1574 reg = <0x1140>;
1575 ti,index-starts-at-one;
1576 };
1577
1578 secure_32k_fck: secure_32k_fck {
1579 #clock-cells = <0>;
1580 compatible = "fixed-clock";
1581 clock-frequency = <32768>;
1582 };
1583
1584 gpt12_fck: gpt12_fck {
1585 #clock-cells = <0>;
1586 compatible = "fixed-factor-clock";
1587 clocks = <&secure_32k_fck>;
1588 clock-mult = <1>;
1589 clock-div = <1>;
1590 };
1591
1592 wdt1_fck: wdt1_fck {
1593 #clock-cells = <0>;
1594 compatible = "fixed-factor-clock";
1595 clocks = <&secure_32k_fck>;
1596 clock-mult = <1>;
1597 clock-div = <1>;
1598 };
1599};
1600
1601&cm_clockdomains {
1602 core_l3_clkdm: core_l3_clkdm {
1603 compatible = "ti,clockdomain";
1604 clocks = <&sdrc_ick>;
1605 };
1606
1607 dpll3_clkdm: dpll3_clkdm {
1608 compatible = "ti,clockdomain";
1609 clocks = <&dpll3_ck>;
1610 };
1611
1612 dpll1_clkdm: dpll1_clkdm {
1613 compatible = "ti,clockdomain";
1614 clocks = <&dpll1_ck>;
1615 };
1616
1617 per_clkdm: per_clkdm {
1618 compatible = "ti,clockdomain";
1619 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
1620 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
1621 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
1622 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
1623 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
1624 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
1625 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
1626 <&mcbsp4_ick>;
1627 };
1628
1629 emu_clkdm: emu_clkdm {
1630 compatible = "ti,clockdomain";
1631 clocks = <&emu_src_ck>;
1632 };
1633
1634 dpll4_clkdm: dpll4_clkdm {
1635 compatible = "ti,clockdomain";
1636 clocks = <&dpll4_ck>;
1637 };
1638
1639 wkup_clkdm: wkup_clkdm {
1640 compatible = "ti,clockdomain";
1641 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
1642 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
1643 <&gpt1_ick>;
1644 };
1645
1646 dss_clkdm: dss_clkdm {
1647 compatible = "ti,clockdomain";
1648 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
1649 };
1650
1651 core_l4_clkdm: core_l4_clkdm {
1652 compatible = "ti,clockdomain";
1653 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
1654 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
1655 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
1656 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
1657 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
1658 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
1659 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
1660 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
1661 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
1662 };
1663};
ubuntu-bionic-kernel mirror