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Commit | Line | Data |
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d9fda07a BC |
1 | /* |
2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
6d624eab | 9 | #include <dt-bindings/gpio/gpio.h> |
8fea7d5a | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
bcd3cca7 | 11 | #include <dt-bindings/pinctrl/omap.h> |
d9fda07a | 12 | |
d9fda07a BC |
13 | / { |
14 | compatible = "ti,omap4430", "ti,omap4"; | |
7136d457 | 15 | interrupt-parent = <&wakeupgen>; |
da6269e7 JMC |
16 | #address-cells = <1>; |
17 | #size-cells = <1>; | |
6c565d1a | 18 | chosen { }; |
d9fda07a BC |
19 | |
20 | aliases { | |
20b80942 NM |
21 | i2c0 = &i2c1; |
22 | i2c1 = &i2c2; | |
23 | i2c2 = &i2c3; | |
24 | i2c3 = &i2c4; | |
cf3c79de RN |
25 | serial0 = &uart1; |
26 | serial1 = &uart2; | |
27 | serial2 = &uart3; | |
28 | serial3 = &uart4; | |
d9fda07a BC |
29 | }; |
30 | ||
476b679a | 31 | cpus { |
eeb25fd5 LP |
32 | #address-cells = <1>; |
33 | #size-cells = <0>; | |
34 | ||
476b679a BC |
35 | cpu@0 { |
36 | compatible = "arm,cortex-a9"; | |
eeb25fd5 | 37 | device_type = "cpu"; |
926fd45b | 38 | next-level-cache = <&L2>; |
eeb25fd5 | 39 | reg = <0x0>; |
8d766fa2 NM |
40 | |
41 | clocks = <&dpll_mpu_ck>; | |
42 | clock-names = "cpu"; | |
43 | ||
44 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
476b679a BC |
45 | }; |
46 | cpu@1 { | |
47 | compatible = "arm,cortex-a9"; | |
eeb25fd5 | 48 | device_type = "cpu"; |
926fd45b | 49 | next-level-cache = <&L2>; |
eeb25fd5 | 50 | reg = <0x1>; |
476b679a BC |
51 | }; |
52 | }; | |
53 | ||
5635121e BC |
54 | gic: interrupt-controller@48241000 { |
55 | compatible = "arm,cortex-a9-gic"; | |
56 | interrupt-controller; | |
57 | #interrupt-cells = <3>; | |
58 | reg = <0x48241000 0x1000>, | |
59 | <0x48240100 0x0100>; | |
7136d457 | 60 | interrupt-parent = <&gic>; |
5635121e BC |
61 | }; |
62 | ||
926fd45b SS |
63 | L2: l2-cache-controller@48242000 { |
64 | compatible = "arm,pl310-cache"; | |
65 | reg = <0x48242000 0x1000>; | |
66 | cache-unified; | |
67 | cache-level = <2>; | |
68 | }; | |
69 | ||
75d71d46 | 70 | local-timer@48240600 { |
eed0de27 | 71 | compatible = "arm,cortex-a9-twd-timer"; |
23c47378 | 72 | clocks = <&mpu_periphclk>; |
eed0de27 | 73 | reg = <0x48240600 0x20>; |
6b472574 | 74 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>; |
7136d457 MZ |
75 | interrupt-parent = <&gic>; |
76 | }; | |
77 | ||
78 | wakeupgen: interrupt-controller@48281000 { | |
79 | compatible = "ti,omap4-wugen-mpu"; | |
80 | interrupt-controller; | |
81 | #interrupt-cells = <3>; | |
82 | reg = <0x48281000 0x1000>; | |
83 | interrupt-parent = <&gic>; | |
eed0de27 SS |
84 | }; |
85 | ||
d9fda07a | 86 | /* |
5c5be9db | 87 | * The soc node represents the soc top level view. It is used for IPs |
d9fda07a BC |
88 | * that are not memory mapped in the MPU view or for the MPU itself. |
89 | */ | |
90 | soc { | |
91 | compatible = "ti,omap-infra"; | |
476b679a BC |
92 | mpu { |
93 | compatible = "ti,omap4-mpu"; | |
94 | ti,hwmods = "mpu"; | |
1306c08a | 95 | sram = <&ocmcram>; |
476b679a BC |
96 | }; |
97 | ||
98 | dsp { | |
99 | compatible = "ti,omap3-c64"; | |
100 | ti,hwmods = "dsp"; | |
101 | }; | |
102 | ||
103 | iva { | |
104 | compatible = "ti,ivahd"; | |
105 | ti,hwmods = "iva"; | |
106 | }; | |
d9fda07a BC |
107 | }; |
108 | ||
109 | /* | |
110 | * XXX: Use a flat representation of the OMAP4 interconnect. | |
111 | * The real OMAP interconnect network is quite complex. | |
b7ab524b | 112 | * Since it will not bring real advantage to represent that in DT for |
d9fda07a BC |
113 | * the moment, just use a fake OCP bus entry to represent the whole bus |
114 | * hierarchy. | |
115 | */ | |
116 | ocp { | |
ad8dfac6 | 117 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
d9fda07a BC |
118 | #address-cells = <1>; |
119 | #size-cells = <1>; | |
120 | ranges; | |
ad8dfac6 | 121 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
20a60eaa SS |
122 | reg = <0x44000000 0x1000>, |
123 | <0x44800000 0x2000>, | |
124 | <0x45000000 0x1000>; | |
8fea7d5a FV |
125 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
126 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
d9fda07a | 127 | |
7415b0b4 TK |
128 | l4_cfg: l4@4a000000 { |
129 | compatible = "ti,omap4-l4-cfg", "simple-bus"; | |
130 | #address-cells = <1>; | |
131 | #size-cells = <1>; | |
132 | ranges = <0 0x4a000000 0x1000000>; | |
2488ff6c | 133 | |
7415b0b4 TK |
134 | cm1: cm1@4000 { |
135 | compatible = "ti,omap4-cm1"; | |
136 | reg = <0x4000 0x2000>; | |
2488ff6c | 137 | |
7415b0b4 TK |
138 | cm1_clocks: clocks { |
139 | #address-cells = <1>; | |
140 | #size-cells = <0>; | |
141 | }; | |
2488ff6c | 142 | |
7415b0b4 TK |
143 | cm1_clockdomains: clockdomains { |
144 | }; | |
2488ff6c TK |
145 | }; |
146 | ||
7415b0b4 TK |
147 | cm2: cm2@8000 { |
148 | compatible = "ti,omap4-cm2"; | |
149 | reg = <0x8000 0x3000>; | |
2488ff6c | 150 | |
7415b0b4 TK |
151 | cm2_clocks: clocks { |
152 | #address-cells = <1>; | |
153 | #size-cells = <0>; | |
154 | }; | |
2488ff6c | 155 | |
7415b0b4 TK |
156 | cm2_clockdomains: clockdomains { |
157 | }; | |
2488ff6c | 158 | }; |
2488ff6c | 159 | |
7415b0b4 TK |
160 | omap4_scm_core: scm@2000 { |
161 | compatible = "ti,omap4-scm-core", "simple-bus"; | |
162 | reg = <0x2000 0x1000>; | |
2488ff6c | 163 | #address-cells = <1>; |
7415b0b4 TK |
164 | #size-cells = <1>; |
165 | ranges = <0 0x2000 0x1000>; | |
166 | ||
167 | scm_conf: scm_conf@0 { | |
168 | compatible = "syscon"; | |
169 | reg = <0x0 0x800>; | |
170 | #address-cells = <1>; | |
171 | #size-cells = <1>; | |
172 | }; | |
2488ff6c TK |
173 | }; |
174 | ||
7415b0b4 TK |
175 | omap4_padconf_core: scm@100000 { |
176 | compatible = "ti,omap4-scm-padconf-core", | |
177 | "simple-bus"; | |
178 | #address-cells = <1>; | |
179 | #size-cells = <1>; | |
180 | ranges = <0 0x100000 0x1000>; | |
181 | ||
182 | omap4_pmx_core: pinmux@40 { | |
183 | compatible = "ti,omap4-padconf", | |
184 | "pinctrl-single"; | |
185 | reg = <0x40 0x0196>; | |
186 | #address-cells = <1>; | |
187 | #size-cells = <0>; | |
be76fd31 | 188 | #pinctrl-cells = <1>; |
7415b0b4 TK |
189 | #interrupt-cells = <1>; |
190 | interrupt-controller; | |
191 | pinctrl-single,register-width = <16>; | |
192 | pinctrl-single,function-mask = <0x7fff>; | |
193 | }; | |
194 | ||
195 | omap4_padconf_global: omap4_padconf_global@5a0 { | |
89a898df KVA |
196 | compatible = "syscon", |
197 | "simple-bus"; | |
7415b0b4 TK |
198 | reg = <0x5a0 0x170>; |
199 | #address-cells = <1>; | |
200 | #size-cells = <1>; | |
9a5e3f27 | 201 | ranges = <0 0x5a0 0x170>; |
7415b0b4 | 202 | |
308cfdaf | 203 | pbias_regulator: pbias_regulator@60 { |
737f146f | 204 | compatible = "ti,pbias-omap4", "ti,pbias-omap"; |
7415b0b4 TK |
205 | reg = <0x60 0x4>; |
206 | syscon = <&omap4_padconf_global>; | |
207 | pbias_mmc_reg: pbias_mmc_omap4 { | |
208 | regulator-name = "pbias_mmc_omap4"; | |
209 | regulator-min-microvolt = <1800000>; | |
210 | regulator-max-microvolt = <3000000>; | |
211 | }; | |
212 | }; | |
213 | }; | |
2488ff6c | 214 | }; |
2488ff6c | 215 | |
7415b0b4 TK |
216 | l4_wkup: l4@300000 { |
217 | compatible = "ti,omap4-l4-wkup", "simple-bus"; | |
218 | #address-cells = <1>; | |
219 | #size-cells = <1>; | |
220 | ranges = <0 0x300000 0x40000>; | |
221 | ||
222 | counter32k: counter@4000 { | |
223 | compatible = "ti,omap-counter32k"; | |
224 | reg = <0x4000 0x20>; | |
225 | ti,hwmods = "counter_32k"; | |
226 | }; | |
227 | ||
228 | prm: prm@6000 { | |
229 | compatible = "ti,omap4-prm"; | |
230 | reg = <0x6000 0x3000>; | |
231 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
232 | ||
233 | prm_clocks: clocks { | |
234 | #address-cells = <1>; | |
235 | #size-cells = <0>; | |
236 | }; | |
237 | ||
238 | prm_clockdomains: clockdomains { | |
239 | }; | |
240 | }; | |
241 | ||
242 | scrm: scrm@a000 { | |
243 | compatible = "ti,omap4-scrm"; | |
244 | reg = <0xa000 0x2000>; | |
245 | ||
246 | scrm_clocks: clocks { | |
247 | #address-cells = <1>; | |
248 | #size-cells = <0>; | |
249 | }; | |
250 | ||
251 | scrm_clockdomains: clockdomains { | |
252 | }; | |
253 | }; | |
254 | ||
255 | omap4_pmx_wkup: pinmux@1e040 { | |
256 | compatible = "ti,omap4-padconf", | |
257 | "pinctrl-single"; | |
258 | reg = <0x1e040 0x0038>; | |
259 | #address-cells = <1>; | |
260 | #size-cells = <0>; | |
be76fd31 | 261 | #pinctrl-cells = <1>; |
7415b0b4 TK |
262 | #interrupt-cells = <1>; |
263 | interrupt-controller; | |
264 | pinctrl-single,register-width = <16>; | |
265 | pinctrl-single,function-mask = <0x7fff>; | |
266 | }; | |
cd042fe5 B |
267 | }; |
268 | }; | |
269 | ||
8b9a2810 RN |
270 | ocmcram: ocmcram@40304000 { |
271 | compatible = "mmio-sram"; | |
272 | reg = <0x40304000 0xa000>; /* 40k */ | |
273 | }; | |
274 | ||
2c2dc545 JH |
275 | sdma: dma-controller@4a056000 { |
276 | compatible = "ti,omap4430-sdma"; | |
277 | reg = <0x4a056000 0x1000>; | |
8fea7d5a FV |
278 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
279 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
280 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
281 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
2c2dc545 | 282 | #dma-cells = <1>; |
24ac1770 PU |
283 | dma-channels = <32>; |
284 | dma-requests = <127>; | |
2c2dc545 JH |
285 | }; |
286 | ||
e3e5a92d BC |
287 | gpio1: gpio@4a310000 { |
288 | compatible = "ti,omap4-gpio"; | |
48420dbc | 289 | reg = <0x4a310000 0x200>; |
8fea7d5a | 290 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d | 291 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 292 | ti,gpio-always-on; |
e3e5a92d BC |
293 | gpio-controller; |
294 | #gpio-cells = <2>; | |
295 | interrupt-controller; | |
ff5c9059 | 296 | #interrupt-cells = <2>; |
e3e5a92d BC |
297 | }; |
298 | ||
299 | gpio2: gpio@48055000 { | |
300 | compatible = "ti,omap4-gpio"; | |
48420dbc | 301 | reg = <0x48055000 0x200>; |
8fea7d5a | 302 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d BC |
303 | ti,hwmods = "gpio2"; |
304 | gpio-controller; | |
305 | #gpio-cells = <2>; | |
306 | interrupt-controller; | |
ff5c9059 | 307 | #interrupt-cells = <2>; |
e3e5a92d BC |
308 | }; |
309 | ||
310 | gpio3: gpio@48057000 { | |
311 | compatible = "ti,omap4-gpio"; | |
48420dbc | 312 | reg = <0x48057000 0x200>; |
8fea7d5a | 313 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d BC |
314 | ti,hwmods = "gpio3"; |
315 | gpio-controller; | |
316 | #gpio-cells = <2>; | |
317 | interrupt-controller; | |
ff5c9059 | 318 | #interrupt-cells = <2>; |
e3e5a92d BC |
319 | }; |
320 | ||
321 | gpio4: gpio@48059000 { | |
322 | compatible = "ti,omap4-gpio"; | |
48420dbc | 323 | reg = <0x48059000 0x200>; |
8fea7d5a | 324 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d BC |
325 | ti,hwmods = "gpio4"; |
326 | gpio-controller; | |
327 | #gpio-cells = <2>; | |
328 | interrupt-controller; | |
ff5c9059 | 329 | #interrupt-cells = <2>; |
e3e5a92d BC |
330 | }; |
331 | ||
332 | gpio5: gpio@4805b000 { | |
333 | compatible = "ti,omap4-gpio"; | |
48420dbc | 334 | reg = <0x4805b000 0x200>; |
8fea7d5a | 335 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d BC |
336 | ti,hwmods = "gpio5"; |
337 | gpio-controller; | |
338 | #gpio-cells = <2>; | |
339 | interrupt-controller; | |
ff5c9059 | 340 | #interrupt-cells = <2>; |
e3e5a92d BC |
341 | }; |
342 | ||
343 | gpio6: gpio@4805d000 { | |
344 | compatible = "ti,omap4-gpio"; | |
48420dbc | 345 | reg = <0x4805d000 0x200>; |
8fea7d5a | 346 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
e3e5a92d BC |
347 | ti,hwmods = "gpio6"; |
348 | gpio-controller; | |
349 | #gpio-cells = <2>; | |
350 | interrupt-controller; | |
ff5c9059 | 351 | #interrupt-cells = <2>; |
e3e5a92d | 352 | }; |
cf3c79de | 353 | |
258511e1 FCJ |
354 | elm: elm@48078000 { |
355 | compatible = "ti,am3352-elm"; | |
356 | reg = <0x48078000 0x2000>; | |
357 | interrupts = <4>; | |
358 | ti,hwmods = "elm"; | |
359 | status = "disabled"; | |
360 | }; | |
361 | ||
1c7dbb55 JH |
362 | gpmc: gpmc@50000000 { |
363 | compatible = "ti,omap4430-gpmc"; | |
364 | reg = <0x50000000 0x1000>; | |
365 | #address-cells = <2>; | |
366 | #size-cells = <1>; | |
8fea7d5a | 367 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
201c7e33 FCJ |
368 | dmas = <&sdma 4>; |
369 | dma-names = "rxtx"; | |
1c7dbb55 JH |
370 | gpmc,num-cs = <8>; |
371 | gpmc,num-waitpins = <4>; | |
372 | ti,hwmods = "gpmc"; | |
f12ecbe2 | 373 | ti,no-idle-on-init; |
7b8b6af1 FV |
374 | clocks = <&l3_div_ck>; |
375 | clock-names = "fck"; | |
8c75b766 RQ |
376 | interrupt-controller; |
377 | #interrupt-cells = <2>; | |
378 | gpio-controller; | |
379 | #gpio-cells = <2>; | |
1c7dbb55 JH |
380 | }; |
381 | ||
19bfb76c | 382 | uart1: serial@4806a000 { |
cf3c79de | 383 | compatible = "ti,omap4-uart"; |
48420dbc | 384 | reg = <0x4806a000 0x100>; |
8fea7d5a | 385 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
cf3c79de RN |
386 | ti,hwmods = "uart1"; |
387 | clock-frequency = <48000000>; | |
388 | }; | |
389 | ||
19bfb76c | 390 | uart2: serial@4806c000 { |
cf3c79de | 391 | compatible = "ti,omap4-uart"; |
48420dbc | 392 | reg = <0x4806c000 0x100>; |
7136d457 | 393 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
cf3c79de RN |
394 | ti,hwmods = "uart2"; |
395 | clock-frequency = <48000000>; | |
396 | }; | |
397 | ||
19bfb76c | 398 | uart3: serial@48020000 { |
cf3c79de | 399 | compatible = "ti,omap4-uart"; |
48420dbc | 400 | reg = <0x48020000 0x100>; |
7136d457 | 401 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
cf3c79de RN |
402 | ti,hwmods = "uart3"; |
403 | clock-frequency = <48000000>; | |
404 | }; | |
405 | ||
19bfb76c | 406 | uart4: serial@4806e000 { |
cf3c79de | 407 | compatible = "ti,omap4-uart"; |
48420dbc | 408 | reg = <0x4806e000 0x100>; |
7136d457 | 409 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
cf3c79de RN |
410 | ti,hwmods = "uart4"; |
411 | clock-frequency = <48000000>; | |
412 | }; | |
58e778f9 | 413 | |
04c7d924 SA |
414 | hwspinlock: spinlock@4a0f6000 { |
415 | compatible = "ti,omap4-hwspinlock"; | |
416 | reg = <0x4a0f6000 0x1000>; | |
417 | ti,hwmods = "spinlock"; | |
34054213 | 418 | #hwlock-cells = <1>; |
04c7d924 SA |
419 | }; |
420 | ||
58e778f9 BC |
421 | i2c1: i2c@48070000 { |
422 | compatible = "ti,omap4-i2c"; | |
48420dbc | 423 | reg = <0x48070000 0x100>; |
8fea7d5a | 424 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
58e778f9 BC |
425 | #address-cells = <1>; |
426 | #size-cells = <0>; | |
427 | ti,hwmods = "i2c1"; | |
428 | }; | |
429 | ||
430 | i2c2: i2c@48072000 { | |
431 | compatible = "ti,omap4-i2c"; | |
48420dbc | 432 | reg = <0x48072000 0x100>; |
8fea7d5a | 433 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
58e778f9 BC |
434 | #address-cells = <1>; |
435 | #size-cells = <0>; | |
436 | ti,hwmods = "i2c2"; | |
437 | }; | |
438 | ||
439 | i2c3: i2c@48060000 { | |
440 | compatible = "ti,omap4-i2c"; | |
48420dbc | 441 | reg = <0x48060000 0x100>; |
8fea7d5a | 442 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
58e778f9 BC |
443 | #address-cells = <1>; |
444 | #size-cells = <0>; | |
445 | ti,hwmods = "i2c3"; | |
446 | }; | |
447 | ||
448 | i2c4: i2c@48350000 { | |
449 | compatible = "ti,omap4-i2c"; | |
48420dbc | 450 | reg = <0x48350000 0x100>; |
8fea7d5a | 451 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
58e778f9 BC |
452 | #address-cells = <1>; |
453 | #size-cells = <0>; | |
454 | ti,hwmods = "i2c4"; | |
455 | }; | |
efcf1e50 BC |
456 | |
457 | mcspi1: spi@48098000 { | |
458 | compatible = "ti,omap4-mcspi"; | |
48420dbc | 459 | reg = <0x48098000 0x200>; |
8fea7d5a | 460 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
efcf1e50 BC |
461 | #address-cells = <1>; |
462 | #size-cells = <0>; | |
463 | ti,hwmods = "mcspi1"; | |
464 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
465 | dmas = <&sdma 35>, |
466 | <&sdma 36>, | |
467 | <&sdma 37>, | |
468 | <&sdma 38>, | |
469 | <&sdma 39>, | |
470 | <&sdma 40>, | |
471 | <&sdma 41>, | |
472 | <&sdma 42>; | |
473 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
474 | "tx2", "rx2", "tx3", "rx3"; | |
efcf1e50 BC |
475 | }; |
476 | ||
477 | mcspi2: spi@4809a000 { | |
478 | compatible = "ti,omap4-mcspi"; | |
48420dbc | 479 | reg = <0x4809a000 0x200>; |
8fea7d5a | 480 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
efcf1e50 BC |
481 | #address-cells = <1>; |
482 | #size-cells = <0>; | |
483 | ti,hwmods = "mcspi2"; | |
484 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
485 | dmas = <&sdma 43>, |
486 | <&sdma 44>, | |
487 | <&sdma 45>, | |
488 | <&sdma 46>; | |
489 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
efcf1e50 BC |
490 | }; |
491 | ||
492 | mcspi3: spi@480b8000 { | |
493 | compatible = "ti,omap4-mcspi"; | |
48420dbc | 494 | reg = <0x480b8000 0x200>; |
8fea7d5a | 495 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
efcf1e50 BC |
496 | #address-cells = <1>; |
497 | #size-cells = <0>; | |
498 | ti,hwmods = "mcspi3"; | |
499 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
500 | dmas = <&sdma 15>, <&sdma 16>; |
501 | dma-names = "tx0", "rx0"; | |
efcf1e50 BC |
502 | }; |
503 | ||
504 | mcspi4: spi@480ba000 { | |
505 | compatible = "ti,omap4-mcspi"; | |
48420dbc | 506 | reg = <0x480ba000 0x200>; |
8fea7d5a | 507 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
efcf1e50 BC |
508 | #address-cells = <1>; |
509 | #size-cells = <0>; | |
510 | ti,hwmods = "mcspi4"; | |
511 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
512 | dmas = <&sdma 70>, <&sdma 71>; |
513 | dma-names = "tx0", "rx0"; | |
efcf1e50 | 514 | }; |
74981768 RN |
515 | |
516 | mmc1: mmc@4809c000 { | |
517 | compatible = "ti,omap4-hsmmc"; | |
48420dbc | 518 | reg = <0x4809c000 0x400>; |
8fea7d5a | 519 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
74981768 RN |
520 | ti,hwmods = "mmc1"; |
521 | ti,dual-volt; | |
522 | ti,needs-special-reset; | |
2c2dc545 JH |
523 | dmas = <&sdma 61>, <&sdma 62>; |
524 | dma-names = "tx", "rx"; | |
cd042fe5 | 525 | pbias-supply = <&pbias_mmc_reg>; |
74981768 RN |
526 | }; |
527 | ||
528 | mmc2: mmc@480b4000 { | |
529 | compatible = "ti,omap4-hsmmc"; | |
48420dbc | 530 | reg = <0x480b4000 0x400>; |
8fea7d5a | 531 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
74981768 RN |
532 | ti,hwmods = "mmc2"; |
533 | ti,needs-special-reset; | |
2c2dc545 JH |
534 | dmas = <&sdma 47>, <&sdma 48>; |
535 | dma-names = "tx", "rx"; | |
74981768 RN |
536 | }; |
537 | ||
538 | mmc3: mmc@480ad000 { | |
539 | compatible = "ti,omap4-hsmmc"; | |
48420dbc | 540 | reg = <0x480ad000 0x400>; |
8fea7d5a | 541 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
74981768 RN |
542 | ti,hwmods = "mmc3"; |
543 | ti,needs-special-reset; | |
2c2dc545 JH |
544 | dmas = <&sdma 77>, <&sdma 78>; |
545 | dma-names = "tx", "rx"; | |
74981768 RN |
546 | }; |
547 | ||
548 | mmc4: mmc@480d1000 { | |
549 | compatible = "ti,omap4-hsmmc"; | |
48420dbc | 550 | reg = <0x480d1000 0x400>; |
8fea7d5a | 551 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
74981768 RN |
552 | ti,hwmods = "mmc4"; |
553 | ti,needs-special-reset; | |
2c2dc545 JH |
554 | dmas = <&sdma 57>, <&sdma 58>; |
555 | dma-names = "tx", "rx"; | |
74981768 RN |
556 | }; |
557 | ||
558 | mmc5: mmc@480d5000 { | |
559 | compatible = "ti,omap4-hsmmc"; | |
48420dbc | 560 | reg = <0x480d5000 0x400>; |
8fea7d5a | 561 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
74981768 RN |
562 | ti,hwmods = "mmc5"; |
563 | ti,needs-special-reset; | |
2c2dc545 JH |
564 | dmas = <&sdma 59>, <&sdma 60>; |
565 | dma-names = "tx", "rx"; | |
74981768 | 566 | }; |
94c30732 | 567 | |
21bd85a1 FV |
568 | mmu_dsp: mmu@4a066000 { |
569 | compatible = "ti,omap4-iommu"; | |
570 | reg = <0x4a066000 0x100>; | |
571 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
572 | ti,hwmods = "mmu_dsp"; | |
22e3bcc6 | 573 | #iommu-cells = <0>; |
21bd85a1 FV |
574 | }; |
575 | ||
576 | mmu_ipu: mmu@55082000 { | |
577 | compatible = "ti,omap4-iommu"; | |
578 | reg = <0x55082000 0x100>; | |
579 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
580 | ti,hwmods = "mmu_ipu"; | |
22e3bcc6 | 581 | #iommu-cells = <0>; |
21bd85a1 FV |
582 | ti,iommu-bus-err-back; |
583 | }; | |
584 | ||
94c30732 XJ |
585 | wdt2: wdt@4a314000 { |
586 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; | |
48420dbc | 587 | reg = <0x4a314000 0x80>; |
8fea7d5a | 588 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
94c30732 XJ |
589 | ti,hwmods = "wd_timer2"; |
590 | }; | |
4f4b5c74 PU |
591 | |
592 | mcpdm: mcpdm@40132000 { | |
593 | compatible = "ti,omap4-mcpdm"; | |
594 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
595 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
63467cf2 | 596 | reg-names = "mpu", "dma"; |
8fea7d5a | 597 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
4f4b5c74 | 598 | ti,hwmods = "mcpdm"; |
4e4ead73 SG |
599 | dmas = <&sdma 65>, |
600 | <&sdma 66>; | |
601 | dma-names = "up_link", "dn_link"; | |
7adb0933 | 602 | status = "disabled"; |
4f4b5c74 | 603 | }; |
a4c38319 PU |
604 | |
605 | dmic: dmic@4012e000 { | |
606 | compatible = "ti,omap4-dmic"; | |
607 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
608 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
63467cf2 | 609 | reg-names = "mpu", "dma"; |
8fea7d5a | 610 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
a4c38319 | 611 | ti,hwmods = "dmic"; |
4e4ead73 SG |
612 | dmas = <&sdma 67>; |
613 | dma-names = "up_link"; | |
7adb0933 | 614 | status = "disabled"; |
a4c38319 | 615 | }; |
61bc3544 | 616 | |
2995a100 PU |
617 | mcbsp1: mcbsp@40122000 { |
618 | compatible = "ti,omap4-mcbsp"; | |
619 | reg = <0x40122000 0xff>, /* MPU private access */ | |
620 | <0x49022000 0xff>; /* L3 Interconnect */ | |
621 | reg-names = "mpu", "dma"; | |
8fea7d5a | 622 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
2995a100 | 623 | interrupt-names = "common"; |
2995a100 PU |
624 | ti,buffer-size = <128>; |
625 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
626 | dmas = <&sdma 33>, |
627 | <&sdma 34>; | |
628 | dma-names = "tx", "rx"; | |
7adb0933 | 629 | status = "disabled"; |
2995a100 PU |
630 | }; |
631 | ||
632 | mcbsp2: mcbsp@40124000 { | |
633 | compatible = "ti,omap4-mcbsp"; | |
634 | reg = <0x40124000 0xff>, /* MPU private access */ | |
635 | <0x49024000 0xff>; /* L3 Interconnect */ | |
636 | reg-names = "mpu", "dma"; | |
8fea7d5a | 637 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
2995a100 | 638 | interrupt-names = "common"; |
2995a100 PU |
639 | ti,buffer-size = <128>; |
640 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
641 | dmas = <&sdma 17>, |
642 | <&sdma 18>; | |
643 | dma-names = "tx", "rx"; | |
7adb0933 | 644 | status = "disabled"; |
2995a100 PU |
645 | }; |
646 | ||
647 | mcbsp3: mcbsp@40126000 { | |
648 | compatible = "ti,omap4-mcbsp"; | |
649 | reg = <0x40126000 0xff>, /* MPU private access */ | |
650 | <0x49026000 0xff>; /* L3 Interconnect */ | |
651 | reg-names = "mpu", "dma"; | |
8fea7d5a | 652 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
2995a100 | 653 | interrupt-names = "common"; |
2995a100 PU |
654 | ti,buffer-size = <128>; |
655 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
656 | dmas = <&sdma 19>, |
657 | <&sdma 20>; | |
658 | dma-names = "tx", "rx"; | |
7adb0933 | 659 | status = "disabled"; |
2995a100 PU |
660 | }; |
661 | ||
662 | mcbsp4: mcbsp@48096000 { | |
663 | compatible = "ti,omap4-mcbsp"; | |
664 | reg = <0x48096000 0xff>; /* L4 Interconnect */ | |
665 | reg-names = "mpu"; | |
8fea7d5a | 666 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
2995a100 | 667 | interrupt-names = "common"; |
2995a100 PU |
668 | ti,buffer-size = <128>; |
669 | ti,hwmods = "mcbsp4"; | |
4e4ead73 SG |
670 | dmas = <&sdma 31>, |
671 | <&sdma 32>; | |
672 | dma-names = "tx", "rx"; | |
7adb0933 | 673 | status = "disabled"; |
2995a100 PU |
674 | }; |
675 | ||
61bc3544 SP |
676 | keypad: keypad@4a31c000 { |
677 | compatible = "ti,omap4-keypad"; | |
48420dbc | 678 | reg = <0x4a31c000 0x80>; |
8fea7d5a | 679 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
48420dbc | 680 | reg-names = "mpu"; |
61bc3544 SP |
681 | ti,hwmods = "kbd"; |
682 | }; | |
11c27069 | 683 | |
1a5fe3ca AT |
684 | dmm@4e000000 { |
685 | compatible = "ti,omap4-dmm"; | |
686 | reg = <0x4e000000 0x800>; | |
687 | interrupts = <0 113 0x4>; | |
688 | ti,hwmods = "dmm"; | |
689 | }; | |
690 | ||
11c27069 A |
691 | emif1: emif@4c000000 { |
692 | compatible = "ti,emif-4d"; | |
48420dbc | 693 | reg = <0x4c000000 0x100>; |
8fea7d5a | 694 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
11c27069 | 695 | ti,hwmods = "emif1"; |
f12ecbe2 | 696 | ti,no-idle-on-init; |
11c27069 A |
697 | phy-type = <1>; |
698 | hw-caps-read-idle-ctrl; | |
699 | hw-caps-ll-interface; | |
700 | hw-caps-temp-alert; | |
701 | }; | |
702 | ||
703 | emif2: emif@4d000000 { | |
704 | compatible = "ti,emif-4d"; | |
48420dbc | 705 | reg = <0x4d000000 0x100>; |
8fea7d5a | 706 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
11c27069 | 707 | ti,hwmods = "emif2"; |
f12ecbe2 | 708 | ti,no-idle-on-init; |
11c27069 A |
709 | phy-type = <1>; |
710 | hw-caps-read-idle-ctrl; | |
711 | hw-caps-ll-interface; | |
712 | hw-caps-temp-alert; | |
713 | }; | |
8f446a7a | 714 | |
3ce0a99c | 715 | ocp2scp@4a0ad000 { |
59bafcf6 | 716 | compatible = "ti,omap-ocp2scp"; |
3ce0a99c | 717 | reg = <0x4a0ad000 0x1f>; |
59bafcf6 KVA |
718 | #address-cells = <1>; |
719 | #size-cells = <1>; | |
720 | ranges; | |
721 | ti,hwmods = "ocp2scp_usb_phy"; | |
cf0d869e KVA |
722 | usb2_phy: usb2phy@4a0ad080 { |
723 | compatible = "ti,omap-usb2"; | |
724 | reg = <0x4a0ad080 0x58>; | |
470019a4 | 725 | ctrl-module = <&omap_control_usb2phy>; |
c65d0ad5 RQ |
726 | clocks = <&usb_phy_cm_clk32k>; |
727 | clock-names = "wkupclk"; | |
975d963e | 728 | #phy-cells = <0>; |
cf0d869e | 729 | }; |
59bafcf6 | 730 | }; |
fab8ad0b | 731 | |
8ebc30dd SA |
732 | mailbox: mailbox@4a0f4000 { |
733 | compatible = "ti,omap4-mailbox"; | |
734 | reg = <0x4a0f4000 0x200>; | |
735 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
736 | ti,hwmods = "mailbox"; | |
24df0453 | 737 | #mbox-cells = <1>; |
8ebc30dd SA |
738 | ti,mbox-num-users = <3>; |
739 | ti,mbox-num-fifos = <8>; | |
d27704d1 SA |
740 | mbox_ipu: mbox_ipu { |
741 | ti,mbox-tx = <0 0 0>; | |
742 | ti,mbox-rx = <1 0 0>; | |
743 | }; | |
744 | mbox_dsp: mbox_dsp { | |
745 | ti,mbox-tx = <3 0 0>; | |
746 | ti,mbox-rx = <2 0 0>; | |
747 | }; | |
8ebc30dd SA |
748 | }; |
749 | ||
fab8ad0b | 750 | timer1: timer@4a318000 { |
002e1ec5 | 751 | compatible = "ti,omap3430-timer"; |
fab8ad0b | 752 | reg = <0x4a318000 0x80>; |
8fea7d5a | 753 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
754 | ti,hwmods = "timer1"; |
755 | ti,timer-alwon; | |
756 | }; | |
757 | ||
758 | timer2: timer@48032000 { | |
002e1ec5 | 759 | compatible = "ti,omap3430-timer"; |
fab8ad0b | 760 | reg = <0x48032000 0x80>; |
8fea7d5a | 761 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
762 | ti,hwmods = "timer2"; |
763 | }; | |
764 | ||
765 | timer3: timer@48034000 { | |
002e1ec5 | 766 | compatible = "ti,omap4430-timer"; |
fab8ad0b | 767 | reg = <0x48034000 0x80>; |
8fea7d5a | 768 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
769 | ti,hwmods = "timer3"; |
770 | }; | |
771 | ||
772 | timer4: timer@48036000 { | |
002e1ec5 | 773 | compatible = "ti,omap4430-timer"; |
fab8ad0b | 774 | reg = <0x48036000 0x80>; |
8fea7d5a | 775 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
776 | ti,hwmods = "timer4"; |
777 | }; | |
778 | ||
d03a93bb | 779 | timer5: timer@40138000 { |
002e1ec5 | 780 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
781 | reg = <0x40138000 0x80>, |
782 | <0x49038000 0x80>; | |
8fea7d5a | 783 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
784 | ti,hwmods = "timer5"; |
785 | ti,timer-dsp; | |
786 | }; | |
787 | ||
d03a93bb | 788 | timer6: timer@4013a000 { |
002e1ec5 | 789 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
790 | reg = <0x4013a000 0x80>, |
791 | <0x4903a000 0x80>; | |
8fea7d5a | 792 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
793 | ti,hwmods = "timer6"; |
794 | ti,timer-dsp; | |
795 | }; | |
796 | ||
d03a93bb | 797 | timer7: timer@4013c000 { |
002e1ec5 | 798 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
799 | reg = <0x4013c000 0x80>, |
800 | <0x4903c000 0x80>; | |
8fea7d5a | 801 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
802 | ti,hwmods = "timer7"; |
803 | ti,timer-dsp; | |
804 | }; | |
805 | ||
d03a93bb | 806 | timer8: timer@4013e000 { |
002e1ec5 | 807 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
808 | reg = <0x4013e000 0x80>, |
809 | <0x4903e000 0x80>; | |
8fea7d5a | 810 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
811 | ti,hwmods = "timer8"; |
812 | ti,timer-pwm; | |
813 | ti,timer-dsp; | |
814 | }; | |
815 | ||
816 | timer9: timer@4803e000 { | |
002e1ec5 | 817 | compatible = "ti,omap4430-timer"; |
fab8ad0b | 818 | reg = <0x4803e000 0x80>; |
8fea7d5a | 819 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
820 | ti,hwmods = "timer9"; |
821 | ti,timer-pwm; | |
822 | }; | |
823 | ||
824 | timer10: timer@48086000 { | |
002e1ec5 | 825 | compatible = "ti,omap3430-timer"; |
fab8ad0b | 826 | reg = <0x48086000 0x80>; |
8fea7d5a | 827 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
828 | ti,hwmods = "timer10"; |
829 | ti,timer-pwm; | |
830 | }; | |
831 | ||
832 | timer11: timer@48088000 { | |
002e1ec5 | 833 | compatible = "ti,omap4430-timer"; |
fab8ad0b | 834 | reg = <0x48088000 0x80>; |
8fea7d5a | 835 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
fab8ad0b JH |
836 | ti,hwmods = "timer11"; |
837 | ti,timer-pwm; | |
838 | }; | |
f17c8994 RQ |
839 | |
840 | usbhstll: usbhstll@4a062000 { | |
841 | compatible = "ti,usbhs-tll"; | |
842 | reg = <0x4a062000 0x1000>; | |
8fea7d5a | 843 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
f17c8994 RQ |
844 | ti,hwmods = "usb_tll_hs"; |
845 | }; | |
846 | ||
847 | usbhshost: usbhshost@4a064000 { | |
848 | compatible = "ti,usbhs-host"; | |
849 | reg = <0x4a064000 0x800>; | |
850 | ti,hwmods = "usb_host_hs"; | |
851 | #address-cells = <1>; | |
852 | #size-cells = <1>; | |
853 | ranges; | |
051fc06d RQ |
854 | clocks = <&init_60m_fclk>, |
855 | <&xclk60mhsp1_ck>, | |
856 | <&xclk60mhsp2_ck>; | |
857 | clock-names = "refclk_60m_int", | |
858 | "refclk_60m_ext_p1", | |
859 | "refclk_60m_ext_p2"; | |
f17c8994 RQ |
860 | |
861 | usbhsohci: ohci@4a064800 { | |
a2525e54 | 862 | compatible = "ti,ohci-omap3"; |
f17c8994 RQ |
863 | reg = <0x4a064800 0x400>; |
864 | interrupt-parent = <&gic>; | |
8fea7d5a | 865 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
f17c8994 RQ |
866 | }; |
867 | ||
868 | usbhsehci: ehci@4a064c00 { | |
a2525e54 | 869 | compatible = "ti,ehci-omap"; |
f17c8994 RQ |
870 | reg = <0x4a064c00 0x400>; |
871 | interrupt-parent = <&gic>; | |
8fea7d5a | 872 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
f17c8994 RQ |
873 | }; |
874 | }; | |
840e5fd8 | 875 | |
470019a4 RQ |
876 | omap_control_usb2phy: control-phy@4a002300 { |
877 | compatible = "ti,control-phy-usb2"; | |
878 | reg = <0x4a002300 0x4>; | |
879 | reg-names = "power"; | |
880 | }; | |
881 | ||
882 | omap_control_usbotg: control-phy@4a00233c { | |
883 | compatible = "ti,control-phy-otghs"; | |
884 | reg = <0x4a00233c 0x4>; | |
885 | reg-names = "otghs_control"; | |
840e5fd8 | 886 | }; |
ad871c10 KVA |
887 | |
888 | usb_otg_hs: usb_otg_hs@4a0ab000 { | |
889 | compatible = "ti,omap4-musb"; | |
890 | reg = <0x4a0ab000 0x7ff>; | |
8fea7d5a | 891 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
ad871c10 KVA |
892 | interrupt-names = "mc", "dma"; |
893 | ti,hwmods = "usb_otg_hs"; | |
894 | usb-phy = <&usb2_phy>; | |
975d963e KVA |
895 | phys = <&usb2_phy>; |
896 | phy-names = "usb2-phy"; | |
ad871c10 KVA |
897 | multipoint = <1>; |
898 | num-eps = <16>; | |
899 | ram-bits = <12>; | |
470019a4 | 900 | ctrl-module = <&omap_control_usbotg>; |
ad871c10 | 901 | }; |
dd6317df JF |
902 | |
903 | aes: aes@4b501000 { | |
904 | compatible = "ti,omap4-aes"; | |
905 | ti,hwmods = "aes"; | |
906 | reg = <0x4b501000 0xa0>; | |
907 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
908 | dmas = <&sdma 111>, <&sdma 110>; | |
909 | dma-names = "tx", "rx"; | |
910 | }; | |
806e9431 JF |
911 | |
912 | des: des@480a5000 { | |
913 | compatible = "ti,omap4-des"; | |
914 | ti,hwmods = "des"; | |
915 | reg = <0x480a5000 0xa0>; | |
916 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
917 | dmas = <&sdma 117>, <&sdma 116>; | |
918 | dma-names = "tx", "rx"; | |
919 | }; | |
e12c7737 AT |
920 | |
921 | abb_mpu: regulator-abb-mpu { | |
922 | compatible = "ti,abb-v2"; | |
923 | regulator-name = "abb_mpu"; | |
924 | #address-cells = <0>; | |
925 | #size-cells = <0>; | |
926 | ti,tranxdone-status-mask = <0x80>; | |
927 | clocks = <&sys_clkin_ck>; | |
928 | ti,settling-time = <50>; | |
929 | ti,clock-cycles = <16>; | |
930 | ||
931 | status = "disabled"; | |
932 | }; | |
933 | ||
934 | abb_iva: regulator-abb-iva { | |
935 | compatible = "ti,abb-v2"; | |
936 | regulator-name = "abb_iva"; | |
937 | #address-cells = <0>; | |
938 | #size-cells = <0>; | |
939 | ti,tranxdone-status-mask = <0x80000000>; | |
940 | clocks = <&sys_clkin_ck>; | |
941 | ti,settling-time = <50>; | |
942 | ti,clock-cycles = <16>; | |
943 | ||
944 | status = "disabled"; | |
945 | }; | |
cfe86fcf TV |
946 | |
947 | dss: dss@58000000 { | |
948 | compatible = "ti,omap4-dss"; | |
949 | reg = <0x58000000 0x80>; | |
950 | status = "disabled"; | |
951 | ti,hwmods = "dss_core"; | |
952 | clocks = <&dss_dss_clk>; | |
953 | clock-names = "fck"; | |
954 | #address-cells = <1>; | |
955 | #size-cells = <1>; | |
956 | ranges; | |
957 | ||
958 | dispc@58001000 { | |
959 | compatible = "ti,omap4-dispc"; | |
960 | reg = <0x58001000 0x1000>; | |
961 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
962 | ti,hwmods = "dss_dispc"; | |
963 | clocks = <&dss_dss_clk>; | |
964 | clock-names = "fck"; | |
965 | }; | |
966 | ||
967 | rfbi: encoder@58002000 { | |
968 | compatible = "ti,omap4-rfbi"; | |
969 | reg = <0x58002000 0x1000>; | |
970 | status = "disabled"; | |
971 | ti,hwmods = "dss_rfbi"; | |
2cc84f46 | 972 | clocks = <&dss_dss_clk>, <&l3_div_ck>; |
cfe86fcf TV |
973 | clock-names = "fck", "ick"; |
974 | }; | |
975 | ||
976 | venc: encoder@58003000 { | |
977 | compatible = "ti,omap4-venc"; | |
978 | reg = <0x58003000 0x1000>; | |
979 | status = "disabled"; | |
980 | ti,hwmods = "dss_venc"; | |
981 | clocks = <&dss_tv_clk>; | |
982 | clock-names = "fck"; | |
983 | }; | |
984 | ||
985 | dsi1: encoder@58004000 { | |
986 | compatible = "ti,omap4-dsi"; | |
987 | reg = <0x58004000 0x200>, | |
988 | <0x58004200 0x40>, | |
989 | <0x58004300 0x20>; | |
990 | reg-names = "proto", "phy", "pll"; | |
991 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
992 | status = "disabled"; | |
993 | ti,hwmods = "dss_dsi1"; | |
994 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; | |
995 | clock-names = "fck", "sys_clk"; | |
996 | }; | |
997 | ||
998 | dsi2: encoder@58005000 { | |
999 | compatible = "ti,omap4-dsi"; | |
1000 | reg = <0x58005000 0x200>, | |
1001 | <0x58005200 0x40>, | |
1002 | <0x58005300 0x20>; | |
1003 | reg-names = "proto", "phy", "pll"; | |
1004 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
1005 | status = "disabled"; | |
1006 | ti,hwmods = "dss_dsi2"; | |
1007 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; | |
1008 | clock-names = "fck", "sys_clk"; | |
1009 | }; | |
1010 | ||
1011 | hdmi: encoder@58006000 { | |
1012 | compatible = "ti,omap4-hdmi"; | |
1013 | reg = <0x58006000 0x200>, | |
1014 | <0x58006200 0x100>, | |
1015 | <0x58006300 0x100>, | |
1016 | <0x58006400 0x1000>; | |
1017 | reg-names = "wp", "pll", "phy", "core"; | |
1018 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
1019 | status = "disabled"; | |
1020 | ti,hwmods = "dss_hdmi"; | |
1021 | clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; | |
1022 | clock-names = "fck", "sys_clk"; | |
53855b30 JS |
1023 | dmas = <&sdma 76>; |
1024 | dma-names = "audio_tx"; | |
cfe86fcf TV |
1025 | }; |
1026 | }; | |
d9fda07a BC |
1027 | }; |
1028 | }; | |
2488ff6c TK |
1029 | |
1030 | /include/ "omap44xx-clocks.dtsi" |