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1 | /* |
2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /* | |
10 | * Carveout for multimedia usecases | |
11 | * It should be the last 48MB of the first 512MB memory part | |
12 | * In theory, it should not even exist. That zone should be reserved | |
13 | * dynamically during the .reserve callback. | |
14 | */ | |
15 | /memreserve/ 0x9d000000 0x03000000; | |
16 | ||
17 | /include/ "skeleton.dtsi" | |
18 | ||
19 | / { | |
20 | compatible = "ti,omap4430", "ti,omap4"; | |
21 | interrupt-parent = <&gic>; | |
22 | ||
23 | aliases { | |
cf3c79de RN |
24 | serial0 = &uart1; |
25 | serial1 = &uart2; | |
26 | serial2 = &uart3; | |
27 | serial3 = &uart4; | |
d9fda07a BC |
28 | }; |
29 | ||
476b679a BC |
30 | cpus { |
31 | cpu@0 { | |
32 | compatible = "arm,cortex-a9"; | |
33 | }; | |
34 | cpu@1 { | |
35 | compatible = "arm,cortex-a9"; | |
36 | }; | |
37 | }; | |
38 | ||
d9fda07a BC |
39 | /* |
40 | * The soc node represents the soc top level view. It is uses for IPs | |
41 | * that are not memory mapped in the MPU view or for the MPU itself. | |
42 | */ | |
43 | soc { | |
44 | compatible = "ti,omap-infra"; | |
476b679a BC |
45 | mpu { |
46 | compatible = "ti,omap4-mpu"; | |
47 | ti,hwmods = "mpu"; | |
48 | }; | |
49 | ||
50 | dsp { | |
51 | compatible = "ti,omap3-c64"; | |
52 | ti,hwmods = "dsp"; | |
53 | }; | |
54 | ||
55 | iva { | |
56 | compatible = "ti,ivahd"; | |
57 | ti,hwmods = "iva"; | |
58 | }; | |
d9fda07a BC |
59 | }; |
60 | ||
61 | /* | |
62 | * XXX: Use a flat representation of the OMAP4 interconnect. | |
63 | * The real OMAP interconnect network is quite complex. | |
64 | * | |
65 | * MPU -+-- MPU_PRIVATE - GIC, L2 | |
66 | * | | |
67 | * +----------------+----------+ | |
68 | * | | | | |
69 | * + +- EMIF - DDR | | |
70 | * | | | | |
71 | * | + +--------+ | |
72 | * | | | | |
73 | * | +- L4_ABE - AESS, MCBSP, TIMERs... | |
74 | * | | | |
75 | * +- L3_MAIN --+- L4_CORE - IPs... | |
76 | * | | |
77 | * +- L4_PER - IPs... | |
78 | * | | |
79 | * +- L4_CFG -+- L4_WKUP - IPs... | |
80 | * | | | |
81 | * | +- IPs... | |
82 | * +- IPU ----+ | |
83 | * | | | |
84 | * +- DSP ----+ | |
85 | * | | | |
86 | * +- DSS ----+ | |
87 | * | |
88 | * Since that will not bring real advantage to represent that in DT for | |
89 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
90 | * hierarchy. | |
91 | */ | |
92 | ocp { | |
ad8dfac6 | 93 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
d9fda07a BC |
94 | #address-cells = <1>; |
95 | #size-cells = <1>; | |
96 | ranges; | |
ad8dfac6 | 97 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
d9fda07a BC |
98 | |
99 | gic: interrupt-controller@48241000 { | |
100 | compatible = "arm,cortex-a9-gic"; | |
101 | interrupt-controller; | |
958e7676 | 102 | #interrupt-cells = <3>; |
d9fda07a BC |
103 | reg = <0x48241000 0x1000>, |
104 | <0x48240100 0x0100>; | |
105 | }; | |
e3e5a92d BC |
106 | |
107 | gpio1: gpio@4a310000 { | |
108 | compatible = "ti,omap4-gpio"; | |
109 | ti,hwmods = "gpio1"; | |
110 | gpio-controller; | |
111 | #gpio-cells = <2>; | |
112 | interrupt-controller; | |
113 | #interrupt-cells = <1>; | |
114 | }; | |
115 | ||
116 | gpio2: gpio@48055000 { | |
117 | compatible = "ti,omap4-gpio"; | |
118 | ti,hwmods = "gpio2"; | |
119 | gpio-controller; | |
120 | #gpio-cells = <2>; | |
121 | interrupt-controller; | |
122 | #interrupt-cells = <1>; | |
123 | }; | |
124 | ||
125 | gpio3: gpio@48057000 { | |
126 | compatible = "ti,omap4-gpio"; | |
127 | ti,hwmods = "gpio3"; | |
128 | gpio-controller; | |
129 | #gpio-cells = <2>; | |
130 | interrupt-controller; | |
131 | #interrupt-cells = <1>; | |
132 | }; | |
133 | ||
134 | gpio4: gpio@48059000 { | |
135 | compatible = "ti,omap4-gpio"; | |
136 | ti,hwmods = "gpio4"; | |
137 | gpio-controller; | |
138 | #gpio-cells = <2>; | |
139 | interrupt-controller; | |
140 | #interrupt-cells = <1>; | |
141 | }; | |
142 | ||
143 | gpio5: gpio@4805b000 { | |
144 | compatible = "ti,omap4-gpio"; | |
145 | ti,hwmods = "gpio5"; | |
146 | gpio-controller; | |
147 | #gpio-cells = <2>; | |
148 | interrupt-controller; | |
149 | #interrupt-cells = <1>; | |
150 | }; | |
151 | ||
152 | gpio6: gpio@4805d000 { | |
153 | compatible = "ti,omap4-gpio"; | |
154 | ti,hwmods = "gpio6"; | |
155 | gpio-controller; | |
156 | #gpio-cells = <2>; | |
157 | interrupt-controller; | |
158 | #interrupt-cells = <1>; | |
159 | }; | |
cf3c79de | 160 | |
19bfb76c | 161 | uart1: serial@4806a000 { |
cf3c79de RN |
162 | compatible = "ti,omap4-uart"; |
163 | ti,hwmods = "uart1"; | |
164 | clock-frequency = <48000000>; | |
165 | }; | |
166 | ||
19bfb76c | 167 | uart2: serial@4806c000 { |
cf3c79de RN |
168 | compatible = "ti,omap4-uart"; |
169 | ti,hwmods = "uart2"; | |
170 | clock-frequency = <48000000>; | |
171 | }; | |
172 | ||
19bfb76c | 173 | uart3: serial@48020000 { |
cf3c79de RN |
174 | compatible = "ti,omap4-uart"; |
175 | ti,hwmods = "uart3"; | |
176 | clock-frequency = <48000000>; | |
177 | }; | |
178 | ||
19bfb76c | 179 | uart4: serial@4806e000 { |
cf3c79de RN |
180 | compatible = "ti,omap4-uart"; |
181 | ti,hwmods = "uart4"; | |
182 | clock-frequency = <48000000>; | |
183 | }; | |
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184 | |
185 | i2c1: i2c@48070000 { | |
186 | compatible = "ti,omap4-i2c"; | |
187 | #address-cells = <1>; | |
188 | #size-cells = <0>; | |
189 | ti,hwmods = "i2c1"; | |
190 | }; | |
191 | ||
192 | i2c2: i2c@48072000 { | |
193 | compatible = "ti,omap4-i2c"; | |
194 | #address-cells = <1>; | |
195 | #size-cells = <0>; | |
196 | ti,hwmods = "i2c2"; | |
197 | }; | |
198 | ||
199 | i2c3: i2c@48060000 { | |
200 | compatible = "ti,omap4-i2c"; | |
201 | #address-cells = <1>; | |
202 | #size-cells = <0>; | |
203 | ti,hwmods = "i2c3"; | |
204 | }; | |
205 | ||
206 | i2c4: i2c@48350000 { | |
207 | compatible = "ti,omap4-i2c"; | |
208 | #address-cells = <1>; | |
209 | #size-cells = <0>; | |
210 | ti,hwmods = "i2c4"; | |
211 | }; | |
d9fda07a BC |
212 | }; |
213 | }; |