]>
Commit | Line | Data |
---|---|---|
d9fda07a BC |
1 | /* |
2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /* | |
10 | * Carveout for multimedia usecases | |
11 | * It should be the last 48MB of the first 512MB memory part | |
12 | * In theory, it should not even exist. That zone should be reserved | |
13 | * dynamically during the .reserve callback. | |
14 | */ | |
15 | /memreserve/ 0x9d000000 0x03000000; | |
16 | ||
17 | /include/ "skeleton.dtsi" | |
18 | ||
19 | / { | |
20 | compatible = "ti,omap4430", "ti,omap4"; | |
21 | interrupt-parent = <&gic>; | |
22 | ||
23 | aliases { | |
cf3c79de RN |
24 | serial0 = &uart1; |
25 | serial1 = &uart2; | |
26 | serial2 = &uart3; | |
27 | serial3 = &uart4; | |
d9fda07a BC |
28 | }; |
29 | ||
476b679a BC |
30 | cpus { |
31 | cpu@0 { | |
32 | compatible = "arm,cortex-a9"; | |
926fd45b | 33 | next-level-cache = <&L2>; |
476b679a BC |
34 | }; |
35 | cpu@1 { | |
36 | compatible = "arm,cortex-a9"; | |
926fd45b | 37 | next-level-cache = <&L2>; |
476b679a BC |
38 | }; |
39 | }; | |
40 | ||
5635121e BC |
41 | gic: interrupt-controller@48241000 { |
42 | compatible = "arm,cortex-a9-gic"; | |
43 | interrupt-controller; | |
44 | #interrupt-cells = <3>; | |
45 | reg = <0x48241000 0x1000>, | |
46 | <0x48240100 0x0100>; | |
47 | }; | |
48 | ||
926fd45b SS |
49 | L2: l2-cache-controller@48242000 { |
50 | compatible = "arm,pl310-cache"; | |
51 | reg = <0x48242000 0x1000>; | |
52 | cache-unified; | |
53 | cache-level = <2>; | |
54 | }; | |
55 | ||
eed0de27 SS |
56 | local-timer@0x48240600 { |
57 | compatible = "arm,cortex-a9-twd-timer"; | |
58 | reg = <0x48240600 0x20>; | |
59 | interrupts = <1 13 0x304>; | |
60 | }; | |
61 | ||
d9fda07a BC |
62 | /* |
63 | * The soc node represents the soc top level view. It is uses for IPs | |
64 | * that are not memory mapped in the MPU view or for the MPU itself. | |
65 | */ | |
66 | soc { | |
67 | compatible = "ti,omap-infra"; | |
476b679a BC |
68 | mpu { |
69 | compatible = "ti,omap4-mpu"; | |
70 | ti,hwmods = "mpu"; | |
71 | }; | |
72 | ||
73 | dsp { | |
74 | compatible = "ti,omap3-c64"; | |
75 | ti,hwmods = "dsp"; | |
76 | }; | |
77 | ||
78 | iva { | |
79 | compatible = "ti,ivahd"; | |
80 | ti,hwmods = "iva"; | |
81 | }; | |
d9fda07a BC |
82 | }; |
83 | ||
84 | /* | |
85 | * XXX: Use a flat representation of the OMAP4 interconnect. | |
86 | * The real OMAP interconnect network is quite complex. | |
d9fda07a BC |
87 | * Since that will not bring real advantage to represent that in DT for |
88 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
89 | * hierarchy. | |
90 | */ | |
91 | ocp { | |
ad8dfac6 | 92 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
d9fda07a BC |
93 | #address-cells = <1>; |
94 | #size-cells = <1>; | |
95 | ranges; | |
ad8dfac6 | 96 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
20a60eaa SS |
97 | reg = <0x44000000 0x1000>, |
98 | <0x44800000 0x2000>, | |
99 | <0x45000000 0x1000>; | |
100 | interrupts = <0 9 0x4>, | |
101 | <0 10 0x4>; | |
d9fda07a | 102 | |
510c0ffd JH |
103 | counter32k: counter@4a304000 { |
104 | compatible = "ti,omap-counter32k"; | |
105 | reg = <0x4a304000 0x20>; | |
106 | ti,hwmods = "counter_32k"; | |
107 | }; | |
108 | ||
679e3310 TL |
109 | omap4_pmx_core: pinmux@4a100040 { |
110 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
111 | reg = <0x4a100040 0x0196>; | |
112 | #address-cells = <1>; | |
113 | #size-cells = <0>; | |
114 | pinctrl-single,register-width = <16>; | |
115 | pinctrl-single,function-mask = <0x7fff>; | |
116 | }; | |
117 | omap4_pmx_wkup: pinmux@4a31e040 { | |
118 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
119 | reg = <0x4a31e040 0x0038>; | |
120 | #address-cells = <1>; | |
121 | #size-cells = <0>; | |
122 | pinctrl-single,register-width = <16>; | |
123 | pinctrl-single,function-mask = <0x7fff>; | |
124 | }; | |
125 | ||
2c2dc545 JH |
126 | sdma: dma-controller@4a056000 { |
127 | compatible = "ti,omap4430-sdma"; | |
128 | reg = <0x4a056000 0x1000>; | |
129 | interrupts = <0 12 0x4>, | |
130 | <0 13 0x4>, | |
131 | <0 14 0x4>, | |
132 | <0 15 0x4>; | |
133 | #dma-cells = <1>; | |
134 | #dma-channels = <32>; | |
135 | #dma-requests = <127>; | |
136 | }; | |
137 | ||
e3e5a92d BC |
138 | gpio1: gpio@4a310000 { |
139 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
140 | reg = <0x4a310000 0x200>; |
141 | interrupts = <0 29 0x4>; | |
e3e5a92d BC |
142 | ti,hwmods = "gpio1"; |
143 | gpio-controller; | |
144 | #gpio-cells = <2>; | |
145 | interrupt-controller; | |
ff5c9059 | 146 | #interrupt-cells = <2>; |
e3e5a92d BC |
147 | }; |
148 | ||
149 | gpio2: gpio@48055000 { | |
150 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
151 | reg = <0x48055000 0x200>; |
152 | interrupts = <0 30 0x4>; | |
e3e5a92d BC |
153 | ti,hwmods = "gpio2"; |
154 | gpio-controller; | |
155 | #gpio-cells = <2>; | |
156 | interrupt-controller; | |
ff5c9059 | 157 | #interrupt-cells = <2>; |
e3e5a92d BC |
158 | }; |
159 | ||
160 | gpio3: gpio@48057000 { | |
161 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
162 | reg = <0x48057000 0x200>; |
163 | interrupts = <0 31 0x4>; | |
e3e5a92d BC |
164 | ti,hwmods = "gpio3"; |
165 | gpio-controller; | |
166 | #gpio-cells = <2>; | |
167 | interrupt-controller; | |
ff5c9059 | 168 | #interrupt-cells = <2>; |
e3e5a92d BC |
169 | }; |
170 | ||
171 | gpio4: gpio@48059000 { | |
172 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
173 | reg = <0x48059000 0x200>; |
174 | interrupts = <0 32 0x4>; | |
e3e5a92d BC |
175 | ti,hwmods = "gpio4"; |
176 | gpio-controller; | |
177 | #gpio-cells = <2>; | |
178 | interrupt-controller; | |
ff5c9059 | 179 | #interrupt-cells = <2>; |
e3e5a92d BC |
180 | }; |
181 | ||
182 | gpio5: gpio@4805b000 { | |
183 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
184 | reg = <0x4805b000 0x200>; |
185 | interrupts = <0 33 0x4>; | |
e3e5a92d BC |
186 | ti,hwmods = "gpio5"; |
187 | gpio-controller; | |
188 | #gpio-cells = <2>; | |
189 | interrupt-controller; | |
ff5c9059 | 190 | #interrupt-cells = <2>; |
e3e5a92d BC |
191 | }; |
192 | ||
193 | gpio6: gpio@4805d000 { | |
194 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
195 | reg = <0x4805d000 0x200>; |
196 | interrupts = <0 34 0x4>; | |
e3e5a92d BC |
197 | ti,hwmods = "gpio6"; |
198 | gpio-controller; | |
199 | #gpio-cells = <2>; | |
200 | interrupt-controller; | |
ff5c9059 | 201 | #interrupt-cells = <2>; |
e3e5a92d | 202 | }; |
cf3c79de | 203 | |
1c7dbb55 JH |
204 | gpmc: gpmc@50000000 { |
205 | compatible = "ti,omap4430-gpmc"; | |
206 | reg = <0x50000000 0x1000>; | |
207 | #address-cells = <2>; | |
208 | #size-cells = <1>; | |
209 | interrupts = <0 20 0x4>; | |
210 | gpmc,num-cs = <8>; | |
211 | gpmc,num-waitpins = <4>; | |
212 | ti,hwmods = "gpmc"; | |
213 | }; | |
214 | ||
19bfb76c | 215 | uart1: serial@4806a000 { |
cf3c79de | 216 | compatible = "ti,omap4-uart"; |
48420dbc BC |
217 | reg = <0x4806a000 0x100>; |
218 | interrupts = <0 72 0x4>; | |
cf3c79de RN |
219 | ti,hwmods = "uart1"; |
220 | clock-frequency = <48000000>; | |
221 | }; | |
222 | ||
19bfb76c | 223 | uart2: serial@4806c000 { |
cf3c79de | 224 | compatible = "ti,omap4-uart"; |
48420dbc BC |
225 | reg = <0x4806c000 0x100>; |
226 | interrupts = <0 73 0x4>; | |
cf3c79de RN |
227 | ti,hwmods = "uart2"; |
228 | clock-frequency = <48000000>; | |
229 | }; | |
230 | ||
19bfb76c | 231 | uart3: serial@48020000 { |
cf3c79de | 232 | compatible = "ti,omap4-uart"; |
48420dbc BC |
233 | reg = <0x48020000 0x100>; |
234 | interrupts = <0 74 0x4>; | |
cf3c79de RN |
235 | ti,hwmods = "uart3"; |
236 | clock-frequency = <48000000>; | |
237 | }; | |
238 | ||
19bfb76c | 239 | uart4: serial@4806e000 { |
cf3c79de | 240 | compatible = "ti,omap4-uart"; |
48420dbc BC |
241 | reg = <0x4806e000 0x100>; |
242 | interrupts = <0 70 0x4>; | |
cf3c79de RN |
243 | ti,hwmods = "uart4"; |
244 | clock-frequency = <48000000>; | |
245 | }; | |
58e778f9 BC |
246 | |
247 | i2c1: i2c@48070000 { | |
248 | compatible = "ti,omap4-i2c"; | |
48420dbc BC |
249 | reg = <0x48070000 0x100>; |
250 | interrupts = <0 56 0x4>; | |
58e778f9 BC |
251 | #address-cells = <1>; |
252 | #size-cells = <0>; | |
253 | ti,hwmods = "i2c1"; | |
254 | }; | |
255 | ||
256 | i2c2: i2c@48072000 { | |
257 | compatible = "ti,omap4-i2c"; | |
48420dbc BC |
258 | reg = <0x48072000 0x100>; |
259 | interrupts = <0 57 0x4>; | |
58e778f9 BC |
260 | #address-cells = <1>; |
261 | #size-cells = <0>; | |
262 | ti,hwmods = "i2c2"; | |
263 | }; | |
264 | ||
265 | i2c3: i2c@48060000 { | |
266 | compatible = "ti,omap4-i2c"; | |
48420dbc BC |
267 | reg = <0x48060000 0x100>; |
268 | interrupts = <0 61 0x4>; | |
58e778f9 BC |
269 | #address-cells = <1>; |
270 | #size-cells = <0>; | |
271 | ti,hwmods = "i2c3"; | |
272 | }; | |
273 | ||
274 | i2c4: i2c@48350000 { | |
275 | compatible = "ti,omap4-i2c"; | |
48420dbc BC |
276 | reg = <0x48350000 0x100>; |
277 | interrupts = <0 62 0x4>; | |
58e778f9 BC |
278 | #address-cells = <1>; |
279 | #size-cells = <0>; | |
280 | ti,hwmods = "i2c4"; | |
281 | }; | |
efcf1e50 BC |
282 | |
283 | mcspi1: spi@48098000 { | |
284 | compatible = "ti,omap4-mcspi"; | |
48420dbc BC |
285 | reg = <0x48098000 0x200>; |
286 | interrupts = <0 65 0x4>; | |
efcf1e50 BC |
287 | #address-cells = <1>; |
288 | #size-cells = <0>; | |
289 | ti,hwmods = "mcspi1"; | |
290 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
291 | dmas = <&sdma 35>, |
292 | <&sdma 36>, | |
293 | <&sdma 37>, | |
294 | <&sdma 38>, | |
295 | <&sdma 39>, | |
296 | <&sdma 40>, | |
297 | <&sdma 41>, | |
298 | <&sdma 42>; | |
299 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
300 | "tx2", "rx2", "tx3", "rx3"; | |
efcf1e50 BC |
301 | }; |
302 | ||
303 | mcspi2: spi@4809a000 { | |
304 | compatible = "ti,omap4-mcspi"; | |
48420dbc BC |
305 | reg = <0x4809a000 0x200>; |
306 | interrupts = <0 66 0x4>; | |
efcf1e50 BC |
307 | #address-cells = <1>; |
308 | #size-cells = <0>; | |
309 | ti,hwmods = "mcspi2"; | |
310 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
311 | dmas = <&sdma 43>, |
312 | <&sdma 44>, | |
313 | <&sdma 45>, | |
314 | <&sdma 46>; | |
315 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
efcf1e50 BC |
316 | }; |
317 | ||
318 | mcspi3: spi@480b8000 { | |
319 | compatible = "ti,omap4-mcspi"; | |
48420dbc BC |
320 | reg = <0x480b8000 0x200>; |
321 | interrupts = <0 91 0x4>; | |
efcf1e50 BC |
322 | #address-cells = <1>; |
323 | #size-cells = <0>; | |
324 | ti,hwmods = "mcspi3"; | |
325 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
326 | dmas = <&sdma 15>, <&sdma 16>; |
327 | dma-names = "tx0", "rx0"; | |
efcf1e50 BC |
328 | }; |
329 | ||
330 | mcspi4: spi@480ba000 { | |
331 | compatible = "ti,omap4-mcspi"; | |
48420dbc BC |
332 | reg = <0x480ba000 0x200>; |
333 | interrupts = <0 48 0x4>; | |
efcf1e50 BC |
334 | #address-cells = <1>; |
335 | #size-cells = <0>; | |
336 | ti,hwmods = "mcspi4"; | |
337 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
338 | dmas = <&sdma 70>, <&sdma 71>; |
339 | dma-names = "tx0", "rx0"; | |
efcf1e50 | 340 | }; |
74981768 RN |
341 | |
342 | mmc1: mmc@4809c000 { | |
343 | compatible = "ti,omap4-hsmmc"; | |
48420dbc BC |
344 | reg = <0x4809c000 0x400>; |
345 | interrupts = <0 83 0x4>; | |
74981768 RN |
346 | ti,hwmods = "mmc1"; |
347 | ti,dual-volt; | |
348 | ti,needs-special-reset; | |
2c2dc545 JH |
349 | dmas = <&sdma 61>, <&sdma 62>; |
350 | dma-names = "tx", "rx"; | |
74981768 RN |
351 | }; |
352 | ||
353 | mmc2: mmc@480b4000 { | |
354 | compatible = "ti,omap4-hsmmc"; | |
48420dbc BC |
355 | reg = <0x480b4000 0x400>; |
356 | interrupts = <0 86 0x4>; | |
74981768 RN |
357 | ti,hwmods = "mmc2"; |
358 | ti,needs-special-reset; | |
2c2dc545 JH |
359 | dmas = <&sdma 47>, <&sdma 48>; |
360 | dma-names = "tx", "rx"; | |
74981768 RN |
361 | }; |
362 | ||
363 | mmc3: mmc@480ad000 { | |
364 | compatible = "ti,omap4-hsmmc"; | |
48420dbc BC |
365 | reg = <0x480ad000 0x400>; |
366 | interrupts = <0 94 0x4>; | |
74981768 RN |
367 | ti,hwmods = "mmc3"; |
368 | ti,needs-special-reset; | |
2c2dc545 JH |
369 | dmas = <&sdma 77>, <&sdma 78>; |
370 | dma-names = "tx", "rx"; | |
74981768 RN |
371 | }; |
372 | ||
373 | mmc4: mmc@480d1000 { | |
374 | compatible = "ti,omap4-hsmmc"; | |
48420dbc BC |
375 | reg = <0x480d1000 0x400>; |
376 | interrupts = <0 96 0x4>; | |
74981768 RN |
377 | ti,hwmods = "mmc4"; |
378 | ti,needs-special-reset; | |
2c2dc545 JH |
379 | dmas = <&sdma 57>, <&sdma 58>; |
380 | dma-names = "tx", "rx"; | |
74981768 RN |
381 | }; |
382 | ||
383 | mmc5: mmc@480d5000 { | |
384 | compatible = "ti,omap4-hsmmc"; | |
48420dbc BC |
385 | reg = <0x480d5000 0x400>; |
386 | interrupts = <0 59 0x4>; | |
74981768 RN |
387 | ti,hwmods = "mmc5"; |
388 | ti,needs-special-reset; | |
2c2dc545 JH |
389 | dmas = <&sdma 59>, <&sdma 60>; |
390 | dma-names = "tx", "rx"; | |
74981768 | 391 | }; |
94c30732 XJ |
392 | |
393 | wdt2: wdt@4a314000 { | |
394 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; | |
48420dbc BC |
395 | reg = <0x4a314000 0x80>; |
396 | interrupts = <0 80 0x4>; | |
94c30732 XJ |
397 | ti,hwmods = "wd_timer2"; |
398 | }; | |
4f4b5c74 PU |
399 | |
400 | mcpdm: mcpdm@40132000 { | |
401 | compatible = "ti,omap4-mcpdm"; | |
402 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
403 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
63467cf2 | 404 | reg-names = "mpu", "dma"; |
4f4b5c74 | 405 | interrupts = <0 112 0x4>; |
4f4b5c74 | 406 | ti,hwmods = "mcpdm"; |
4e4ead73 SG |
407 | dmas = <&sdma 65>, |
408 | <&sdma 66>; | |
409 | dma-names = "up_link", "dn_link"; | |
4f4b5c74 | 410 | }; |
a4c38319 PU |
411 | |
412 | dmic: dmic@4012e000 { | |
413 | compatible = "ti,omap4-dmic"; | |
414 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
415 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
63467cf2 | 416 | reg-names = "mpu", "dma"; |
a4c38319 | 417 | interrupts = <0 114 0x4>; |
a4c38319 | 418 | ti,hwmods = "dmic"; |
4e4ead73 SG |
419 | dmas = <&sdma 67>; |
420 | dma-names = "up_link"; | |
a4c38319 | 421 | }; |
61bc3544 | 422 | |
2995a100 PU |
423 | mcbsp1: mcbsp@40122000 { |
424 | compatible = "ti,omap4-mcbsp"; | |
425 | reg = <0x40122000 0xff>, /* MPU private access */ | |
426 | <0x49022000 0xff>; /* L3 Interconnect */ | |
427 | reg-names = "mpu", "dma"; | |
428 | interrupts = <0 17 0x4>; | |
429 | interrupt-names = "common"; | |
2995a100 PU |
430 | ti,buffer-size = <128>; |
431 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
432 | dmas = <&sdma 33>, |
433 | <&sdma 34>; | |
434 | dma-names = "tx", "rx"; | |
2995a100 PU |
435 | }; |
436 | ||
437 | mcbsp2: mcbsp@40124000 { | |
438 | compatible = "ti,omap4-mcbsp"; | |
439 | reg = <0x40124000 0xff>, /* MPU private access */ | |
440 | <0x49024000 0xff>; /* L3 Interconnect */ | |
441 | reg-names = "mpu", "dma"; | |
442 | interrupts = <0 22 0x4>; | |
443 | interrupt-names = "common"; | |
2995a100 PU |
444 | ti,buffer-size = <128>; |
445 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
446 | dmas = <&sdma 17>, |
447 | <&sdma 18>; | |
448 | dma-names = "tx", "rx"; | |
2995a100 PU |
449 | }; |
450 | ||
451 | mcbsp3: mcbsp@40126000 { | |
452 | compatible = "ti,omap4-mcbsp"; | |
453 | reg = <0x40126000 0xff>, /* MPU private access */ | |
454 | <0x49026000 0xff>; /* L3 Interconnect */ | |
455 | reg-names = "mpu", "dma"; | |
456 | interrupts = <0 23 0x4>; | |
457 | interrupt-names = "common"; | |
2995a100 PU |
458 | ti,buffer-size = <128>; |
459 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
460 | dmas = <&sdma 19>, |
461 | <&sdma 20>; | |
462 | dma-names = "tx", "rx"; | |
2995a100 PU |
463 | }; |
464 | ||
465 | mcbsp4: mcbsp@48096000 { | |
466 | compatible = "ti,omap4-mcbsp"; | |
467 | reg = <0x48096000 0xff>; /* L4 Interconnect */ | |
468 | reg-names = "mpu"; | |
469 | interrupts = <0 16 0x4>; | |
470 | interrupt-names = "common"; | |
2995a100 PU |
471 | ti,buffer-size = <128>; |
472 | ti,hwmods = "mcbsp4"; | |
4e4ead73 SG |
473 | dmas = <&sdma 31>, |
474 | <&sdma 32>; | |
475 | dma-names = "tx", "rx"; | |
2995a100 PU |
476 | }; |
477 | ||
61bc3544 SP |
478 | keypad: keypad@4a31c000 { |
479 | compatible = "ti,omap4-keypad"; | |
48420dbc BC |
480 | reg = <0x4a31c000 0x80>; |
481 | interrupts = <0 120 0x4>; | |
482 | reg-names = "mpu"; | |
61bc3544 SP |
483 | ti,hwmods = "kbd"; |
484 | }; | |
11c27069 A |
485 | |
486 | emif1: emif@4c000000 { | |
487 | compatible = "ti,emif-4d"; | |
48420dbc BC |
488 | reg = <0x4c000000 0x100>; |
489 | interrupts = <0 110 0x4>; | |
11c27069 A |
490 | ti,hwmods = "emif1"; |
491 | phy-type = <1>; | |
492 | hw-caps-read-idle-ctrl; | |
493 | hw-caps-ll-interface; | |
494 | hw-caps-temp-alert; | |
495 | }; | |
496 | ||
497 | emif2: emif@4d000000 { | |
498 | compatible = "ti,emif-4d"; | |
48420dbc BC |
499 | reg = <0x4d000000 0x100>; |
500 | interrupts = <0 111 0x4>; | |
11c27069 A |
501 | ti,hwmods = "emif2"; |
502 | phy-type = <1>; | |
503 | hw-caps-read-idle-ctrl; | |
504 | hw-caps-ll-interface; | |
505 | hw-caps-temp-alert; | |
506 | }; | |
8f446a7a | 507 | |
3ce0a99c | 508 | ocp2scp@4a0ad000 { |
59bafcf6 | 509 | compatible = "ti,omap-ocp2scp"; |
3ce0a99c | 510 | reg = <0x4a0ad000 0x1f>; |
59bafcf6 KVA |
511 | #address-cells = <1>; |
512 | #size-cells = <1>; | |
513 | ranges; | |
514 | ti,hwmods = "ocp2scp_usb_phy"; | |
cf0d869e KVA |
515 | usb2_phy: usb2phy@4a0ad080 { |
516 | compatible = "ti,omap-usb2"; | |
517 | reg = <0x4a0ad080 0x58>; | |
518 | ctrl-module = <&omap_control_usb>; | |
519 | }; | |
59bafcf6 | 520 | }; |
fab8ad0b JH |
521 | |
522 | timer1: timer@4a318000 { | |
523 | compatible = "ti,omap2-timer"; | |
524 | reg = <0x4a318000 0x80>; | |
525 | interrupts = <0 37 0x4>; | |
526 | ti,hwmods = "timer1"; | |
527 | ti,timer-alwon; | |
528 | }; | |
529 | ||
530 | timer2: timer@48032000 { | |
531 | compatible = "ti,omap2-timer"; | |
532 | reg = <0x48032000 0x80>; | |
533 | interrupts = <0 38 0x4>; | |
534 | ti,hwmods = "timer2"; | |
535 | }; | |
536 | ||
537 | timer3: timer@48034000 { | |
538 | compatible = "ti,omap2-timer"; | |
539 | reg = <0x48034000 0x80>; | |
540 | interrupts = <0 39 0x4>; | |
541 | ti,hwmods = "timer3"; | |
542 | }; | |
543 | ||
544 | timer4: timer@48036000 { | |
545 | compatible = "ti,omap2-timer"; | |
546 | reg = <0x48036000 0x80>; | |
547 | interrupts = <0 40 0x4>; | |
548 | ti,hwmods = "timer4"; | |
549 | }; | |
550 | ||
d03a93bb | 551 | timer5: timer@40138000 { |
fab8ad0b | 552 | compatible = "ti,omap2-timer"; |
d03a93bb JH |
553 | reg = <0x40138000 0x80>, |
554 | <0x49038000 0x80>; | |
fab8ad0b JH |
555 | interrupts = <0 41 0x4>; |
556 | ti,hwmods = "timer5"; | |
557 | ti,timer-dsp; | |
558 | }; | |
559 | ||
d03a93bb | 560 | timer6: timer@4013a000 { |
fab8ad0b | 561 | compatible = "ti,omap2-timer"; |
d03a93bb JH |
562 | reg = <0x4013a000 0x80>, |
563 | <0x4903a000 0x80>; | |
fab8ad0b JH |
564 | interrupts = <0 42 0x4>; |
565 | ti,hwmods = "timer6"; | |
566 | ti,timer-dsp; | |
567 | }; | |
568 | ||
d03a93bb | 569 | timer7: timer@4013c000 { |
fab8ad0b | 570 | compatible = "ti,omap2-timer"; |
d03a93bb JH |
571 | reg = <0x4013c000 0x80>, |
572 | <0x4903c000 0x80>; | |
fab8ad0b JH |
573 | interrupts = <0 43 0x4>; |
574 | ti,hwmods = "timer7"; | |
575 | ti,timer-dsp; | |
576 | }; | |
577 | ||
d03a93bb | 578 | timer8: timer@4013e000 { |
fab8ad0b | 579 | compatible = "ti,omap2-timer"; |
d03a93bb JH |
580 | reg = <0x4013e000 0x80>, |
581 | <0x4903e000 0x80>; | |
fab8ad0b JH |
582 | interrupts = <0 44 0x4>; |
583 | ti,hwmods = "timer8"; | |
584 | ti,timer-pwm; | |
585 | ti,timer-dsp; | |
586 | }; | |
587 | ||
588 | timer9: timer@4803e000 { | |
589 | compatible = "ti,omap2-timer"; | |
590 | reg = <0x4803e000 0x80>; | |
591 | interrupts = <0 45 0x4>; | |
592 | ti,hwmods = "timer9"; | |
593 | ti,timer-pwm; | |
594 | }; | |
595 | ||
596 | timer10: timer@48086000 { | |
597 | compatible = "ti,omap2-timer"; | |
598 | reg = <0x48086000 0x80>; | |
599 | interrupts = <0 46 0x4>; | |
600 | ti,hwmods = "timer10"; | |
601 | ti,timer-pwm; | |
602 | }; | |
603 | ||
604 | timer11: timer@48088000 { | |
605 | compatible = "ti,omap2-timer"; | |
606 | reg = <0x48088000 0x80>; | |
607 | interrupts = <0 47 0x4>; | |
608 | ti,hwmods = "timer11"; | |
609 | ti,timer-pwm; | |
610 | }; | |
f17c8994 RQ |
611 | |
612 | usbhstll: usbhstll@4a062000 { | |
613 | compatible = "ti,usbhs-tll"; | |
614 | reg = <0x4a062000 0x1000>; | |
615 | interrupts = <0 78 0x4>; | |
616 | ti,hwmods = "usb_tll_hs"; | |
617 | }; | |
618 | ||
619 | usbhshost: usbhshost@4a064000 { | |
620 | compatible = "ti,usbhs-host"; | |
621 | reg = <0x4a064000 0x800>; | |
622 | ti,hwmods = "usb_host_hs"; | |
623 | #address-cells = <1>; | |
624 | #size-cells = <1>; | |
625 | ranges; | |
626 | ||
627 | usbhsohci: ohci@4a064800 { | |
628 | compatible = "ti,ohci-omap3", "usb-ohci"; | |
629 | reg = <0x4a064800 0x400>; | |
630 | interrupt-parent = <&gic>; | |
631 | interrupts = <0 76 0x4>; | |
632 | }; | |
633 | ||
634 | usbhsehci: ehci@4a064c00 { | |
635 | compatible = "ti,ehci-omap", "usb-ehci"; | |
636 | reg = <0x4a064c00 0x400>; | |
637 | interrupt-parent = <&gic>; | |
638 | interrupts = <0 77 0x4>; | |
639 | }; | |
640 | }; | |
840e5fd8 KVA |
641 | |
642 | omap_control_usb: omap-control-usb@4a002300 { | |
643 | compatible = "ti,omap-control-usb"; | |
644 | reg = <0x4a002300 0x4>, | |
645 | <0x4a00233c 0x4>; | |
646 | reg-names = "control_dev_conf", "otghs_control"; | |
647 | ti,type = <1>; | |
648 | }; | |
ad871c10 KVA |
649 | |
650 | usb_otg_hs: usb_otg_hs@4a0ab000 { | |
651 | compatible = "ti,omap4-musb"; | |
652 | reg = <0x4a0ab000 0x7ff>; | |
653 | interrupts = <0 92 0x4>, <0 93 0x4>; | |
654 | interrupt-names = "mc", "dma"; | |
655 | ti,hwmods = "usb_otg_hs"; | |
656 | usb-phy = <&usb2_phy>; | |
657 | multipoint = <1>; | |
658 | num-eps = <16>; | |
659 | ram-bits = <12>; | |
660 | ti,has-mailbox; | |
661 | }; | |
d9fda07a BC |
662 | }; |
663 | }; |