[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / omap4.dtsi

/*
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * Carveout for multimedia usecases
 * It should be the last 48MB of the first 512MB memory part
 * In theory, it should not even exist. That zone should be reserved
 * dynamically during the .reserve callback.
 */
/memreserve/ 0x9d000000 0x03000000;

/include/ "skeleton.dtsi"

/ {
	compatible = "ti,omap4430", "ti,omap4";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
		};
		cpu@1 {
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
		};
	};

	gic: interrupt-controller@48241000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48241000 0x1000>,
		      <0x48240100 0x0100>;
	};

	L2: l2-cache-controller@48242000 {
		compatible = "arm,pl310-cache";
		reg = <0x48242000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	local-timer@0x48240600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x48240600 0x20>;
		interrupts = <1 13 0x304>;
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap4-mpu";
			ti,hwmods = "mpu";
		};

		dsp {
			compatible = "ti,omap3-c64";
			ti,hwmods = "dsp";
		};

		iva {
			compatible = "ti,ivahd";
			ti,hwmods = "iva";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP4 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";

		counter32k: counter@4a304000 {
			compatible = "ti,omap-counter32k";
			reg = <0x4a304000 0x20>;
			ti,hwmods = "counter_32k";
		};

		omap4_pmx_core: pinmux@4a100040 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4a100040 0x0196>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};
		omap4_pmx_wkup: pinmux@4a31e040 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4a31e040 0x0038>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};

		gpio1: gpio@4a310000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4a310000 0x200>;
			interrupts = <0 29 0x4>;
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <0 30 0x4>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <0 31 0x4>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <0 32 0x4>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <0 33 0x4>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <0 34 0x4>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts = <0 72 0x4>;
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <0 73 0x4>;
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <0 74 0x4>;
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <0 70 0x4>;
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <0 56 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <0 57 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <0 61 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		i2c4: i2c@48350000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48350000 0x100>;
			interrupts = <0 62 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
			interrupts = <0 65 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
			interrupts = <0 66 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
			interrupts = <0 91 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
			interrupts = <0 48 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x4809c000 0x400>;
			interrupts = <0 83 0x4>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480b4000 0x400>;
			interrupts = <0 86 0x4>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480ad000 0x400>;
			interrupts = <0 94 0x4>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d1000 0x400>;
			interrupts = <0 96 0x4>;
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d5000 0x400>;
			interrupts = <0 59 0x4>;
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
		};

		wdt2: wdt@4a314000 {
			compatible = "ti,omap4-wdt", "ti,omap3-wdt";
			reg = <0x4a314000 0x80>;
			interrupts = <0 80 0x4>;
			ti,hwmods = "wd_timer2";
		};

		mcpdm: mcpdm@40132000 {
			compatible = "ti,omap4-mcpdm";
			reg = <0x40132000 0x7f>, /* MPU private access */
			      <0x49032000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 112 0x4>;
			ti,hwmods = "mcpdm";
		};

		dmic: dmic@4012e000 {
			compatible = "ti,omap4-dmic";
			reg = <0x4012e000 0x7f>, /* MPU private access */
			      <0x4902e000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 114 0x4>;
			ti,hwmods = "dmic";
		};

		mcbsp1: mcbsp@40122000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40122000 0xff>, /* MPU private access */
			      <0x49022000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 17 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
		};

		mcbsp2: mcbsp@40124000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40124000 0xff>, /* MPU private access */
			      <0x49024000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 22 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
		};

		mcbsp3: mcbsp@40126000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40126000 0xff>, /* MPU private access */
			      <0x49026000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 23 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
		};

		mcbsp4: mcbsp@48096000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x48096000 0xff>; /* L4 Interconnect */
			reg-names = "mpu";
			interrupts = <0 16 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp4";
		};

		keypad: keypad@4a31c000 {
			compatible = "ti,omap4-keypad";
			reg = <0x4a31c000 0x80>;
			interrupts = <0 120 0x4>;
			reg-names = "mpu";
			ti,hwmods = "kbd";
		};

		emif1: emif@4c000000 {
			compatible = "ti,emif-4d";
			reg = <0x4c000000 0x100>;
			interrupts = <0 110 0x4>;
			ti,hwmods = "emif1";
			phy-type = <1>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		emif2: emif@4d000000 {
			compatible = "ti,emif-4d";
			reg = <0x4d000000 0x100>;
			interrupts = <0 111 0x4>;
			ti,hwmods = "emif2";
			phy-type = <1>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		ocp2scp@4a0ad000 {
			compatible = "ti,omap-ocp2scp";
			reg = <0x4a0ad000 0x1f>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "ocp2scp_usb_phy";
			usb2_phy: usb2phy@4a0ad080 {
				compatible = "ti,omap-usb2";
				reg = <0x4a0ad080 0x58>;
				ctrl-module = <&omap_control_usb>;
			};
		};

		timer1: timer@4a318000 {
			compatible = "ti,omap2-timer";
			reg = <0x4a318000 0x80>;
			interrupts = <0 37 0x4>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48032000 {
			compatible = "ti,omap2-timer";
			reg = <0x48032000 0x80>;
			interrupts = <0 38 0x4>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48034000 {
			compatible = "ti,omap2-timer";
			reg = <0x48034000 0x80>;
			interrupts = <0 39 0x4>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48036000 {
			compatible = "ti,omap2-timer";
			reg = <0x48036000 0x80>;
			interrupts = <0 40 0x4>;
			ti,hwmods = "timer4";
		};

		timer5: timer@40138000 {
			compatible = "ti,omap2-timer";
			reg = <0x40138000 0x80>,
			      <0x49038000 0x80>;
			interrupts = <0 41 0x4>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
		};

		timer6: timer@4013a000 {
			compatible = "ti,omap2-timer";
			reg = <0x4013a000 0x80>,
			      <0x4903a000 0x80>;
			interrupts = <0 42 0x4>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
		};

		timer7: timer@4013c000 {
			compatible = "ti,omap2-timer";
			reg = <0x4013c000 0x80>,
			      <0x4903c000 0x80>;
			interrupts = <0 43 0x4>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@4013e000 {
			compatible = "ti,omap2-timer";
			reg = <0x4013e000 0x80>,
			      <0x4903e000 0x80>;
			interrupts = <0 44 0x4>;
			ti,hwmods = "timer8";
			ti,timer-pwm;
			ti,timer-dsp;
		};

		timer9: timer@4803e000 {
			compatible = "ti,omap2-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <0 45 0x4>;
			ti,hwmods = "timer9";
			ti,timer-pwm;
		};

		timer10: timer@48086000 {
			compatible = "ti,omap2-timer";
			reg = <0x48086000 0x80>;
			interrupts = <0 46 0x4>;
			ti,hwmods = "timer10";
			ti,timer-pwm;
		};

		timer11: timer@48088000 {
			compatible = "ti,omap2-timer";
			reg = <0x48088000 0x80>;
			interrupts = <0 47 0x4>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};

		usbhstll: usbhstll@4a062000 {
			compatible = "ti,usbhs-tll";
			reg = <0x4a062000 0x1000>;
			interrupts = <0 78 0x4>;
			ti,hwmods = "usb_tll_hs";
		};

		usbhshost: usbhshost@4a064000 {
			compatible = "ti,usbhs-host";
			reg = <0x4a064000 0x800>;
			ti,hwmods = "usb_host_hs";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			usbhsohci: ohci@4a064800 {
				compatible = "ti,ohci-omap3", "usb-ohci";
				reg = <0x4a064800 0x400>;
				interrupt-parent = <&gic>;
				interrupts = <0 76 0x4>;
			};

			usbhsehci: ehci@4a064c00 {
				compatible = "ti,ehci-omap", "usb-ehci";
				reg = <0x4a064c00 0x400>;
				interrupt-parent = <&gic>;
				interrupts = <0 77 0x4>;
			};
		};

		omap_control_usb: omap-control-usb@4a002300 {
			compatible = "ti,omap-control-usb";
			reg = <0x4a002300 0x4>,
			      <0x4a00233c 0x4>;
			reg-names = "control_dev_conf", "otghs_control";
			ti,type = <1>;
		};

		usb_otg_hs: usb_otg_hs@4a0ab000 {
			compatible = "ti,omap4-musb";
			reg = <0x4a0ab000 0x7ff>;
			interrupts = <0 92 0x4>, <0 93 0x4>;
			interrupt-names = "mc", "dma";
			ti,hwmods = "usb_otg_hs";
			usb-phy = <&usb2_phy>;
			multipoint = <1>;
			num-eps = <16>;
			ram-bits = <12>;
			ti,has-mailbox;
		};
	};
};
Commit	Line	Data
d9fda07a BC	1	/*
	2	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	/*
	10	* Carveout for multimedia usecases
	11	* It should be the last 48MB of the first 512MB memory part
	12	* In theory, it should not even exist. That zone should be reserved
	13	* dynamically during the .reserve callback.
	14	*/
	15	/memreserve/ 0x9d000000 0x03000000;
	16
	17	/include/ "skeleton.dtsi"
	18
	19	/ {
	20	compatible = "ti,omap4430", "ti,omap4";
	21	interrupt-parent = <&gic>;
	22
	23	aliases {
cf3c79de RN	24	serial0 = &uart1;
	25	serial1 = &uart2;
	26	serial2 = &uart3;
	27	serial3 = &uart4;
d9fda07a BC	28	};
d9fda07a BC	29
476b679a BC	30	cpus {
	31	cpu@0 {
	32	compatible = "arm,cortex-a9";
926fd45b	33	next-level-cache = <&L2>;
476b679a BC	34	};
	35	cpu@1 {
	36	compatible = "arm,cortex-a9";
926fd45b	37	next-level-cache = <&L2>;
476b679a BC	38	};
	39	};
	40
5635121e BC	41	gic: interrupt-controller@48241000 {
	42	compatible = "arm,cortex-a9-gic";
	43	interrupt-controller;
	44	#interrupt-cells = <3>;
	45	reg = <0x48241000 0x1000>,
	46	<0x48240100 0x0100>;
	47	};
	48
926fd45b SS	49	L2: l2-cache-controller@48242000 {
	50	compatible = "arm,pl310-cache";
	51	reg = <0x48242000 0x1000>;
	52	cache-unified;
	53	cache-level = <2>;
	54	};
	55
eed0de27 SS	56	local-timer@0x48240600 {
	57	compatible = "arm,cortex-a9-twd-timer";
	58	reg = <0x48240600 0x20>;
	59	interrupts = <1 13 0x304>;
	60	};
	61
d9fda07a BC	62	/*
	63	* The soc node represents the soc top level view. It is uses for IPs
	64	* that are not memory mapped in the MPU view or for the MPU itself.
	65	*/
	66	soc {
	67	compatible = "ti,omap-infra";
476b679a BC	68	mpu {
	69	compatible = "ti,omap4-mpu";
	70	ti,hwmods = "mpu";
	71	};
	72
	73	dsp {
	74	compatible = "ti,omap3-c64";
	75	ti,hwmods = "dsp";
	76	};
	77
	78	iva {
	79	compatible = "ti,ivahd";
	80	ti,hwmods = "iva";
	81	};
d9fda07a BC	82	};
	83
	84	/*
	85	* XXX: Use a flat representation of the OMAP4 interconnect.
	86	* The real OMAP interconnect network is quite complex.
d9fda07a BC	87	* Since that will not bring real advantage to represent that in DT for
	88	* the moment, just use a fake OCP bus entry to represent the whole bus
	89	* hierarchy.
	90	*/
	91	ocp {
ad8dfac6	92	compatible = "ti,omap4-l3-noc", "simple-bus";
d9fda07a BC	93	#address-cells = <1>;
	94	#size-cells = <1>;
	95	ranges;
ad8dfac6	96	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
d9fda07a	97
510c0ffd JH	98	counter32k: counter@4a304000 {
	99	compatible = "ti,omap-counter32k";
	100	reg = <0x4a304000 0x20>;
	101	ti,hwmods = "counter_32k";
	102	};
	103
679e3310 TL	104	omap4_pmx_core: pinmux@4a100040 {
	105	compatible = "ti,omap4-padconf", "pinctrl-single";
	106	reg = <0x4a100040 0x0196>;
	107	#address-cells = <1>;
	108	#size-cells = <0>;
	109	pinctrl-single,register-width = <16>;
	110	pinctrl-single,function-mask = <0x7fff>;
	111	};
	112	omap4_pmx_wkup: pinmux@4a31e040 {
	113	compatible = "ti,omap4-padconf", "pinctrl-single";
	114	reg = <0x4a31e040 0x0038>;
	115	#address-cells = <1>;
	116	#size-cells = <0>;
	117	pinctrl-single,register-width = <16>;
	118	pinctrl-single,function-mask = <0x7fff>;
	119	};
	120
e3e5a92d BC	121	gpio1: gpio@4a310000 {
e3e5a92d BC	122	compatible = "ti,omap4-gpio";
48420dbc BC	123	reg = <0x4a310000 0x200>;
48420dbc BC	124	interrupts = <0 29 0x4>;
e3e5a92d BC	125	ti,hwmods = "gpio1";
	126	gpio-controller;
	127	#gpio-cells = <2>;
	128	interrupt-controller;
	129	#interrupt-cells = <1>;
	130	};
	131
	132	gpio2: gpio@48055000 {
	133	compatible = "ti,omap4-gpio";
48420dbc BC	134	reg = <0x48055000 0x200>;
48420dbc BC	135	interrupts = <0 30 0x4>;
e3e5a92d BC	136	ti,hwmods = "gpio2";
	137	gpio-controller;
	138	#gpio-cells = <2>;
	139	interrupt-controller;
	140	#interrupt-cells = <1>;
	141	};
	142
	143	gpio3: gpio@48057000 {
	144	compatible = "ti,omap4-gpio";
48420dbc BC	145	reg = <0x48057000 0x200>;
48420dbc BC	146	interrupts = <0 31 0x4>;
e3e5a92d BC	147	ti,hwmods = "gpio3";
	148	gpio-controller;
	149	#gpio-cells = <2>;
	150	interrupt-controller;
	151	#interrupt-cells = <1>;
	152	};
	153
	154	gpio4: gpio@48059000 {
	155	compatible = "ti,omap4-gpio";
48420dbc BC	156	reg = <0x48059000 0x200>;
48420dbc BC	157	interrupts = <0 32 0x4>;
e3e5a92d BC	158	ti,hwmods = "gpio4";
	159	gpio-controller;
	160	#gpio-cells = <2>;
	161	interrupt-controller;
	162	#interrupt-cells = <1>;
	163	};
	164
	165	gpio5: gpio@4805b000 {
	166	compatible = "ti,omap4-gpio";
48420dbc BC	167	reg = <0x4805b000 0x200>;
48420dbc BC	168	interrupts = <0 33 0x4>;
e3e5a92d BC	169	ti,hwmods = "gpio5";
	170	gpio-controller;
	171	#gpio-cells = <2>;
	172	interrupt-controller;
	173	#interrupt-cells = <1>;
	174	};
	175
	176	gpio6: gpio@4805d000 {
	177	compatible = "ti,omap4-gpio";
48420dbc BC	178	reg = <0x4805d000 0x200>;
48420dbc BC	179	interrupts = <0 34 0x4>;
e3e5a92d BC	180	ti,hwmods = "gpio6";
	181	gpio-controller;
	182	#gpio-cells = <2>;
	183	interrupt-controller;
	184	#interrupt-cells = <1>;
	185	};
cf3c79de	186
19bfb76c	187	uart1: serial@4806a000 {
cf3c79de	188	compatible = "ti,omap4-uart";
48420dbc BC	189	reg = <0x4806a000 0x100>;
48420dbc BC	190	interrupts = <0 72 0x4>;
cf3c79de RN	191	ti,hwmods = "uart1";
	192	clock-frequency = <48000000>;
	193	};
	194
19bfb76c	195	uart2: serial@4806c000 {
cf3c79de	196	compatible = "ti,omap4-uart";
48420dbc BC	197	reg = <0x4806c000 0x100>;
48420dbc BC	198	interrupts = <0 73 0x4>;
cf3c79de RN	199	ti,hwmods = "uart2";
	200	clock-frequency = <48000000>;
	201	};
	202
19bfb76c	203	uart3: serial@48020000 {
cf3c79de	204	compatible = "ti,omap4-uart";
48420dbc BC	205	reg = <0x48020000 0x100>;
48420dbc BC	206	interrupts = <0 74 0x4>;
cf3c79de RN	207	ti,hwmods = "uart3";
	208	clock-frequency = <48000000>;
	209	};
	210
19bfb76c	211	uart4: serial@4806e000 {
cf3c79de	212	compatible = "ti,omap4-uart";
48420dbc BC	213	reg = <0x4806e000 0x100>;
48420dbc BC	214	interrupts = <0 70 0x4>;
cf3c79de RN	215	ti,hwmods = "uart4";
	216	clock-frequency = <48000000>;
	217	};
58e778f9 BC	218
	219	i2c1: i2c@48070000 {
	220	compatible = "ti,omap4-i2c";
48420dbc BC	221	reg = <0x48070000 0x100>;
48420dbc BC	222	interrupts = <0 56 0x4>;
58e778f9 BC	223	#address-cells = <1>;
	224	#size-cells = <0>;
	225	ti,hwmods = "i2c1";
	226	};
	227
	228	i2c2: i2c@48072000 {
	229	compatible = "ti,omap4-i2c";
48420dbc BC	230	reg = <0x48072000 0x100>;
48420dbc BC	231	interrupts = <0 57 0x4>;
58e778f9 BC	232	#address-cells = <1>;
	233	#size-cells = <0>;
	234	ti,hwmods = "i2c2";
	235	};
	236
	237	i2c3: i2c@48060000 {
	238	compatible = "ti,omap4-i2c";
48420dbc BC	239	reg = <0x48060000 0x100>;
48420dbc BC	240	interrupts = <0 61 0x4>;
58e778f9 BC	241	#address-cells = <1>;
	242	#size-cells = <0>;
	243	ti,hwmods = "i2c3";
	244	};
	245
	246	i2c4: i2c@48350000 {
	247	compatible = "ti,omap4-i2c";
48420dbc BC	248	reg = <0x48350000 0x100>;
48420dbc BC	249	interrupts = <0 62 0x4>;
58e778f9 BC	250	#address-cells = <1>;
	251	#size-cells = <0>;
	252	ti,hwmods = "i2c4";
	253	};
efcf1e50 BC	254
	255	mcspi1: spi@48098000 {
	256	compatible = "ti,omap4-mcspi";
48420dbc BC	257	reg = <0x48098000 0x200>;
48420dbc BC	258	interrupts = <0 65 0x4>;
efcf1e50 BC	259	#address-cells = <1>;
	260	#size-cells = <0>;
	261	ti,hwmods = "mcspi1";
	262	ti,spi-num-cs = <4>;
	263	};
	264
	265	mcspi2: spi@4809a000 {
	266	compatible = "ti,omap4-mcspi";
48420dbc BC	267	reg = <0x4809a000 0x200>;
48420dbc BC	268	interrupts = <0 66 0x4>;
efcf1e50 BC	269	#address-cells = <1>;
	270	#size-cells = <0>;
	271	ti,hwmods = "mcspi2";
	272	ti,spi-num-cs = <2>;
	273	};
	274
	275	mcspi3: spi@480b8000 {
	276	compatible = "ti,omap4-mcspi";
48420dbc BC	277	reg = <0x480b8000 0x200>;
48420dbc BC	278	interrupts = <0 91 0x4>;
efcf1e50 BC	279	#address-cells = <1>;
	280	#size-cells = <0>;
	281	ti,hwmods = "mcspi3";
	282	ti,spi-num-cs = <2>;
	283	};
	284
	285	mcspi4: spi@480ba000 {
	286	compatible = "ti,omap4-mcspi";
48420dbc BC	287	reg = <0x480ba000 0x200>;
48420dbc BC	288	interrupts = <0 48 0x4>;
efcf1e50 BC	289	#address-cells = <1>;
	290	#size-cells = <0>;
	291	ti,hwmods = "mcspi4";
	292	ti,spi-num-cs = <1>;
	293	};
74981768 RN	294
	295	mmc1: mmc@4809c000 {
	296	compatible = "ti,omap4-hsmmc";
48420dbc BC	297	reg = <0x4809c000 0x400>;
48420dbc BC	298	interrupts = <0 83 0x4>;
74981768 RN	299	ti,hwmods = "mmc1";
	300	ti,dual-volt;
	301	ti,needs-special-reset;
	302	};
	303
	304	mmc2: mmc@480b4000 {
	305	compatible = "ti,omap4-hsmmc";
48420dbc BC	306	reg = <0x480b4000 0x400>;
48420dbc BC	307	interrupts = <0 86 0x4>;
74981768 RN	308	ti,hwmods = "mmc2";
	309	ti,needs-special-reset;
	310	};
	311
	312	mmc3: mmc@480ad000 {
	313	compatible = "ti,omap4-hsmmc";
48420dbc BC	314	reg = <0x480ad000 0x400>;
48420dbc BC	315	interrupts = <0 94 0x4>;
74981768 RN	316	ti,hwmods = "mmc3";
	317	ti,needs-special-reset;
	318	};
	319
	320	mmc4: mmc@480d1000 {
	321	compatible = "ti,omap4-hsmmc";
48420dbc BC	322	reg = <0x480d1000 0x400>;
48420dbc BC	323	interrupts = <0 96 0x4>;
74981768 RN	324	ti,hwmods = "mmc4";
	325	ti,needs-special-reset;
	326	};
	327
	328	mmc5: mmc@480d5000 {
	329	compatible = "ti,omap4-hsmmc";
48420dbc BC	330	reg = <0x480d5000 0x400>;
48420dbc BC	331	interrupts = <0 59 0x4>;
74981768 RN	332	ti,hwmods = "mmc5";
	333	ti,needs-special-reset;
	334	};
94c30732 XJ	335
	336	wdt2: wdt@4a314000 {
	337	compatible = "ti,omap4-wdt", "ti,omap3-wdt";
48420dbc BC	338	reg = <0x4a314000 0x80>;
48420dbc BC	339	interrupts = <0 80 0x4>;
94c30732 XJ	340	ti,hwmods = "wd_timer2";
94c30732 XJ	341	};
4f4b5c74 PU	342
	343	mcpdm: mcpdm@40132000 {
	344	compatible = "ti,omap4-mcpdm";
	345	reg = <0x40132000 0x7f>, /* MPU private access */
	346	<0x49032000 0x7f>; /* L3 Interconnect */
63467cf2	347	reg-names = "mpu", "dma";
4f4b5c74	348	interrupts = <0 112 0x4>;
4f4b5c74 PU	349	ti,hwmods = "mcpdm";
4f4b5c74 PU	350	};
a4c38319 PU	351
	352	dmic: dmic@4012e000 {
	353	compatible = "ti,omap4-dmic";
	354	reg = <0x4012e000 0x7f>, /* MPU private access */
	355	<0x4902e000 0x7f>; /* L3 Interconnect */
63467cf2	356	reg-names = "mpu", "dma";
a4c38319	357	interrupts = <0 114 0x4>;
a4c38319 PU	358	ti,hwmods = "dmic";
a4c38319 PU	359	};
61bc3544	360
2995a100 PU	361	mcbsp1: mcbsp@40122000 {
	362	compatible = "ti,omap4-mcbsp";
	363	reg = <0x40122000 0xff>, /* MPU private access */
	364	<0x49022000 0xff>; /* L3 Interconnect */
	365	reg-names = "mpu", "dma";
	366	interrupts = <0 17 0x4>;
	367	interrupt-names = "common";
2995a100 PU	368	ti,buffer-size = <128>;
	369	ti,hwmods = "mcbsp1";
	370	};
	371
	372	mcbsp2: mcbsp@40124000 {
	373	compatible = "ti,omap4-mcbsp";
	374	reg = <0x40124000 0xff>, /* MPU private access */
	375	<0x49024000 0xff>; /* L3 Interconnect */
	376	reg-names = "mpu", "dma";
	377	interrupts = <0 22 0x4>;
	378	interrupt-names = "common";
2995a100 PU	379	ti,buffer-size = <128>;
	380	ti,hwmods = "mcbsp2";
	381	};
	382
	383	mcbsp3: mcbsp@40126000 {
	384	compatible = "ti,omap4-mcbsp";
	385	reg = <0x40126000 0xff>, /* MPU private access */
	386	<0x49026000 0xff>; /* L3 Interconnect */
	387	reg-names = "mpu", "dma";
	388	interrupts = <0 23 0x4>;
	389	interrupt-names = "common";
2995a100 PU	390	ti,buffer-size = <128>;
	391	ti,hwmods = "mcbsp3";
	392	};
	393
	394	mcbsp4: mcbsp@48096000 {
	395	compatible = "ti,omap4-mcbsp";
	396	reg = <0x48096000 0xff>; /* L4 Interconnect */
	397	reg-names = "mpu";
	398	interrupts = <0 16 0x4>;
	399	interrupt-names = "common";
2995a100 PU	400	ti,buffer-size = <128>;
	401	ti,hwmods = "mcbsp4";
	402	};
	403
61bc3544 SP	404	keypad: keypad@4a31c000 {
61bc3544 SP	405	compatible = "ti,omap4-keypad";
48420dbc BC	406	reg = <0x4a31c000 0x80>;
	407	interrupts = <0 120 0x4>;
	408	reg-names = "mpu";
61bc3544 SP	409	ti,hwmods = "kbd";
61bc3544 SP	410	};
11c27069 A	411
	412	emif1: emif@4c000000 {
	413	compatible = "ti,emif-4d";
48420dbc BC	414	reg = <0x4c000000 0x100>;
48420dbc BC	415	interrupts = <0 110 0x4>;
11c27069 A	416	ti,hwmods = "emif1";
	417	phy-type = <1>;
	418	hw-caps-read-idle-ctrl;
	419	hw-caps-ll-interface;
	420	hw-caps-temp-alert;
	421	};
	422
	423	emif2: emif@4d000000 {
	424	compatible = "ti,emif-4d";
48420dbc BC	425	reg = <0x4d000000 0x100>;
48420dbc BC	426	interrupts = <0 111 0x4>;
11c27069 A	427	ti,hwmods = "emif2";
	428	phy-type = <1>;
	429	hw-caps-read-idle-ctrl;
	430	hw-caps-ll-interface;
	431	hw-caps-temp-alert;
	432	};
8f446a7a	433
3ce0a99c	434	ocp2scp@4a0ad000 {
59bafcf6	435	compatible = "ti,omap-ocp2scp";
3ce0a99c	436	reg = <0x4a0ad000 0x1f>;
59bafcf6 KVA	437	#address-cells = <1>;
	438	#size-cells = <1>;
	439	ranges;
	440	ti,hwmods = "ocp2scp_usb_phy";
cf0d869e KVA	441	usb2_phy: usb2phy@4a0ad080 {
	442	compatible = "ti,omap-usb2";
	443	reg = <0x4a0ad080 0x58>;
	444	ctrl-module = <&omap_control_usb>;
	445	};
59bafcf6	446	};
fab8ad0b JH	447
	448	timer1: timer@4a318000 {
	449	compatible = "ti,omap2-timer";
	450	reg = <0x4a318000 0x80>;
	451	interrupts = <0 37 0x4>;
	452	ti,hwmods = "timer1";
	453	ti,timer-alwon;
	454	};
	455
	456	timer2: timer@48032000 {
	457	compatible = "ti,omap2-timer";
	458	reg = <0x48032000 0x80>;
	459	interrupts = <0 38 0x4>;
	460	ti,hwmods = "timer2";
	461	};
	462
	463	timer3: timer@48034000 {
	464	compatible = "ti,omap2-timer";
	465	reg = <0x48034000 0x80>;
	466	interrupts = <0 39 0x4>;
	467	ti,hwmods = "timer3";
	468	};
	469
	470	timer4: timer@48036000 {
	471	compatible = "ti,omap2-timer";
	472	reg = <0x48036000 0x80>;
	473	interrupts = <0 40 0x4>;
	474	ti,hwmods = "timer4";
	475	};
	476
d03a93bb	477	timer5: timer@40138000 {
fab8ad0b	478	compatible = "ti,omap2-timer";
d03a93bb JH	479	reg = <0x40138000 0x80>,
d03a93bb JH	480	<0x49038000 0x80>;
fab8ad0b JH	481	interrupts = <0 41 0x4>;
	482	ti,hwmods = "timer5";
	483	ti,timer-dsp;
	484	};
	485
d03a93bb	486	timer6: timer@4013a000 {
fab8ad0b	487	compatible = "ti,omap2-timer";
d03a93bb JH	488	reg = <0x4013a000 0x80>,
d03a93bb JH	489	<0x4903a000 0x80>;
fab8ad0b JH	490	interrupts = <0 42 0x4>;
	491	ti,hwmods = "timer6";
	492	ti,timer-dsp;
	493	};
	494
d03a93bb	495	timer7: timer@4013c000 {
fab8ad0b	496	compatible = "ti,omap2-timer";
d03a93bb JH	497	reg = <0x4013c000 0x80>,
d03a93bb JH	498	<0x4903c000 0x80>;
fab8ad0b JH	499	interrupts = <0 43 0x4>;
	500	ti,hwmods = "timer7";
	501	ti,timer-dsp;
	502	};
	503
d03a93bb	504	timer8: timer@4013e000 {
fab8ad0b	505	compatible = "ti,omap2-timer";
d03a93bb JH	506	reg = <0x4013e000 0x80>,
d03a93bb JH	507	<0x4903e000 0x80>;
fab8ad0b JH	508	interrupts = <0 44 0x4>;
	509	ti,hwmods = "timer8";
	510	ti,timer-pwm;
	511	ti,timer-dsp;
	512	};
	513
	514	timer9: timer@4803e000 {
	515	compatible = "ti,omap2-timer";
	516	reg = <0x4803e000 0x80>;
	517	interrupts = <0 45 0x4>;
	518	ti,hwmods = "timer9";
	519	ti,timer-pwm;
	520	};
	521
	522	timer10: timer@48086000 {
	523	compatible = "ti,omap2-timer";
	524	reg = <0x48086000 0x80>;
	525	interrupts = <0 46 0x4>;
	526	ti,hwmods = "timer10";
	527	ti,timer-pwm;
	528	};
	529
	530	timer11: timer@48088000 {
	531	compatible = "ti,omap2-timer";
	532	reg = <0x48088000 0x80>;
	533	interrupts = <0 47 0x4>;
	534	ti,hwmods = "timer11";
	535	ti,timer-pwm;
	536	};
f17c8994 RQ	537
	538	usbhstll: usbhstll@4a062000 {
	539	compatible = "ti,usbhs-tll";
	540	reg = <0x4a062000 0x1000>;
	541	interrupts = <0 78 0x4>;
	542	ti,hwmods = "usb_tll_hs";
	543	};
	544
	545	usbhshost: usbhshost@4a064000 {
	546	compatible = "ti,usbhs-host";
	547	reg = <0x4a064000 0x800>;
	548	ti,hwmods = "usb_host_hs";
	549	#address-cells = <1>;
	550	#size-cells = <1>;
	551	ranges;
	552
	553	usbhsohci: ohci@4a064800 {
	554	compatible = "ti,ohci-omap3", "usb-ohci";
	555	reg = <0x4a064800 0x400>;
	556	interrupt-parent = <&gic>;
	557	interrupts = <0 76 0x4>;
	558	};
	559
	560	usbhsehci: ehci@4a064c00 {
	561	compatible = "ti,ehci-omap", "usb-ehci";
	562	reg = <0x4a064c00 0x400>;
	563	interrupt-parent = <&gic>;
	564	interrupts = <0 77 0x4>;
	565	};
	566	};
840e5fd8 KVA	567
	568	omap_control_usb: omap-control-usb@4a002300 {
	569	compatible = "ti,omap-control-usb";
	570	reg = <0x4a002300 0x4>,
	571	<0x4a00233c 0x4>;
	572	reg-names = "control_dev_conf", "otghs_control";
	573	ti,type = <1>;
	574	};
ad871c10 KVA	575
	576	usb_otg_hs: usb_otg_hs@4a0ab000 {
	577	compatible = "ti,omap4-musb";
	578	reg = <0x4a0ab000 0x7ff>;
	579	interrupts = <0 92 0x4>, <0 93 0x4>;
	580	interrupt-names = "mc", "dma";
	581	ti,hwmods = "usb_otg_hs";
	582	usb-phy = <&usb2_phy>;
	583	multipoint = <1>;
	584	num-eps = <16>;
	585	ram-bits = <12>;
	586	ti,has-mailbox;
	587	};
d9fda07a BC	588	};
d9fda07a BC	589	};