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ARM: dts: omap4-sdp: Move audio related pinmux to respective nodes
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / omap4.dtsi
CommitLineData
d9fda07a
BC		 1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
6d624eab 9#include <dt-bindings/gpio/gpio.h>
8fea7d5a 10#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 11#include <dt-bindings/pinctrl/omap.h>
d9fda07a 12
98ef7957 13#include "skeleton.dtsi"
d9fda07a
BC		 14
15/ {
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>;
18
19 aliases {
20b80942
NM		 20 i2c0 = &i2c1;
21 i2c1 = &i2c2;
22 i2c2 = &i2c3;
23 i2c3 = &i2c4;
cf3c79de
RN		 24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
d9fda07a
BC		 28 };
29
476b679a 30 cpus {
eeb25fd5
LP		 31 #address-cells = <1>;
32 #size-cells = <0>;
33
476b679a
BC		 34 cpu@0 {
35 compatible = "arm,cortex-a9";
eeb25fd5 36 device_type = "cpu";
926fd45b 37 next-level-cache = <&L2>;
eeb25fd5 38 reg = <0x0>;
476b679a
BC		 39 };
40 cpu@1 {
41 compatible = "arm,cortex-a9";
eeb25fd5 42 device_type = "cpu";
926fd45b 43 next-level-cache = <&L2>;
eeb25fd5 44 reg = <0x1>;
476b679a
BC		 45 };
46 };
47
5635121e
BC		 48 gic: interrupt-controller@48241000 {
49 compatible = "arm,cortex-a9-gic";
50 interrupt-controller;
51 #interrupt-cells = <3>;
52 reg = <0x48241000 0x1000>,
53 <0x48240100 0x0100>;
54 };
55
926fd45b
SS		 56 L2: l2-cache-controller@48242000 {
57 compatible = "arm,pl310-cache";
58 reg = <0x48242000 0x1000>;
59 cache-unified;
60 cache-level = <2>;
61 };
62
75d71d46 63 local-timer@48240600 {
eed0de27
SS		 64 compatible = "arm,cortex-a9-twd-timer";
65 reg = <0x48240600 0x20>;
8fea7d5a 66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
eed0de27
SS		 67 };
68
d9fda07a
BC		 69 /*
70 * The soc node represents the soc top level view. It is uses for IPs
71 * that are not memory mapped in the MPU view or for the MPU itself.
72 */
73 soc {
74 compatible = "ti,omap-infra";
476b679a
BC		 75 mpu {
76 compatible = "ti,omap4-mpu";
77 ti,hwmods = "mpu";
78 };
79
80 dsp {
81 compatible = "ti,omap3-c64";
82 ti,hwmods = "dsp";
83 };
84
85 iva {
86 compatible = "ti,ivahd";
87 ti,hwmods = "iva";
88 };
d9fda07a
BC		 89 };
90
91 /*
92 * XXX: Use a flat representation of the OMAP4 interconnect.
93 * The real OMAP interconnect network is quite complex.
d9fda07a
BC		 94 * Since that will not bring real advantage to represent that in DT for
95 * the moment, just use a fake OCP bus entry to represent the whole bus
96 * hierarchy.
97 */
98 ocp {
ad8dfac6 99 compatible = "ti,omap4-l3-noc", "simple-bus";
d9fda07a
BC		 100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
ad8dfac6 103 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 104 reg = <0x44000000 0x1000>,
105 <0x44800000 0x2000>,
106 <0x45000000 0x1000>;
8fea7d5a
FV		 107 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
d9fda07a 109
2488ff6c
TK		 110 cm1: cm1@4a004000 {
111 compatible = "ti,omap4-cm1";
112 reg = <0x4a004000 0x2000>;
113
114 cm1_clocks: clocks {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 };
118
119 cm1_clockdomains: clockdomains {
120 };
121 };
122
123 prm: prm@4a306000 {
124 compatible = "ti,omap4-prm";
125 reg = <0x4a306000 0x3000>;
126
127 prm_clocks: clocks {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 };
131
132 prm_clockdomains: clockdomains {
133 };
134 };
135
136 cm2: cm2@4a008000 {
137 compatible = "ti,omap4-cm2";
138 reg = <0x4a008000 0x3000>;
139
140 cm2_clocks: clocks {
141 #address-cells = <1>;
142 #size-cells = <0>;
143 };
144
145 cm2_clockdomains: clockdomains {
146 };
147 };
148
149 scrm: scrm@4a30a000 {
150 compatible = "ti,omap4-scrm";
151 reg = <0x4a30a000 0x2000>;
152
153 scrm_clocks: clocks {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 };
157
158 scrm_clockdomains: clockdomains {
159 };
160 };
161
510c0ffd
JH		 162 counter32k: counter@4a304000 {
163 compatible = "ti,omap-counter32k";
164 reg = <0x4a304000 0x20>;
165 ti,hwmods = "counter_32k";
166 };
167
679e3310
TL		 168 omap4_pmx_core: pinmux@4a100040 {
169 compatible = "ti,omap4-padconf", "pinctrl-single";
170 reg = <0x4a100040 0x0196>;
171 #address-cells = <1>;
172 #size-cells = <0>;
30a69ef7
TL		 173 #interrupt-cells = <1>;
174 interrupt-controller;
679e3310
TL		 175 pinctrl-single,register-width = <16>;
176 pinctrl-single,function-mask = <0x7fff>;
177 };
178 omap4_pmx_wkup: pinmux@4a31e040 {
179 compatible = "ti,omap4-padconf", "pinctrl-single";
180 reg = <0x4a31e040 0x0038>;
181 #address-cells = <1>;
182 #size-cells = <0>;
30a69ef7
TL		 183 #interrupt-cells = <1>;
184 interrupt-controller;
679e3310
TL		 185 pinctrl-single,register-width = <16>;
186 pinctrl-single,function-mask = <0x7fff>;
187 };
188
2c2dc545
JH		 189 sdma: dma-controller@4a056000 {
190 compatible = "ti,omap4430-sdma";
191 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 192 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 196 #dma-cells = <1>;
197 #dma-channels = <32>;
198 #dma-requests = <127>;
199 };
200
e3e5a92d
BC		 201 gpio1: gpio@4a310000 {
202 compatible = "ti,omap4-gpio";
48420dbc 203 reg = <0x4a310000 0x200>;
8fea7d5a 204 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d 205 ti,hwmods = "gpio1";
e4b9b9f3 206 ti,gpio-always-on;
e3e5a92d
BC		 207 gpio-controller;
208 #gpio-cells = <2>;
209 interrupt-controller;
ff5c9059 210 #interrupt-cells = <2>;
e3e5a92d
BC		 211 };
212
213 gpio2: gpio@48055000 {
214 compatible = "ti,omap4-gpio";
48420dbc 215 reg = <0x48055000 0x200>;
8fea7d5a 216 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 217 ti,hwmods = "gpio2";
218 gpio-controller;
219 #gpio-cells = <2>;
220 interrupt-controller;
ff5c9059 221 #interrupt-cells = <2>;
e3e5a92d
BC		 222 };
223
224 gpio3: gpio@48057000 {
225 compatible = "ti,omap4-gpio";
48420dbc 226 reg = <0x48057000 0x200>;
8fea7d5a 227 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 228 ti,hwmods = "gpio3";
229 gpio-controller;
230 #gpio-cells = <2>;
231 interrupt-controller;
ff5c9059 232 #interrupt-cells = <2>;
e3e5a92d
BC		 233 };
234
235 gpio4: gpio@48059000 {
236 compatible = "ti,omap4-gpio";
48420dbc 237 reg = <0x48059000 0x200>;
8fea7d5a 238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 239 ti,hwmods = "gpio4";
240 gpio-controller;
241 #gpio-cells = <2>;
242 interrupt-controller;
ff5c9059 243 #interrupt-cells = <2>;
e3e5a92d
BC		 244 };
245
246 gpio5: gpio@4805b000 {
247 compatible = "ti,omap4-gpio";
48420dbc 248 reg = <0x4805b000 0x200>;
8fea7d5a 249 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 250 ti,hwmods = "gpio5";
251 gpio-controller;
252 #gpio-cells = <2>;
253 interrupt-controller;
ff5c9059 254 #interrupt-cells = <2>;
e3e5a92d
BC		 255 };
256
257 gpio6: gpio@4805d000 {
258 compatible = "ti,omap4-gpio";
48420dbc 259 reg = <0x4805d000 0x200>;
8fea7d5a 260 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 261 ti,hwmods = "gpio6";
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
ff5c9059 265 #interrupt-cells = <2>;
e3e5a92d 266 };
cf3c79de 267
1c7dbb55
JH		 268 gpmc: gpmc@50000000 {
269 compatible = "ti,omap4430-gpmc";
270 reg = <0x50000000 0x1000>;
271 #address-cells = <2>;
272 #size-cells = <1>;
8fea7d5a 273 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 274 gpmc,num-cs = <8>;
275 gpmc,num-waitpins = <4>;
276 ti,hwmods = "gpmc";
f12ecbe2 277 ti,no-idle-on-init;
1c7dbb55
JH		 278 };
279
19bfb76c 280 uart1: serial@4806a000 {
cf3c79de 281 compatible = "ti,omap4-uart";
48420dbc 282 reg = <0x4806a000 0x100>;
8fea7d5a 283 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 284 ti,hwmods = "uart1";
285 clock-frequency = <48000000>;
286 };
287
19bfb76c 288 uart2: serial@4806c000 {
cf3c79de 289 compatible = "ti,omap4-uart";
48420dbc 290 reg = <0x4806c000 0x100>;
8fea7d5a 291 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 292 ti,hwmods = "uart2";
293 clock-frequency = <48000000>;
294 };
295
19bfb76c 296 uart3: serial@48020000 {
cf3c79de 297 compatible = "ti,omap4-uart";
48420dbc 298 reg = <0x48020000 0x100>;
8fea7d5a 299 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 300 ti,hwmods = "uart3";
301 clock-frequency = <48000000>;
302 };
303
19bfb76c 304 uart4: serial@4806e000 {
cf3c79de 305 compatible = "ti,omap4-uart";
48420dbc 306 reg = <0x4806e000 0x100>;
8fea7d5a 307 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 308 ti,hwmods = "uart4";
309 clock-frequency = <48000000>;
310 };
58e778f9 311
04c7d924
SA		 312 hwspinlock: spinlock@4a0f6000 {
313 compatible = "ti,omap4-hwspinlock";
314 reg = <0x4a0f6000 0x1000>;
315 ti,hwmods = "spinlock";
34054213 316 #hwlock-cells = <1>;
04c7d924
SA		 317 };
318
58e778f9
BC		 319 i2c1: i2c@48070000 {
320 compatible = "ti,omap4-i2c";
48420dbc 321 reg = <0x48070000 0x100>;
8fea7d5a 322 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 323 #address-cells = <1>;
324 #size-cells = <0>;
325 ti,hwmods = "i2c1";
326 };
327
328 i2c2: i2c@48072000 {
329 compatible = "ti,omap4-i2c";
48420dbc 330 reg = <0x48072000 0x100>;
8fea7d5a 331 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 332 #address-cells = <1>;
333 #size-cells = <0>;
334 ti,hwmods = "i2c2";
335 };
336
337 i2c3: i2c@48060000 {
338 compatible = "ti,omap4-i2c";
48420dbc 339 reg = <0x48060000 0x100>;
8fea7d5a 340 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 341 #address-cells = <1>;
342 #size-cells = <0>;
343 ti,hwmods = "i2c3";
344 };
345
346 i2c4: i2c@48350000 {
347 compatible = "ti,omap4-i2c";
48420dbc 348 reg = <0x48350000 0x100>;
8fea7d5a 349 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 350 #address-cells = <1>;
351 #size-cells = <0>;
352 ti,hwmods = "i2c4";
353 };
efcf1e50
BC		 354
355 mcspi1: spi@48098000 {
356 compatible = "ti,omap4-mcspi";
48420dbc 357 reg = <0x48098000 0x200>;
8fea7d5a 358 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 359 #address-cells = <1>;
360 #size-cells = <0>;
361 ti,hwmods = "mcspi1";
362 ti,spi-num-cs = <4>;
2c2dc545
JH		 363 dmas = <&sdma 35>,
364 <&sdma 36>,
365 <&sdma 37>,
366 <&sdma 38>,
367 <&sdma 39>,
368 <&sdma 40>,
369 <&sdma 41>,
370 <&sdma 42>;
371 dma-names = "tx0", "rx0", "tx1", "rx1",
372 "tx2", "rx2", "tx3", "rx3";
efcf1e50
BC		 373 };
374
375 mcspi2: spi@4809a000 {
376 compatible = "ti,omap4-mcspi";
48420dbc 377 reg = <0x4809a000 0x200>;
8fea7d5a 378 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 379 #address-cells = <1>;
380 #size-cells = <0>;
381 ti,hwmods = "mcspi2";
382 ti,spi-num-cs = <2>;
2c2dc545
JH		 383 dmas = <&sdma 43>,
384 <&sdma 44>,
385 <&sdma 45>,
386 <&sdma 46>;
387 dma-names = "tx0", "rx0", "tx1", "rx1";
efcf1e50
BC		 388 };
389
390 mcspi3: spi@480b8000 {
391 compatible = "ti,omap4-mcspi";
48420dbc 392 reg = <0x480b8000 0x200>;
8fea7d5a 393 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 394 #address-cells = <1>;
395 #size-cells = <0>;
396 ti,hwmods = "mcspi3";
397 ti,spi-num-cs = <2>;
2c2dc545
JH		 398 dmas = <&sdma 15>, <&sdma 16>;
399 dma-names = "tx0", "rx0";
efcf1e50
BC		 400 };
401
402 mcspi4: spi@480ba000 {
403 compatible = "ti,omap4-mcspi";
48420dbc 404 reg = <0x480ba000 0x200>;
8fea7d5a 405 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 406 #address-cells = <1>;
407 #size-cells = <0>;
408 ti,hwmods = "mcspi4";
409 ti,spi-num-cs = <1>;
2c2dc545
JH		 410 dmas = <&sdma 70>, <&sdma 71>;
411 dma-names = "tx0", "rx0";
efcf1e50 412 };
74981768
RN		 413
414 mmc1: mmc@4809c000 {
415 compatible = "ti,omap4-hsmmc";
48420dbc 416 reg = <0x4809c000 0x400>;
8fea7d5a 417 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 418 ti,hwmods = "mmc1";
419 ti,dual-volt;
420 ti,needs-special-reset;
2c2dc545
JH		 421 dmas = <&sdma 61>, <&sdma 62>;
422 dma-names = "tx", "rx";
74981768
RN		 423 };
424
425 mmc2: mmc@480b4000 {
426 compatible = "ti,omap4-hsmmc";
48420dbc 427 reg = <0x480b4000 0x400>;
8fea7d5a 428 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 429 ti,hwmods = "mmc2";
430 ti,needs-special-reset;
2c2dc545
JH		 431 dmas = <&sdma 47>, <&sdma 48>;
432 dma-names = "tx", "rx";
74981768
RN		 433 };
434
435 mmc3: mmc@480ad000 {
436 compatible = "ti,omap4-hsmmc";
48420dbc 437 reg = <0x480ad000 0x400>;
8fea7d5a 438 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 439 ti,hwmods = "mmc3";
440 ti,needs-special-reset;
2c2dc545
JH		 441 dmas = <&sdma 77>, <&sdma 78>;
442 dma-names = "tx", "rx";
74981768
RN		 443 };
444
445 mmc4: mmc@480d1000 {
446 compatible = "ti,omap4-hsmmc";
48420dbc 447 reg = <0x480d1000 0x400>;
8fea7d5a 448 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 449 ti,hwmods = "mmc4";
450 ti,needs-special-reset;
2c2dc545
JH		 451 dmas = <&sdma 57>, <&sdma 58>;
452 dma-names = "tx", "rx";
74981768
RN		 453 };
454
455 mmc5: mmc@480d5000 {
456 compatible = "ti,omap4-hsmmc";
48420dbc 457 reg = <0x480d5000 0x400>;
8fea7d5a 458 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 459 ti,hwmods = "mmc5";
460 ti,needs-special-reset;
2c2dc545
JH		 461 dmas = <&sdma 59>, <&sdma 60>;
462 dma-names = "tx", "rx";
74981768 463 };
94c30732
XJ		 464
465 wdt2: wdt@4a314000 {
466 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
48420dbc 467 reg = <0x4a314000 0x80>;
8fea7d5a 468 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
94c30732
XJ		 469 ti,hwmods = "wd_timer2";
470 };
4f4b5c74
PU		 471
472 mcpdm: mcpdm@40132000 {
473 compatible = "ti,omap4-mcpdm";
474 reg = <0x40132000 0x7f>, /* MPU private access */
475 <0x49032000 0x7f>; /* L3 Interconnect */
63467cf2 476 reg-names = "mpu", "dma";
8fea7d5a 477 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
4f4b5c74 478 ti,hwmods = "mcpdm";
4e4ead73
SG		 479 dmas = <&sdma 65>,
480 <&sdma 66>;
481 dma-names = "up_link", "dn_link";
4f4b5c74 482 };
a4c38319
PU		 483
484 dmic: dmic@4012e000 {
485 compatible = "ti,omap4-dmic";
486 reg = <0x4012e000 0x7f>, /* MPU private access */
487 <0x4902e000 0x7f>; /* L3 Interconnect */
63467cf2 488 reg-names = "mpu", "dma";
8fea7d5a 489 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
a4c38319 490 ti,hwmods = "dmic";
4e4ead73
SG		 491 dmas = <&sdma 67>;
492 dma-names = "up_link";
a4c38319 493 };
61bc3544 494
2995a100
PU		 495 mcbsp1: mcbsp@40122000 {
496 compatible = "ti,omap4-mcbsp";
497 reg = <0x40122000 0xff>, /* MPU private access */
498 <0x49022000 0xff>; /* L3 Interconnect */
499 reg-names = "mpu", "dma";
8fea7d5a 500 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
2995a100 501 interrupt-names = "common";
2995a100
PU		 502 ti,buffer-size = <128>;
503 ti,hwmods = "mcbsp1";
4e4ead73
SG		 504 dmas = <&sdma 33>,
505 <&sdma 34>;
506 dma-names = "tx", "rx";
2995a100
PU		 507 };
508
509 mcbsp2: mcbsp@40124000 {
510 compatible = "ti,omap4-mcbsp";
511 reg = <0x40124000 0xff>, /* MPU private access */
512 <0x49024000 0xff>; /* L3 Interconnect */
513 reg-names = "mpu", "dma";
8fea7d5a 514 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
2995a100 515 interrupt-names = "common";
2995a100
PU		 516 ti,buffer-size = <128>;
517 ti,hwmods = "mcbsp2";
4e4ead73
SG		 518 dmas = <&sdma 17>,
519 <&sdma 18>;
520 dma-names = "tx", "rx";
2995a100
PU		 521 };
522
523 mcbsp3: mcbsp@40126000 {
524 compatible = "ti,omap4-mcbsp";
525 reg = <0x40126000 0xff>, /* MPU private access */
526 <0x49026000 0xff>; /* L3 Interconnect */
527 reg-names = "mpu", "dma";
8fea7d5a 528 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
2995a100 529 interrupt-names = "common";
2995a100
PU		 530 ti,buffer-size = <128>;
531 ti,hwmods = "mcbsp3";
4e4ead73
SG		 532 dmas = <&sdma 19>,
533 <&sdma 20>;
534 dma-names = "tx", "rx";
2995a100
PU		 535 };
536
537 mcbsp4: mcbsp@48096000 {
538 compatible = "ti,omap4-mcbsp";
539 reg = <0x48096000 0xff>; /* L4 Interconnect */
540 reg-names = "mpu";
8fea7d5a 541 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2995a100 542 interrupt-names = "common";
2995a100
PU		 543 ti,buffer-size = <128>;
544 ti,hwmods = "mcbsp4";
4e4ead73
SG		 545 dmas = <&sdma 31>,
546 <&sdma 32>;
547 dma-names = "tx", "rx";
2995a100
PU		 548 };
549
61bc3544
SP		 550 keypad: keypad@4a31c000 {
551 compatible = "ti,omap4-keypad";
48420dbc 552 reg = <0x4a31c000 0x80>;
8fea7d5a 553 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
48420dbc 554 reg-names = "mpu";
61bc3544
SP		 555 ti,hwmods = "kbd";
556 };
11c27069
A		 557
558 emif1: emif@4c000000 {
559 compatible = "ti,emif-4d";
48420dbc 560 reg = <0x4c000000 0x100>;
8fea7d5a 561 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
11c27069 562 ti,hwmods = "emif1";
f12ecbe2 563 ti,no-idle-on-init;
11c27069
A		 564 phy-type = <1>;
565 hw-caps-read-idle-ctrl;
566 hw-caps-ll-interface;
567 hw-caps-temp-alert;
568 };
569
570 emif2: emif@4d000000 {
571 compatible = "ti,emif-4d";
48420dbc 572 reg = <0x4d000000 0x100>;
8fea7d5a 573 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
11c27069 574 ti,hwmods = "emif2";
f12ecbe2 575 ti,no-idle-on-init;
11c27069
A		 576 phy-type = <1>;
577 hw-caps-read-idle-ctrl;
578 hw-caps-ll-interface;
579 hw-caps-temp-alert;
580 };
8f446a7a 581
3ce0a99c 582 ocp2scp@4a0ad000 {
59bafcf6 583 compatible = "ti,omap-ocp2scp";
3ce0a99c 584 reg = <0x4a0ad000 0x1f>;
59bafcf6
KVA		 585 #address-cells = <1>;
586 #size-cells = <1>;
587 ranges;
588 ti,hwmods = "ocp2scp_usb_phy";
cf0d869e
KVA		 589 usb2_phy: usb2phy@4a0ad080 {
590 compatible = "ti,omap-usb2";
591 reg = <0x4a0ad080 0x58>;
470019a4 592 ctrl-module = <&omap_control_usb2phy>;
975d963e 593 #phy-cells = <0>;
cf0d869e 594 };
59bafcf6 595 };
fab8ad0b
JH		 596
597 timer1: timer@4a318000 {
002e1ec5 598 compatible = "ti,omap3430-timer";
fab8ad0b 599 reg = <0x4a318000 0x80>;
8fea7d5a 600 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 601 ti,hwmods = "timer1";
602 ti,timer-alwon;
603 };
604
605 timer2: timer@48032000 {
002e1ec5 606 compatible = "ti,omap3430-timer";
fab8ad0b 607 reg = <0x48032000 0x80>;
8fea7d5a 608 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 609 ti,hwmods = "timer2";
610 };
611
612 timer3: timer@48034000 {
002e1ec5 613 compatible = "ti,omap4430-timer";
fab8ad0b 614 reg = <0x48034000 0x80>;
8fea7d5a 615 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 616 ti,hwmods = "timer3";
617 };
618
619 timer4: timer@48036000 {
002e1ec5 620 compatible = "ti,omap4430-timer";
fab8ad0b 621 reg = <0x48036000 0x80>;
8fea7d5a 622 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 623 ti,hwmods = "timer4";
624 };
625
d03a93bb 626 timer5: timer@40138000 {
002e1ec5 627 compatible = "ti,omap4430-timer";
d03a93bb
JH		 628 reg = <0x40138000 0x80>,
629 <0x49038000 0x80>;
8fea7d5a 630 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 631 ti,hwmods = "timer5";
632 ti,timer-dsp;
633 };
634
d03a93bb 635 timer6: timer@4013a000 {
002e1ec5 636 compatible = "ti,omap4430-timer";
d03a93bb
JH		 637 reg = <0x4013a000 0x80>,
638 <0x4903a000 0x80>;
8fea7d5a 639 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 640 ti,hwmods = "timer6";
641 ti,timer-dsp;
642 };
643
d03a93bb 644 timer7: timer@4013c000 {
002e1ec5 645 compatible = "ti,omap4430-timer";
d03a93bb
JH		 646 reg = <0x4013c000 0x80>,
647 <0x4903c000 0x80>;
8fea7d5a 648 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 649 ti,hwmods = "timer7";
650 ti,timer-dsp;
651 };
652
d03a93bb 653 timer8: timer@4013e000 {
002e1ec5 654 compatible = "ti,omap4430-timer";
d03a93bb
JH		 655 reg = <0x4013e000 0x80>,
656 <0x4903e000 0x80>;
8fea7d5a 657 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 658 ti,hwmods = "timer8";
659 ti,timer-pwm;
660 ti,timer-dsp;
661 };
662
663 timer9: timer@4803e000 {
002e1ec5 664 compatible = "ti,omap4430-timer";
fab8ad0b 665 reg = <0x4803e000 0x80>;
8fea7d5a 666 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 667 ti,hwmods = "timer9";
668 ti,timer-pwm;
669 };
670
671 timer10: timer@48086000 {
002e1ec5 672 compatible = "ti,omap3430-timer";
fab8ad0b 673 reg = <0x48086000 0x80>;
8fea7d5a 674 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 675 ti,hwmods = "timer10";
676 ti,timer-pwm;
677 };
678
679 timer11: timer@48088000 {
002e1ec5 680 compatible = "ti,omap4430-timer";
fab8ad0b 681 reg = <0x48088000 0x80>;
8fea7d5a 682 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 683 ti,hwmods = "timer11";
684 ti,timer-pwm;
685 };
f17c8994
RQ		 686
687 usbhstll: usbhstll@4a062000 {
688 compatible = "ti,usbhs-tll";
689 reg = <0x4a062000 0x1000>;
8fea7d5a 690 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
f17c8994
RQ		 691 ti,hwmods = "usb_tll_hs";
692 };
693
694 usbhshost: usbhshost@4a064000 {
695 compatible = "ti,usbhs-host";
696 reg = <0x4a064000 0x800>;
697 ti,hwmods = "usb_host_hs";
698 #address-cells = <1>;
699 #size-cells = <1>;
700 ranges;
701
702 usbhsohci: ohci@4a064800 {
703 compatible = "ti,ohci-omap3", "usb-ohci";
704 reg = <0x4a064800 0x400>;
705 interrupt-parent = <&gic>;
8fea7d5a 706 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
f17c8994
RQ		 707 };
708
709 usbhsehci: ehci@4a064c00 {
710 compatible = "ti,ehci-omap", "usb-ehci";
711 reg = <0x4a064c00 0x400>;
712 interrupt-parent = <&gic>;
8fea7d5a 713 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
f17c8994
RQ		 714 };
715 };
840e5fd8 716
470019a4
RQ		 717 omap_control_usb2phy: control-phy@4a002300 {
718 compatible = "ti,control-phy-usb2";
719 reg = <0x4a002300 0x4>;
720 reg-names = "power";
721 };
722
723 omap_control_usbotg: control-phy@4a00233c {
724 compatible = "ti,control-phy-otghs";
725 reg = <0x4a00233c 0x4>;
726 reg-names = "otghs_control";
840e5fd8 727 };
ad871c10
KVA		 728
729 usb_otg_hs: usb_otg_hs@4a0ab000 {
730 compatible = "ti,omap4-musb";
731 reg = <0x4a0ab000 0x7ff>;
8fea7d5a 732 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
ad871c10
KVA		 733 interrupt-names = "mc", "dma";
734 ti,hwmods = "usb_otg_hs";
735 usb-phy = <&usb2_phy>;
975d963e
KVA		 736 phys = <&usb2_phy>;
737 phy-names = "usb2-phy";
ad871c10
KVA		 738 multipoint = <1>;
739 num-eps = <16>;
740 ram-bits = <12>;
470019a4 741 ctrl-module = <&omap_control_usbotg>;
ad871c10 742 };
dd6317df
JF		 743
744 aes: aes@4b501000 {
745 compatible = "ti,omap4-aes";
746 ti,hwmods = "aes";
747 reg = <0x4b501000 0xa0>;
748 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
749 dmas = <&sdma 111>, <&sdma 110>;
750 dma-names = "tx", "rx";
751 };
806e9431
JF		 752
753 des: des@480a5000 {
754 compatible = "ti,omap4-des";
755 ti,hwmods = "des";
756 reg = <0x480a5000 0xa0>;
757 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
758 dmas = <&sdma 117>, <&sdma 116>;
759 dma-names = "tx", "rx";
760 };
d9fda07a
BC		 761 };
762};
2488ff6c
TK		 763
764/include/ "omap44xx-clocks.dtsi"
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